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Chapter 4 Sequential Statements

Chapter 4 Sequential Statements

Variable assignment Variable assignment statement statement

Signal assignment Signal assignment statement statement

If statementIf statement Case statementCase statement Loop statementLoop statement Next statementNext statement

Exit statementExit statement Null statementNull statement Return statementReturn statement Procedure call Procedure call

statementstatement Assertion statementAssertion statement Wait statement Wait statement ExercisesExercises

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Null statementNull statement

Null_statement::=Null_statement::=nullnull;;Note:Note:

Null Null is used to explicitly specify that no is used to explicitly specify that no action is to be performed. This is especially action is to be performed. This is especially useful in the useful in the case statementcase statement when no action when no action is required for a choice.is required for a choice.

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Return statementReturn statement

Return_statement::=return [expression];

Note:

A return statement is used to complete the execution of the innermost enclosing function or procedure body. It is allowed only within the body of a function or a procedure.

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Function and procedure call statements

Function and procedure call statements

entity RETURNSTMT isend RETURNSTMT;architecture RTL of RETURNSTMT is function BOOL2BIT (BOOL : in boolean) return bit is begin if BOOL then return '1'; else return '0'; end if; end BOOL2BIT; procedure EVEN_PARITY ( signal DATA : in bit_vector(7 downto 0);

signal PARITY : out bit) is variable temp : bit;begin temp := DATA(0); for i in 1 to 7 loop temp := temp xor DATA(i); end loop; PARITY <= temp; return; end EVEN_PARITY; signal DIN : bit_vector(7 downto 0); signal BOOL1 : boolean; signal BIT1, PARITY : bit;

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Procedure call statementProcedure call statementbegin doit : process (BOOL1, DIN) begin BIT1 <= BOOL2BIT(BOOL1); EVEN_PARITY(DIN, PARITY); end process; vector : process begin

BOOL1 <= TRUE after 10 ns, FALSE after 20 ns; DIN <= "00011111" after 10 ns,

"11001101" after 20 ns, "11111111"

after 30 ns, "10000011" after 40 ns; wait for 50 ns; end process;end RTL;

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Assertion statementAssertion statement

assertion_statement::=ssertion_statement::=assert assert condition condition [[report report expression][expression][severity severity expression];expression];

Note:Note: The report expression is an expression of a

STRING type to be reported. The severity expression is an enumerated type with four values NOTE, WARNING, ERROR and FAILURE. The default severity level is ERROR if the severity clause is not specified.

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Assertion statementAssertion statemententity ASRTSTMT isend ASRTSTMT;architecture BEH of ASRTSTMT is constant SETUP : time := 3 ns; constant HOLD : time := 3 ns; signal D, CLOCK, Q : bit;begin setup_check : process (CLOCK) begin assert FALSE report "Event on CLOCK"

severity NOTE; if (CLOCK'event and CLOCK = '1') then assert D'STABLE(SETUP) report "D setup error" severity WARNING; if (D'STABLE(SETUP)) then Q <= D; end if; end if; end process;

hold_check : process begin wait on D; assert FALSE report "Event on D" severity NOTE; if (CLOCK = '1') then assert (CLOCK'LAST_EVENT > HOLD) report "D hold error" severity

WARNING; end if; end process; vector : process begin CLOCK <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns; D <= '1' after 8 ns, '0' after 12 ns, '1' after 15 ns; wait; end process;end BEH;

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Assertion statementAssertion statement

if (CLOCK'event and CLOCK = '1') then

assert D'STABLE(SETUP)

report "D setup error" severity WARNING;

assert FALSE report "Event on D" severity NOTE;

if (CLOCK = '1') then

assert (CLOCK'LAST_EVENT > HOLD)

report "D hold error" severity WARNING;

DCKQ

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Assertion statementAssertion statement

OutputOutput::Assertion NOTE at 0 NS in design unit ASRTSTMT(BEH)from Assertion NOTE at 0 NS in design unit ASRTSTMT(BEH)from

process/ASRTSTMT/SETUP_CHECK:”Event on CLOCK”process/ASRTSTMT/SETUP_CHECK:”Event on CLOCK”

Assertion NOTE at 8 NS in design unit ASRTSTMT(BEH)from Assertion NOTE at 8 NS in design unit ASRTSTMT(BEH)from process/ASRTSTMT/HOLD_CHECK:”Event on D”process/ASRTSTMT/HOLD_CHECK:”Event on D”

Assertion NOTE at 10 NS in design unit ASRTSTMT(BEH)from Assertion NOTE at 10 NS in design unit ASRTSTMT(BEH)from process/ASRTSTMT/SETUP_CHECK:”Event on CLOCK”process/ASRTSTMT/SETUP_CHECK:”Event on CLOCK”

Assertion WARNING at 10 NS in design unit ASRTSTMT(BEH)from Assertion WARNING at 10 NS in design unit ASRTSTMT(BEH)from process/ASRTSTMT/SETUP_CHECK:”D setup error”process/ASRTSTMT/SETUP_CHECK:”D setup error”

Assertion NOTE at 12 NS in design unit ASRTSTMT(BEH)from Assertion NOTE at 12 NS in design unit ASRTSTMT(BEH)from process/ASRTSTMT/HOLD_CHECK:”Event on D”process/ASRTSTMT/HOLD_CHECK:”Event on D”

Assertion WARNING at 12 NS in design unit ASRTSTMT(BEH)from Assertion WARNING at 12 NS in design unit ASRTSTMT(BEH)from process/ASRTSTMT/HOLD_CHECK:”D hold error”process/ASRTSTMT/HOLD_CHECK:”D hold error”

Assertion NOTE at 15 NS in design unit ASRTSTMT(BEH)from Assertion NOTE at 15 NS in design unit ASRTSTMT(BEH)from process/ASRTSTMT/HOLD_CHECK:”Event on D”process/ASRTSTMT/HOLD_CHECK:”Event on D”

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Wait statementWait statement

wait_statement::=wait_statement::=wait wait [sensitivity_clause][sensitivity_clause][conditional_clause][conditional_clause]

[timout_clause];[timout_clause];

sensitivity_clause::=sensitivity_clause::=on on sensitivity_listsensitivity_list

conditional_clause::=conditional_clause::=until until boolean_expressionboolean_expression

timout_clause::=timout_clause::=for for time_expressiontime_expression

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Wait statementWait statement

entity WAITSTMT is port ( CLOCK : in bit; A, B, C, D : in bit; Q, W, X, Y, Z : out bit);end WAITSTMT;architecture BEH of WAITSTMT is constant PERIOD : time := 30 ns;begin dff : process begin wait until CLOCK'event and CLOCK = '1'; Q <= D; end process; nand0 : process (A, B) begin W <= A nand B; end process;

nand1 : process begin X <= A nand B; wait on A, B; end process; more : process begin wait on A, B until (C or D) = '0' for 100 ns; Y <= A or B; wait until A = '0' for PERIOD; wait on C for 50 * PERIOD; wait on A until B = '1'; Z <= A or (C and D); wait for 2 * PERIOD; end process; forever : process

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Wait statementWait statement

begin

-- do something once

if (A and B and C and D) = '1' then

wait;

else

wait for PERIOD;

end if;

end process;

end BEH;

Note One:

There must be a way to suspend a process to avoid an infinite simulation loop. wait statement causes the suspension of a process statement or a procedure.

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Wait statementWait statement

entity IFWAIT isend IFWAIT;architecture RTL of IFWAIT is signal CLK : bit; signal SEL : bit_vector(1 downto 0);begin p0 : process begin if SEL = "00" then wait until CLK'event and CLK = '1'; elsif SEL = "01" then wait for 60 ns; else null; end if; end process;end RTL;

Note Two: Be careful when wait statement are used in different conditions of if statements. On the left, if SEL(1)=‘1’, the process will run forever.

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ExercisesExercises

--Counter VHDL ibrary IEEE;                --library definition use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Counter is         --entity definition   port (     clk:in std_logic;     reset: in std_logic;     q: out std_logic_vector(3 downto 0)     ); end Counter; architecture Counter of Counter is    begin       process(clk,reset)                      variable qtemp: std_logic_vector(3 downto 0);   -- temporary variable for output q[3..0]  

begin    if reset='1' then     qtemp:="0000";                  -- Reset asychroniously    else     if clk'event and clk='1' then             -- Counting state      if qtemp<9 then       qtemp:=qtemp+1;              -- Counter increase      else       qtemp:="0000";                             -- Return the zero state      end if;     end if;    q<=qtemp;                                        -- Output     end if;   end process;                                       -- End Process end Counter;                                        -- End Architecture

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ExercisesExercises

entity JKFF is port ( CLK, RSTn, J, K : in bit; Q : out bit);end JKFF;-------------------------------------------------architecture RTL of JKFF is signal FF : bit;begin process (CLK, RSTn) variable JK : bit_vector(1 downto 0); begin if (RSTn = '0') then FF <= '0'; elsif (CLK'event and CLK = '1') then JK := J & K; case JK is when "01" => FF <= '0'; when "10" => FF <= '1'; when "11" => FF <= not FF; when "00" => FF <= FF; end case;end if; end process;

Q <= FF;end RTL;-------------------------------------------------architecture RTL1 of JKFF is signal FF : bit;begin process (CLK, RSTn) begin if (RSTn = '0') then FF <= '0'; Q <= '0'; elsif (CLK'event and CLK = '1') then if (J = '1') and (K = '1') then FF <= not FF; elsif (J = '1') and (K = '0') then FF <= '1'; elsif (J = '0') and (K = '1') then FF <= '0'; end if; end if; Q <= FF; end process;end RTL1;