1.5 giga hertz ultra high speed adc testing on atesoc.yonsei.ac.kr/test/papers/6th/g-2 ate ac signal...
TRANSCRIPT
2005. 7. 1. Jin-Soo Ko 제 6 회 테스트 학술 대회1
1.5 Giga Hertz Ultra High Speed ADC Testing on ATE
Jin-Soo KoTeradyn Inc.
제 6 회 테스트 학술 대회22005. 7. 1. Jin-Soo Ko
Contents
w Giga Hertz ADC Overvieww Challenges to ATE Systemsw Tiger Mixed Signal Instruments Introduction w Device Test Requirementsw Tiger System Configurationw DIB Design Techniquew Dynamic Testing Resultsw Conclusion
제 6 회 테스트 학술 대회32005. 7. 1. Jin-Soo Ko
Giga Hertz ADC Overview
w Flash, Folding Architecturesw 6 to 10 Bit Resolutionw ~500MHz to 2~3 GHz Sample Ratew Bipolar, SiGe, CMOS Processesw Differential Analog Input, Differential
Digital Output, Differential Clockw BGA, LQFP Packages
제 6 회 테스트 학술 대회42005. 7. 1. Jin-Soo Ko
Giga Hertz ADC Applications
w Direct RF Down Conversionw Digital RF/IF Signal Processingw Satellite Set-top Boxesw Electronic Countermeasures/Electronic
Warfarew High Speed Data Acquisitionw ATE Systemsw Digital Oscilloscopesw …
제 6 회 테스트 학술 대회52005. 7. 1. Jin-Soo Ko
Test System Requirements
w High Frequency High Performance Sine Wave Signal Generatorw Low Jitter High Frequency Clock Generatorw Ultra High Speed Digital Pin Electronics
with DSSC ( Digital Signal Source and capture) Capabilitiesw Differential Analog & Digital Capabilities
제 6 회 테스트 학술 대회62005. 7. 1. Jin-Soo Ko
AC Instruments for GHz ADC Testing
AC Instrument Description
LFAC 1.2 MHz, 90 dB Source and Dig
BBAC DC to 15 MHz Source and Digitizer
VHFCW 250 MHz CW Source
AWGLAN Octal Diff Outputs, 250 MHz BW
AWG2500 10-bit, 2500 Msps, DC to 1400 MHzBW
3.2GHz CW Src Microwave Sine Wave Source
PicoClock 1 GHz Clock, <1.5 pS rms Jitter
제 6 회 테스트 학술 대회72005. 7. 1. Jin-Soo Ko
DPE32: Differential Pin Electronics
Differential Driver6-Level Output Waveform
Differential ComparatorPass/Fail Signal
1.6 GbpsDrive/Compare/ IO
High Speed Differential Digital Instruments for GHz ADC Testing
제 6 회 테스트 학술 대회82005. 7. 1. Jin-Soo Ko
“V” means compare to LOW or HIGH and send data to capture memory
Tiger DSSC - Digital Signal I/O
10110HLHLXX---10110H--HHLHL------111-----X00XXXXX---11101000000LHH10110HLHLXX---10110H--HHLHL------111-----X00
REPEAT 32 10110HLHLXXWWWWWWWWWWW10110HLHLXX---10110H--HHLHL------111-----X00XXXXX---11101000000LHH10110HLHLXX---10110H--HHLHL------111-----X00XXXXX---11101000000LHH10110HLHLXX---10110H--HHLHL------111-----X00
REPEAT 32 10110HLHLXXVVVVVVVVVVV10110HLHLXX---10110H--HHLHL------111-----X00XXXXX---11101000000LHH
010000001100101011000111110110110010000000010011011011011100110100..
“W” means substitute data from the source segment memory
?????????????????????????????????????????????????????????????????????????????..
DUT needs a specific ‘waveform’
‘Captured waveform’ to be processed.
Result is a ‘performance’measurement like SNR
Functional Testing
Digital Signal Segment #132 samples
Digital Signal Capture #132 samples
FunctionalTest Requirement
PerformanceTest Requirement
제 6 회 테스트 학술 대회92005. 7. 1. Jin-Soo Ko
Tiger DC Instruments
DC Instruments Quantity Description
AAPU’s Up to 48 ±30 V, ±30 mA
VI Up to 7 ±60 V, ±200 mA
HCU Up to 4 ±30 V, ±2 A
Quad Voltage Source Up to 8 +6 V, 5 A(QVS) Sources Gangable to 10 A
High Current Power Up to 24 8 @ 6 A per board,Supplies (HCPS) Sources Gangable to 48 A
제 6 회 테스트 학술 대회102005. 7. 1. Jin-Soo Ko
Device Test Requirements
w 1.5Gsps, 8Bit ADCw INL, DNL < 1.0 LSBw Dynamic Testing @ fi = 250MHz, fs = 1.5GHz
n SNR > 45 dBn THD < -50 dBn SFDR < -50 dBn SINAD > 44 dBn ENOB > 7.0 LSBn IMD < -66.8dBc
제 6 회 테스트 학술 대회112005. 7. 1. Jin-Soo Ko
Test Setup
CW
AWG
Ext. Src
Ext. Clk
HSD
Pico Clk
BPF
DIGCAP
DIGCAP
DUT
QVS, dutsrc, duthcu, etc
w DUT Input, Output, CLK are Differential
w DIGCAP: Parallel Octal Moden 4 Bit Widthn 2 for Primary Data
Outputn 2 for Auxiliary
Data Outputn 750Msps Data Rate
w High Freq Relays Controlled by SDBs
w BPF: Low distortion CW signal shaping
제 6 회 테스트 학술 대회122005. 7. 1. Jin-Soo Ko
Dual Tone Generation
w Multi-Site Parallel Testing
w High Quality Dual Tone Generation
w Improving IMD Performance by Using 2 Independent Sources
w CW Source:n 250MHz Rangen 1 Hz Stepn 12Bit Resolution
w Combiner/Splitter
CW2
CW1
Combiner Splitter
f1
f2f1 f2
f1 f2f1 f2
To Site #0
To Site #1
vhfawgvhfcw
제 6 회 테스트 학술 대회132005. 7. 1. Jin-Soo Ko
DIB Design Information
w Dual Site Designw 20 Layers:
n 8 GND Layersn 4 Power Layersn 6 Internal Layersn 1 Component Siden 1 Solder Side
w Single GND Planew Splitted PWR Planesw Avoid through holesw Matching impedance
Site #0Site #1
BPF
Ext. ClkInput
Ext. Sig. Input
High Speed Relays
Combiner/Splitter
제 6 회 테스트 학술 대회142005. 7. 1. Jin-Soo Ko
PECL Digital Output Termination
•Differential drive
•Force high
• common mode 1.3v (device spec)
•50 Ohm termination
Drive Side:
Receive Side:•Differential Receive
•Compare pattern
•Vod = 0.2v (device Spec)
제 6 회 테스트 학술 대회152005. 7. 1. Jin-Soo Ko
Dynamic Test Pattern
Pattern Running in T8 ModeDIGCAPs for
Primary Data Output
DIGCAPs for Auxiliary Data Output
제 6 회 테스트 학술 대회162005. 7. 1. Jin-Soo Ko
External Instrument Integration
Marconi 2026
CableTrunk
ATEMainframe
ATETesthead
Generic CC/Cardletfor signal delivery
10M Ref.
DIB
제 6 회 테스트 학술 대회172005. 7. 1. Jin-Soo Ko
Test Results: CW Src for Fs=0.8GHz
w Fs=0.8GHz fi=250MHz,
제 6 회 테스트 학술 대회182005. 7. 1. Jin-Soo Ko
Test Results: Ext Src for Fs=0.8GHz
w Fs=0.8GHz fi=250MHz,
제 6 회 테스트 학술 대회192005. 7. 1. Jin-Soo Ko
Test Results: CW Src for Fs=1.5GHz
SNR = 45.72dB
THD =-67.84dB
SFDR =-57.88dB
SINAD = 45.70dB
ENOB = 7.30dB
w Fs=1.5GHz fi=250MHz,
제 6 회 테스트 학술 대회202005. 7. 1. Jin-Soo Ko
Test Results: Ext Src for Fs=1.5GHz
w Fs=1.5GHz fi=250MHz,
SNR = 47.45dB
THD =-67.31dB
SFDR =-63.45dB
SINAD = 47.41dB
ENOB = 7.58dB
제 6 회 테스트 학술 대회212005. 7. 1. Jin-Soo Ko
Dual Tone IMD Testing Resultsw Fs = 1.5GHzw Fi1 = 249.5MHzw Fi2 = 250.5MHzw IMD <= -67dBw Clk Src: Marconi 2026w Sig Src: HP8644B