Logix5000 Controllers Execution Time and Memory Use Reference Manual1756 ControlLogix, 1769 CompactLogix, 1794 FlexLogix, 20D PowerFlex 700S with DriveLogix

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Introducton

Logix5000 Controllers Execution Time and Memory Use Reference Manual

1756 ControlLogix, 1769 CompactLogix, 1794 FlexLogix, 20D PowerFlex 700S with DriveLogix

The memory use of a project is the same regardless of which Logix5000 controller you are using (CompactLogix, FlexLogix, etc). However the execution times vary based on controller type.

Important User Information

Solid state equipment has operational characteristics differing from those of electromechanical equipment. Safety Guidelines for the Application, Installation and Maintenance of Solid State Controls (Publication SGI-1.1 available from your local Rockwell Automation sales office or online at http://www.ab.com/manuals/gi) describes some important differences between solid state equipment and hard-wired electromechanical devices. Because of this difference, and also because of the wide variety of uses for solid state equipment, all persons responsible for applying this equipment must satisfy themselves that each intended application of this equipment is acceptable.

In no event will Rockwell Automation, Inc. be responsible or liable for indirect or consequential damages resulting from the use or application of this equipment.

The examples and diagrams in this manual are included solely for illustrative purposes. Because of the many variables and requirements associated with any particular installation, Rockwell Automation, Inc. cannot assume responsibility or liability for actual use based on the examples and diagrams.

No patent liability is assumed by Rockwell Automation, Inc. with respect to use of information, circuits, equipment, or software described in this manual.

Reproduction of the contents of this manual, in whole or in part, without written permission of Rockwell Automation, Inc. is prohibited.

About this manual

Use these worksheets to estimate the memory use and execution time of your logic. Use this information to select among different programming options.

The information in these worksheets is based on RSLogix 5000 software revision 13 and controller firmware revision 13. One exception is the equipment phase instructions. Their information is based on revision 15. Actual results may vary because of the configuration of your project and the revision of software and firmware that you are using.

ImportantThe 1756-L63 controller uses a cache mechanism to enhance the performance of instructions. Actual performance depends on how sequentially the data is laid out and how frequently it is accessed.

Caching has a significant impact on the execution times of bit instructions (XIC, XIO, OTE, OTU, OTL). For example, an XIC instruction has a best case execution time of 0.05 s, where the project takes full advantage of caching. The XIC instruction has a worst-case execution time of 0.4 s, where the project uses minimal caching. The typical execution time of an XIC instruction is approximately 0.1 s

When you download your project, the controller optimizes memory use, which could reduce your calculated memory use by as much as 10% from the values presented in this worksheet.

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Examples

Ladder InstructionsHere are some examples for a 1756-L63 controller:

Example:Data Type:Memory (bytes):Execution time (s):Description:

ADDDINT280.26ADD instruction

Source ADINT

Source BDINT

DestinationDINT

280.26total

Array subscriptsWhen an array uses a tag for one of its subsrcipts (e.g., Array_A[Tag_B]), additional memory and execution time is required, depending on the number of dimensions in the array. Memory use and execution time for an instruction increases for each parameter that references an array.

Example:Data Type:Memory (bytes):Execution time (s):Description:

ADDDINT280.26ADD instruction

Source ADINT[DINT]840.69array subscript

Source BDINT

DestinationDINT

1120.95total

ExpressionsIf an instruction contains an expression (CMP, CPT, FAL, FSC), than add memory and time for each operator in the expression. For each operator, use the values for the corresponding instruction.

Here is an example for a 1756-L63 controller:

Example:Data Type:Memory (bytes):Execution time (s):Description:

CPT (tag_a + tag_b)761.65CPT instruction

ADD (+)DINT280.26ADD operator

1041.90total

Data conversionsLogix5000 controllers typically compare or manipulate values as DINTs or REALs (optimal data type).

If you use a data type that is not an optimal data type or if you mix data types, you must add memory and execution time for data conversion.

If you use mix integers and REALs in an instruction, the controller converts the values to REALs and then back to the destination data type.

Example:Data Type:Memory (bytes):Execution time (s):Description:

ADDREAL441.52ADD instruction

Source ADINT962.40DINT to REAL conversion

Source BREAL

DestinationREAL

1403.92total

ADDREAL441.52ADD instruction

Source ADINT962.40DINT to REAL conversion

Source BREAL

DestinationDINT923.50REAL to DINT conversion

2327.43total

ADDDINT280.26ADD instruction

Source AINT800.52INT to DINT conversion

Source BINT800.52INT to DINT conversion

DestinationINT722.24DINT to INT conversion

2603.53total

Function Block ElementsFunction block elements include the following:

Function Block Instructions -These times include only the time for the instruction. They do not include time for IREFs, OREFs, or wires.Use the same times regardless of whether the function block is in a function block diagram or structured text.

IREFs and OREFs -Choose the time for the IREF or OREF based on the data type of its tag. Do not add any time for immediate values.

Wires -Choose the time for a wire based on the data type at each end of the wire pin).

Here is an example of a function block diagram for a 1756-L63 controller:

Structured TextThe number and complexity of the assignments, instructions, and comments included in the construct increases the memory and execution time that are required.

Here's examples for a 1756-L63 controller:

Example:Data Type:Memory (bytes):Execution time (s):Description:

Tag_A := Tag_B;DINT920.27simple assignment

Tag_ADINT

Tag_BDINT

920.27total

Example:Data Type:Memory (bytes):Execution time (s):Description:

Tag_A := Tag_B + Tag_C;Complex assignment. Use the numbers for the CPT instruction plus the numbers for the ADD instruction.

Tag_ADINT

Tag_BDINT

Tag_CDINT

CPTDINT761.65Memory and time for the CPT instruction

ADD (+)DINT280.26Memory and time for the ADD instruction

1041.90total

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&R1756-RM087E-EN-E - May 2005&8Supersedes Publication 1756-RM087D-EN-E - April 2004

1.7 s for the ADD instruction

2.73 s for the DINT-to-REAL wire (The Source A pin uses the REAL data type.)

0.46 s for the REAL IREF

0.38 s for the REAL-to-REAL wire (The Source B pin uses the REAL data type.)

0.28 s for the DINT IREF

Ladder Instructions

MotionLadder InstructionData typeNotesMemory (bytes)Execution time if true (s)Execution time if true (s)Execution time if true (s):Execution time if true (s):

yes1756-L1, -L1Mx1756-L55Mxx1756-L61, -L62, -L631769-L201769-L301769-L311769-L32, -L351794-L33, -L34DriveLogix5720DriveLogix5730

ABLn/a5213.311.24.815.215.73.82.814.912.54.4

ABSDINT320.610.600.280.760.780.300.320.710.610.30

ABSREAL560.880.860.411.051.070.450.461.030.870.43

ACBn/a5213.511.03.415.615.92.22.115.112.73.8

ACLn/a64139.8102.628.2134.3136.536.033.3160.3135.036.5

ACSREAL48271.0249.631.8334.0339.435.735.4320.6269.933.3

ADDDINT280.560.550.260.760.770.290.290.670.560.27

ADDREAL4410.710.41.513.313.51.71.712.710.71.6

AFIn/a40.050.050.030.070.050.030.020.060.060.02

AHLn/a68104.077.525.1102.7104.233.230.9116.6102.033.8

ANDDINT280.410.520.260.690.700.400.340.730.950.28

ARDn/a7688.466.02.286.287.52.93.8102.586.426.9

ARLn/a7688.766.02.786.387.84.33.4102.786.624.4

ASNREAL48261.7240.830.1322.6327.834.334.0309.6260.632.1

ATNREAL48223.5212.321.3275.5279.924.124.0264.4222.622.4

AVEINTLength55.3+ (x 7.0)48.0+ (x 6.1)14.4+ (x 2.4)68.0+ (x 8.6)63.4+ (x 8.0)-3.0+ (x .0)16.2+ (x 2.8)65.2+ (x 8.2)54.9+ (x 6.9)15.7+ (x 2.6)

AVEREALLength11645.0+ (x 14.6)39.2+ (x 13.6)12.3+ (x 3.2)55.8+ (x 18.0)51.8+ (x 16.7)12.8-+ (x .1)14.2+ (x 3.6)52.9+ (x 17.3)44.8+ (x 14.5)12.9+ (x 3.4)

AVESINTLength55.0+ (x 6.6)47.7+ (x 5.8)14.3+ (x 2.3)68.0+ (x 8.1)63.3+ (x 7.5)-8.2+ (x .0)15.9+ (x 2.7)65.2+ (x 7.7)55.0+ (x 6.5)14.4+ (x 2.5)

AWAn/a8089.666.418.586.387.725.425.2103.086.825.6

AWTn/a8088.766.519.686.487.927.223.3103.086.825.8

BRKn/a44n/an/an/an/an/an/an/an/an/an/a

BSLDINTx = LengthRound up x /32 to a whole number.527.8+ ( (x /32) 0.8)6.3+ ( (x /32) 0.6)2.4+ ( (x /32) 0.2)9.8+ ( (x /32) 1.0)9.2+ ( (x /32) 0.9)2.7+ ( (x /32) 0.2)2.7+ ( (x /32) 0.2)9.3+ ( (x /32) 0.9)7.8+ ( (x /32) 0.8)2.5+ ( (x /32) 0.2)

BSRDINTx = LengthRound up x /32 to a whole number.52+ ( (x /32) 0.8)7.0+ ( (x /32) 0.6)2.6+ ( (x /32) 0.2)10.9+ ( (x /32) 1.0)1