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1. Gates, Truth Tables, and LogicEquations

The electronics inside a modern computerare digital. Digital electronics operate withonly two voltage levels of interest: a highvoltage and a low voltage.

The fact that computers are digital is also akey reason they use binary numbers.

Thus, rather than refer to the voltage levels,we talk about signals that are (logically)true, or 1, or are asserted; or signalsthat are (logically) false, or 0, or are

deasserted. The values 0 and 1 are


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ogic blocks are categori!ed as one oftwo types, depending on whether theycontain memory."locks without memory

are called combinational; the output of acombinational block depends only on thecurrent input.#n blocks with memory, the outputs can

depend on both the inputs and the valuestored in memory, which is called thestateof the logic block.cobinationallogic$ logic systemwhoseblocks do not

containmemor and

sequential logic$ group of logic

elements that containmemory and hencewhose value depends onthe inputs as well as the

current


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"oolean $lgebra$nother approach is to e%press the logic

function with logic e&uations.#n "oolean algebra, all the variables have thevalues 0 or 1.There are three operators:

The ' operator is written as , as in A + B.The result of an OR operator is 1 if either of thevariables is 1. The ' operation is also called alogical sum, since its result is 1 if either operand

is 1.The $*+ operator is written as , as in A B.The result of an A!D operator is 1 only if bothinputs are 1. The $*+ operator is also called

logical product, since its result is 1 only if both


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Gate a device that implements basic logicfunctions, such as $*+ or '

The unary operator *'T is written as $.The result of a !OT operator is " only ifthe input is 0. $pplying the operator *'Tto a logical value results in an inversion ornegation of the value (i.e., if the input is 0the output is 1, and vice versa).


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$ny logical function can be constructed using

$*+ gates, ' gates, and inversion.#n fact, all logic functions can be constructedwith only a single gate type, if that gate isinverting. The two common inverting gates are

called !"# and !$!% and correspond toinverted ' and $*+ gates, respectively. *'and *$*+ gates are called universal, since an#logic function can be built using this one gatet#pe.


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-. ombinational ogic-.1 +ecoders

%ecoder a logic block that has an n$bit inputand -n outputs, %here only one output is

asserted for each input combination.


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-.- /ultiple%or or elector

The left side of igure .2.- shows this

multiple%or has 2 inputs: - data values and aselector (or control) value. The selectorvalue deterines &hich of the inputsbecomes the output. 3e can represent the

logic function computed by a two4input


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Then the multiple%or basically consists of

three parts:1. $ decoder that generates n signals, eachindicating a dierent input value-. $n array of n A!D gates, each combiningone of the inputs %ith a signal from thedecoder2. $ single large ' gate that incorporates the

outputs of the $*+ gates

/ultiple%ors can be created with an arbitrarynumber of data inputs. 3hen there are onlytwo inputs, the selector is a single signal that

selects one of the inputs if it is true (1) and theother if it is false (0). #f there are n data inputs, there %ill need tobe log-n selector inputs.


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-.2 Two4evel ogic and 5$s (5rogrammableogic $rray)

$ny logic function can be implemented withonly $*+, ', and *'T functions.$ny logic function can be written in a canonicalform, where every input is either a true orcomplemented variable and there are only twolevels of gates6one being $*+ and the other

'6with a possible inversion on the 7naloutput.uch a representation is called a t%o$levelrepresentation. A sum-of-products

representation is a logical sum (') of


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A sum-of-products representation is a logical sum (OR)

of logical products (terms using the AND operator).


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The sum4of4products representation correspondsto a common structured logic implementationcalled a 'L$.

$ 'L$ has a set of inputs and correspondinginput complements, and two stages of logic.

The 7rst stage is an array of $*+ gates thatform a set of roduct ters (soeties

called inters).

Each roduct ter

can consist of any of theinputs or theircomplements.

The second stage is anarray of ' gates, eachof which forms a logicalsum of any number of

the product terms.


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8$ 5$ can directly implement the truth tableof a set of logic functions with multiple inputsand outputs.

8 ince each entry where the output is truere&uires a product term, there will be acorresponding row in the 5$.89ach output corresponds to a potential row

of ' gates in the second stage. The numberof ' gates corresponds to the number oftruth table entries for which the output istrue.

8The total si!e of a 5$, is e&ual to the sumof thesi!e of the $*+ gate array (called the A!D

plane* and the sie of the OR gate array(called the OR lane*.

Example :


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Example :

The first stage is an

arra of AND gates

that form a set of

product terms

(sometimes called

minterms).

Size of theAND

gate arra! "#$The second stage is

an arra of OR gates%each of &hich forms a

logical sum of an

num'er of the product

terms.

ie of the OR gatearra !$#"


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$ 5$ using dots to indicate the components ofthe product terms and sum terms in the array.ather than use inverters on the gates, usually

all the inputs are run the width of the $*+ planein both true and complement forms.$ dot in the $*+ planeindicates that the input,or its inverse, occurs in the product term.

$ dot in the ' plane indicates that the


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.* #"+s$nother form of structured logic that can beused to implement a set of logic functions is a

readonly eory (#"+).8$ '/ is called a memory because it has aset of locations that can be read; however,the contents of these locations are 7%ed,usually at the time the '/ is manufactured.8 There are also rograable #"+s('#"+s) that can be programmed

electronically, when a designer knows theircontents.8 There are also erasable '#"+s; thesedevices re&uire a slow erasure process using

ultraviolet light, and thus are used as read4


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$ '/ contains -naddressable entries, thenthere are n input lines.

The number of bits (m) in each addressable

entry is e&ual to the number of output bits.

'/s and 5$s are closely related.

$ '/ is fully decoded: it contains a fulloutput word for every possible inputcombination.


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-.< +on=t ares

There are situations where we do not carewhat the value of some output is, eitherbecause another output is true or because asubset of the input combinations determines

the values of the outputs.uch situations are referred to as don-t cares.Don-t cares are important because they makeit easier to optimi!e the implementation of a

logic function.

There are two types of don=t cares:8output don=t cares and8input don=t cares.


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8 Output don-t cares arise %hen %e don-tcare about the value of an output for some

input combination. They appear as >s in theoutput portion of a truth table. 3hen anoutput is a don=t care for some inputcombination, the designer is free to make

the output true or false for that inputcombination.

8 nput don-t cares arise %hen an outputdepends on only some of the inputs, andthey are also shown as >s, though in theinput portion of the truth table.


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9%ample:onsider a logic function with inputs A, B, and &de/ned as follo%s0

#f A or & is true, then output D is true, %hatever thevalue of B. #f A or B is true, then output 1 is true, %hatever thevalue of &.

'utput 2 is true if e3actl# one of the inputs is true,although %e don-t care about the value of 2, %heneverD and 1 are both true.


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1) 'utput 2 is true if e3actl# one of the inputs is true,but %edon-t care about the value of 2, %henever D and 1 areboth true.

*+,-/0/,

10/, 231+/4


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-) #f we also use the input don=t cares,this truth table can be further simpli7ed

A!5 6723-08986

61 8/ ; < =

>fA or C is true, then output D is true, whatever the value of B.>fA or B is true, then output E is true, whatever the value of C.


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-.? $rrays of ogic 9lements

/any of the combinational operations to be

performed on data have to be done to anentire word (2- bits) of data.

Thus we often want to build an array of logicelements.

$ bus is a collection of data lines thatis treated together as a single logicalsignal.

The term bus is also used to indicate ashared collection of lines %ith multiplesources and uses, such as #@' buses.


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$multiple%or

that selectsbetween apair of 2-4bit buses


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2. onstructing a "asic $rithmetic ogic Anit

8 The arithetic logic unit ($L-) is thebrawn of the computer, the device thatperforms the arithmetic operations likeaddition and subtraction or logical operations

like $*+ and '.8 The $A is constructed from four hardwarebuilding blocks ($*+ and ' gates, inverters,and multiple%ors)

2.1 $ 14"it$A

ontrol line

elects AND or OR operation


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Adder


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arry'ut B (b arry#n) (a arry#n) (a b) (a b arry#n)

arry'ut B (b arry#n) (a

arry#n) (a b)

>f a ? ' ? =arr>n is true% then all of the

other three terms must also 'e true%

so &e can lea@e out this last termcorresponding to the fourth line of the

ta'le.


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B# C,6

2,/C< 892,8/40CF6%

GHIJ 8/4

opcode 89

278/


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2.- $ 2-4"it$A

The addercreated by

directly linkingthe carries of 14bit adders iscalled a

ripple carr#adder.

2 - 1) = t l li


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2.-.1)ubtractionis the sameas adding

thenegativeversion ofan operand.That

e%plainswhy two=scomplementrepresentation is used.

Control lines

=ontrol lines

(Kin@ert% Operation)

C,6 2,/C< 89

2,8/40CF6% GHIJ

8/4 opcode 89

278/


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2.-.-) #mplementation of a *'operation

Control lines =ontrol lines (Ain@ert%

Kin@ert% Operation)C,6 2,/C< 89

2,8/40CF6% GHIJ

8/4 opcode 89

278/


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2.-.2) upport of theset on less than instruction (slt Ct0,Cs2,CsD)

The operation produces 1 in Ct0, if Cs2 E CsD,

and 0 otherwise. onse&uently, slt will set allbut the least signi7cant bit to 0, with the leastsigni7cant bit set according to the comparison.

$dd an input (ess)for the slt resultand use it onl# for

slt (i.e. %hen

' i


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'peration8onnect 0 to the ess input for the upper 21bits of the $A, since those bits are always set to

0.8ompare and set the least signi/cant bit for sltinstructions.#mplementation

3hat happens if we subtract b from aF(a G b) E 0 i.e. #f the dierence is negative, then

a E b

et the least signi7cant bit of a slt operation to 1if a E b; i.e., a 1 if a G b is negative and a 0 ifit=s positive.

This desired result corresponds e%actly to the

sign bit values: 1 means negative and 0 means

Thus we need a new 1 bit $A for the most


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Thus, we need a new 14bit $A for the mostsigni7cant bit (/bit) that has an e%tra outputbit: the adder output. The drawing shows the

design, with this new adder output line called)et, and used onl# for slt.4.5.6* )ince we need a special $A for the mostsigni7cant bit, we addedthe overHow detection

logic since it is also associated with that bit.

3e need only connect thesign bit (the mostsigni7cant bit) from the

adder output (et) to theleast signi7cant bit input(ess) to get set on lessthan result.

$ 2-4bit $A


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$ 2-4bit $Aconstructed from the21 copies of the 14bit

$A (slide 2-) and one14bit $A (slide 2D) forthe /bit. The essinputs are connected to

0 e%cept for the leastsigni7cant bit, which isconnected to the etoutput of the most

signi7cant bit.#f the $A performs a Gb and we select theinput 2 in themultiple%or, then

8 or subtraction we set both


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or subtraction, we set botharry#n and "invert to 1 .

8or adds or logical operations,both control lines must be 0.8Thus the arry#n (for the b) and"invert are combined to a singlecontrol line called Bnegate.

2.-.


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The combination of the 14bit$invert line, the 14bit "negateline, and the -4bit 'peration

lines as D4bit control lines forthe $A, telling it to performadd, subtract, $*+, ', or seton

less than.

a, b, esult are 2-4bit buses

(ML'it)


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6* &7O&8)&locks are needed in se9uential logic to decide%hen an element that contains state should be

updated. $ clock is simply a free4running signalwith a 7%ed c#cle time.

loc/ing ethodologyThe approach used todetermine when data is valid and stable

relative to the clock.Edgetriggered cloc/ing$ clocking schemein which all state changes occur on a clockedge.

The clock edge acts as a sampling signal,


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ynchronous syste.$ memory systemthat employs clocks and where data signalsare read only when the clock indicates that the

signal values are stable.

The 7gure shows the relationship among thestate elements and the combinational logicblocks in a synchronous, se&uential logicdesign.

The state elements, whose outputs change

only after the clock edge, provide valid inputs


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$n edge4triggered methodologyallows a stateelement to be read and written in the sameclock cycle without creating a racethat could

lead to undetermined data values.'f course, the clock cycle must still be longenough so that the input values are stablewhen the active clock edge occurs (itdepends on the delay introduced by thecombinational logic).

#n case where the delay of the combinational


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#n case where the delay of the combinationallogic before and after a state element is smallenough then each block could operate in one4

half clock cycle, rather than the more usualfull clock cycle.Then the state element can be written on therising clock edge corresponding to a half clock

cycle, since the inputs and outputs will bothbe usable after one4half clock cycle (on thefalling clock edge).'ne common place where this techni&ue is

used is in register les, where simplyreading or writing the register 7le (see slideDJ) can often be done in half the normal clockcycle.#egister le$ state element that consists of

D 1) /emory 9lements: lip4lops atches


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D.1) /emory 9lements: lip lops, atchesand egisters$ll memory elements store state: theoutput from any memory element depends both

8on the inputs and8on the value that has been stored inside thememory element.

Thus all logic blocks containing a memory

element contain state and are se&uential.

$ pair of cross4coupled*' gates can store aninternal value. The valuestored on the output : isrec#cled b# inverting it toobtain : and then inverting

: to obtain :. f either R or

M.5.5) Bncloced emor element : LR latch (setLreset latch)

D 1 -) lip4lops and atches


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D.1.-) lip lops and atchesAnlike the 4 latch, all the latches and Hip4Hopsare clocked,which means that they have a clock

input and the change of state is triggered bythat clock.The dierence between a Hip4Hop and a latchisthe point at which the clock causes the state to

actually change (clock methodology, see slide2J).#n a cloc/ed latch, the state is changedwhenever the appropriate inputs change and the

clock is asserted (level triggered) , whereasin a 2i2o, the state is changed only on aclock edge (edge triggered).

D.1.2) + memor

"oth % latch and % 2i2o have one data

input that stores the value of that input signal in


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$ % latch has twoinputs and two outputs.

The inputsare the datavalue to be stored(called D* and a clocksignal (called &* that

indicates %hen thelatch should read thevalue on the D inputand store it.83hen the clock input & is asserted, the latchis said to be open (follo%s the D input*, and

the value of the output (:*becomes the valueof the input D.8hen the clock input & is deasserted, thelatch is said to be closed, and the value of the

output (:* is whatever value was stored the

D atch


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ince when the latch is open the value of :changes as D changes, this structure is

sometimes called a transparent latch.

'peration of a + latch, assuming the outputis initially deasserted.

3hen the clock, &, is asserted, the latch isopen and the : output immediatel# (%ithin a

small dela#* assumes the value of the D

tored

Output follo&s input

=loc asserted

>nput changed

$ + Hip4Hop with a


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$ + Hip4Hop with afalling4edge trigger.The 7rst latch, called

the master, is openand follows the inputD %hen the clockinput, &, is asserted.

hen the clock input,&, falls, the /rst latchis closed, but thesecond latch, called

the slave, is open andgets its input from theoutput of the master

latch.

=ompared

to D atch

=P period

D flipLflop

tored


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"ecause the D input is sampled on the clockedge, it must be valid for a period of timeimmediately before and immediately after theclock edge.8 The minimum time that the input must bevalid before the clock edge is called the setu

tie;

8 The minimum time during which it must be

valid after the clock edge is called the holdtie.Thus the inuts to any 2i2o ust bevalid during a window that begins at time tsetup

before the clock edge and ends at t holdafter theclock edge.

Qalling =P edge

D.1.D) egister iles ()


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) g ( )'ne structure that iscentral to the datapath

is a register /le.A register /le consists ofa set of registers thatcan be read and written

by supplying a registernumberto be accessed.9ach register consists of

2- + Hip4Hops.$ register 7le with two read ports and onewrite porti.e. has 7ve inputs: the 7rst threeinputs select the desired reg. K the data tobe written and

two outputs(for the data to be read).

"

"

"

The


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Theimplementationof two 2-4bit

read ports for aregister 7le withn registerscanbe done with a

pair of n-to-1multiplexors,each 32 bitswide. Theregister readnumber signalis used as the

multiple%or

"

"

log n

logn


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The 2-4bit write port for a is implemented with adecoder that is used with the write signal to generate the& input to the regs. All 4 inputs (the reg number, the data,and the write signal) will have setup and hold4timeconstraints that ensure that the correct data is written

"

log n

D -) /emory 9lements: $/s and


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D.-) /emory 9lements: $/s and+$/sD.-.1) tatic andom $ccess /emory ($/)$ memory where data is stored statically (as inHip4Hops) rather than dynamically (as in+$/).$/s are faster than +$/s, but less dense

and more e%pensive per bit.To initiate a read orwrite access, thehi select signalmust be made active.

or reads, we mustalso activate the"utut enablesignal that controlswhether or not the

datum selected by

or writes we must supply the data to be


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or writes, we must supply the data to bewritten and the address, as well as signals tocause the write to occur. 3hen both the 3rite

enable and hi select are true, the dataon the data input lines is written into the cellspeci7ed by the address.

! "#$ %

#"&$% read &' '*+,

-!$ " +./ " '0

12! 34

state 5u66ers !

'*+ (see slides 73477),

To allow multiple sources to


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To allow multiple sources todrive a single line, a three$state buer (or tristatebuer* is used. A three$

state buer has t%o inputs


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The basic structureof a Dword L -bit$/consists of a

decoder thatselects which pairof cells to activate.

The activated cellsuse a 24state

output buerconnected to thevertical bit linesthat supply the

re&uested data.The address thatselects the cell issent on one of aset of hori!ontaladdress lines,The Ss of all latches are "Lstate 'uffers% asserted ' the ena'le input


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Thus the

output B# of the R

is replaced '

" state 'uffers in a RA

R

RA

The shared 'it lines DoutU5V and

DoutUWV are ena'led ' one of

the &ord lines (WL")

>n a M X Y RA% &e &ould need a LtoLM decoder i.e. M


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%

&ord lines (&hich are the lines used to ena'le the indi@idual ZipL

Zops)[ Each &ord line consists of Y 'its.

To circum@ent this

pro'lem (i.e. to

reduce the sie of

the decoder)% large

memories are

organied as

rectangular arras

and use a t&oLstep

decoding process

(M\ x Y)

RA #5] RA M#

RA M#Y

/emory organi!ation as rectangular array and use of a -4d di


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Typical organi!ation of a *+4 5 #$+as an array

of *6 4 10* arrays. The first decoder generatesthe addresses for eight DM N 10-D arrays (using $-14$10);then a set of ultile7ors is used to select 1 bitfrom each 10-D4bit4wide array (using $O4$0).

This is a chepear design than a single4level decode

step decoding process

+ l t f b th h $/


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+evelopment of both synchronous $/s($/s) and synchronous +$/s (+$/s). The key capability provided by synchronous$/s is the ability to transfer a burst of datafrom a series of se9uential addresses within anarray or row. The burst is de7ned by a starting

address, supplied in the usual fashion, and aburst length. The speed advantage of synchronous $/scomes from the ability to transfer the bits in the

burst without having to specify additionaladdress bits. #nstead, a clock is used to transferthe successive bits in the burst. The elimination of the need to specify the

address for the transfers within the burst

M..) Dnamic Random Access emor (+$/s)


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#n a static $/ ($/), the value stored in a cellis kept on a pair of inverting gates, and as long

as power is applied, the value can be keptinde7nitely. #n a dynamic $/ (+$/), the valuekept in a cell is stored as a charge in a capacitor.$ single transistor is then used to access this

stored charge, either to read the value or tooverwrite the charge stored there. "ecause+$/s use only a single transistor per bit ofstorage, they are much denser and cheaper per

bit."y comparison, $/s re&uire four to si%transistors per bit.

"ecause +$/s store the charge on a

A singleLtransistor DRA cell


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To refresh the cell, read its contents and &rite itbac/. The charge can be kept for several ms, whichmight correspond to close to a million clock cycles.

Today, single4chip memory controllers often handlethe refresh function independently of the processor.

+$/s also use a two4level decoding structure (ne%tslide), and this allows us to refresh an entire row(which shares a word line) with a read cycle followedimmediately by a write cycle.

Typically, refresh operations consume 1P to -P of the

A singleLtransistor DRA cell

contains a capacitor that stores the

cell contents and a transistor used to

access the cell.

'*


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$ D/ 4 1 %#$+ is built &ith a 0*5 4 0*5array. The ro& access uses 11 bits to select arow, which is then latched in -0DJ 14bit latches.

$ /A> chooses the output bit from these -0DJlatches. To save pins and reduce the package cost,the same address lines are used for both the row andcolumn address; a pair of signals called $ (ow$ccess trobe) and $ (olumn $ccess trobe) are

used to signal the +$/ that either a row or column

Ro& access

=olumn accessC*

55

WMY

WMY

5

8'*+ 9+/:

D 2) 9rror +etection and orrection


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D.2) 9rror +etection and orrection"ecause of the potential for data corruption inlarge memories, most computer systems use

some sort of error4checking code to detectpossible corruption of data.

'ne simple code that is heavily used is a parit#code.n a parit# code the number of 1s in a word iscounted; the word has odd parity if the number

of 1s is odd and even otherwise. 3hen a word is written into memory, theparity bit is also written (1 for odd, 0 for even).Then, when the word is read out, the parity bit

is read and checked.

$ 1 bit parity scheme is an error detection


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$ 14bit parity scheme is an error detectioncode(detection of an error in data, but notthe precise location and, hence, correction of

the error)

There are also Error Correction CodesECC!that %ill detect and allo% correction ofan error.

2or large main memories, many systems use

a code that allows the detection of up to -bits of error and the correction of a single bitof error. These codes work by using morebits to encode the data; for e%ample, the

typical codes used for main memories

8) 9initestate achine (to describe ai l )


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sequential syste)$ se&uential system is described as a 7nite4statemachine.$ 7nite4state machine has a set of states andtwo functions, a ne%t4state function that mapsthe current state and the inputs to a new state,

and an output function that maps the currentstate and possibly the inputs to a set of assertedoutputs.!e7tstate function

$ combinational function that, given the inputsand the current state, determines the ne%t stateof a 7nite4state machine.

"ututfunctionproduces a setof outputs

from the


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The state machines we discuss here ares#nchronous. This means that the state

changes together with the clock cycle, anda new state is computed once every clock.

Thus, the state elements are updated onlyon the clock edge.

3hen a 7nite4state machine (/) is usedas a controller, the output function is oftenrestricted to depend on Rust the current

state. uch a 7nite4state machine is calleda =oore machine.

#f the output function can depend on both

$ / can be implemented with a register to


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$ / can be implemented with a register tohold the current state and a block ofcombinational logic that computes the ne%t4

state function and the output function

Thus a Q &ith M 'its

of state% can descri'e

up to 5] states.

To implement the Q

in this &a% &e must

^rst assign state

num'ers to the states.This process is called

state assignment.


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Example of a Q:

=ontrol of a traf^c light at an intersection of a northLsouth (N) route and an eastL&est (E_) route.

Qor simplicit% &e &ill consider onl the green and

red lights.

_e &ant the lights to ccle no faster than "W

seconds in each direction% thus &e &ill use a W.W""

` cloc.

The follo&ing steps are reuired:

a* Output signals setting


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* p g g!)lite0hen this signal is asserted, the light onthe north$south road is green; when this signal is

deasserted, the light on the north4south road isred.1lite0hen this signal is asserted, the light onthe east$%est road is green; when this signal is

deasserted, the light on the east4west road isred.

b* )tates speci/cation and assignment!)green0 The tra>c light is green in the !$)direction1green0 The tra>c light is green in the 1$

direction.

W

5

tate assignment

d* nput signals setting b# e3ternal sensors!) di h i h


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!)car0 ndicates that a car is over thedetector placed in the roadbed in front of

the light on the north4south road (goingnorth or south).1car0 ndicates that a car is over thedetector placed in the roadbed in front of

the light on the east4west road (going eastor west).e* Next state function determination

=urrent state

W

W

WW

5

5

5

5

W

5

W5

5

5

W

W

$ graphical representation, is often used for /.#n this representation nodes are used to indicate


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#n this representation, nodes are used to indicatestates.a)#nside the node we place a list of the outputs

that are activefor that state.b) +irected arcs are used to show the ne%t4statefunction,c) labels on the arcs specifying the input

condition as logic functions.or e%ample the transition from *green to 9wgreeninthe ne%t4state table (see true table of slide ?O) is(*car 93car) (*car 93car), which is e&uivalentto 93car.

tate

;utput

t state

indication

8To implement the /, we must 7rst assign


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state numbers to the states (stateassignment*.)lides ?@$?.

8 Thus %e assigned !)green to state and1green to state 1, i.e. the state registercontains a single bit.8The ne%t4state function would be given asurrenttate is the contents of the state

register (0 or 1) *e%ttate is the output of thene%t4state function that will be written into thestate register at the end of the clock cycle.8The output functionis also simple:

W

5

1stlpdigitas asgafdg ag _ agafga rag dafg adfgaergervfgrergerg adgaerga g

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