2 clamping

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III SEM(E&E) ANALOG ELECTRONICS LAB

CLAMPING CIRCUIT

Expt No:2 Date:

AIM :To design a positive/negative clamping circuits for a given reference levelvoltage.

APPARATUS :

THEORY :

A circuit that places either negative or positive peaks of a signal at the desired

D.C level is known as clamping circuit.

A clamping circuit essentially adds DC component to the signal. The input

signal is a sine wave having peak-to-peak value of 10. The clamper adds a D.C

component and pushes the signal upward so that the negative peaks fall on the !ero

level. As we can see the waveform now has peak values of 10 and 0.

"t may #e seen that the shape of the original signal has not changed$ there is

only a vertical shift in the signal. %uch a clamping is called positive clamping. Thenegative clamper does the reverse& ie. it pushes the signal downward so that the

positive peak falls on the !ero level.

A clamping circuit should not change the peak-to-peak value of the signal. "tshould only change the DC level& for this a clamping circuit uses a capacitor with a

diode and a load resistance '(. The operation of the clamper is #ased on the principle

that the charging time of the capacitor is made small as compared to discharge time.

"n a positive clamper the input signal is assumed as s)uare wave with a time

period T. The clamped output is o#tained across '(. This circuit designs incorporate

two main features. *irstly the value of '(and C are so selected that constant T + '(.C

is very large. This means the voltage across the capacitor will not discharge

significantly during the interval the diode is in non-conducting state& secondly '(.C

time constant is deli#erately made much greater than the time period T of the

incoming signal.

S!. No. PARTICULARS RAN"E #UANTITY

1 Diode 1N 4007 1

2 'esistor ,00k 1

3 Capacitor 1* 1

4 DC ower %upply 0-1 1

5 %ignal generator --- 1

6 C' --- 1

7 Connecting #oards 2 3ires --- ---


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DESI"N : *re)uency of "nput s)uare wave is 1k4!

3.5.T Time period& T+1/*T+1ms.'.C 66 T & '.C 66 1 ms 7say8

(et C + 1 *

' 66 91 ms / 1*:& ' 66 0 5

' ,00 5.

Let us Choose, RL=200 K & C = 1 F.

PROCEDURE :

1. ;efore wiring the circuit & check all the components using multimeter.

2.


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"nput waveform utput waveform

i o

v ,m

,m 0 t 0 t

-v

Positive c!"#i$% cicuit ith /ve e(ee$ce :

'esi%$ o(Positive c!"#i$% cicuit :During negative half cycle

?D@ is & c+7m-

+ '. 7m + in/,8

3hen Diode is '.; or open ckt

-inB c o + 0 o + in c

7,m-

87,m-

8


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Positive c!"#i$% cicuit ith -ve e(ee$ce :

Positive C!"#i$% ith ve e(ee$ce vot!%e

,m

o

t0

t

,m

o

0

7-'-

+

7,m-

'

8


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e%!tive C!"#i$% Cicuit :

'esi%$ o( e%!tive C!"#i$% :

During %#$itive half Ccle!

3hen Diode ?D@ is & c = "-

.

During Negative half Ccle!

3hen Diode is 'everse ;iased or pen ckt

*rom circuit #y 5..( & -in c o + 0

o = i$- c

3hen in+ m& o + inB c + mB 7m- 8

o + mB m .

o =

3hen in+ 0 o + 0 B c + 0 B 7m- 8

o = "-

.

3hen in+ -m& o + inB c + -mB 7m- 8o = -2"/

.


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i o

10v

2" 0 t 0 t

-10v

"nput 3aveform utput 3aveform

e%!tive C!"#i$% ith -ve Re(ee$ce:

'esi%$ o( e%!tive C!"#i$% ith -ve Re(ee$ce:

7-,m7'

+

7'8

2"


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During %#$itive half ccle!

?D@ is &c=)"-

+ / R. where 7m + in/,8

During %#$itive half ccle!

3hen Diode is '.; or open ckt& from circuit #y 5..(

-in c o + 0.

o = i$- c

3hen in+ -m )$#ut !t -ve #e! +&

o + in- c

o + -mB 7m- '8.

o = -2"-Re(./

.)ut#ut -ve #e! +

3hen in+0&

o + in- c

o + 0 -7m- 'ef.8

o = -"- R/

.

3hen in+ m )$#ut /ve #e! +&

o + in- c

o + m- 7m- '8

o + m- m- '

o = R/

)ut#ut /ve Pe! +

e%!tive C!"#i$% ith /ve Re(ee$ce:


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i o

10v

2" 0 t 0 t

-10v

"nput 3aveform utput 3aveform

7-,m7'-

+

7-'

8

2"

2 clamping

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