2 class d2: logic...

2 Class D2: Logic Compilers; Sequential Circuits I: flip-flops

Chapter 15N

Class 15/D2: Logic Compilers;Sequential Circuits I: flip-flops

Contents

15NClass 15/D2: Logic Compilers; Sequential Circuits I: flip-flops 115N.1Big Points from Last time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315N.2Why? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315N.3Implementing a combinational function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

15N.3.1Simplifying or minimizing logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415N.4Active-Low, again . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

15N.4.1Diagram it with Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515N.4.2Do it with a logic compiler: ABEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715N.4.3Do it with another logic compiler: Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

15N.5Considering Gates as ‘Do This/Do That’ Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015N.5.1AND as Pass/Block* Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015N.5.2AND as “IF” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

15N.6XOR as Invert/Pass* Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115N.7OR as Set/Pass* Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215N.8Sequential Circuits, generally, and Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15N.8.1The Simplest Flip-Flop: the “latch,” made from a few transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215N.8.2The Simplest Flip-Flop again: the “latch,” made with two gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1315N.8.3Switch Debouncers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415N.8.4. . . But SR Usually is Not Good Enough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515N.8.5Edge-triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

15N.9More Debouncers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915N.9.1D Flop and slow clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915N.9.2Positive-Feedback Debouncer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

15N.10Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2015N.10.1Ripple counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

15N.11Synchronous counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2115N.11.1What “synchronous”means . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2115N.11.2. . . Synchronous counting requires a smarter flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2215N.11.3The counter behavior we want . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

15N.12Another flop application: Shift-Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2315N.13AoE Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Class D2: Logic Compilers; Sequential Circuits I: flip-flops 3

REV 21; March 7, 2015.

15N.1 Big Points from Last time

• digital gives good noise immunity

• . . . noise immunity allows most of what’s wonderful about digital:

– binary coding of information permits electronics of extreme simplicity, thus small size and lowcost

– noise immunity is fundamental to data storage, and transmission through adverse conditions

– the fact that information is encoded permits processing to detect and correct errors (e.g., in digitalmusic playback)

• since noise-immunity is fundamental, better noise immunity is important: 5-volt CMOS beats old“TTL.” But differential signaling is best, and works at the low voltages now common.

• arrays of gates—PAL’s, PLD’s and FPGA’s—are taking over from small packages of just a few gates. . .

• . . . and a logic compiler, used to program such parts, normally takes care of minimization

• most digital control signals are active low (for historical reasons). . .

• . . . a logic compiler can hide some of that nastiness from you

• binary numbers: 2’s-complement represents negative numbers. Simple scheme: MSB is negative, in2’s-comp. But signed/unsigned is a matter for humans to interpret; the binary representation does notreveal which is intended.

15N.2 Why?

What task do we undertake, this time? To remember states of binary signals, so as to make circuits that aremore versatile than the merely combinational circuits that we met last time.

15N.3 Implementing a combinational function

Most of the time, the combinational logic you need to design is so simple that you require nothing more thana little skill in drawing to work out the best implementation. For such simple gating, the main challenge liesin getting used to the widespread use of active-low signals.

Here’s an example: “Clock flop if RD* or WR* is asserted, and Now* is asserted”

1Revisions: respond to Paul’s notes: tidy ripple waveforms, add IC ripple waveforms (2/15); insert Ray’s redrawings (10/14); addheaderfile (6/14); add ‘Why’ (1/14); make text signal names match figure, in 1st combi truth table example (10/13); add S, R labels tonand latch figure (3/13); add treatment of gates as ’do this or that’, add ‘AND as IF’ (7/12); add index (6/12); answer queries embedded(10/11)


Figure 1: Easy combinational logic; some signals active low: don’t think too hard; just draw it

You can make this problem difficult for yourself if you think too hard: if you say something like, ‘Let’s see, Ihave a low in and if the other input is low I want the output high–that’s a NOR gate...”–then you’re in troubleat the outset. Do it the easy way, instead.

Here is the easy process for drawing clear, correct circuits that include active-low signals:

1. Draw the shapes that fit the description: AND shape for the word AND, regardless of active levels;

2. Add inversion bubbles to gate inputs and outputs wherever needed to match active levels;

3. Figure out what gate types you need (notice that this step comes last—and comes never if you use alogic compiler and PLD).

In general, bubbles meet bubbles in a circuit diagram properly drawn: a gate output with a bubble feeds agate input with a bubble, and your eye sees the cancellation that this double-negative implies: bubbles popbubbles. This usual rule does not apply in the exceptional case when your logic is looking for non-assertionof a signal. We’ll see such cases in §??. It also often does not apply to edge-triggering, where it is timing thatdetermines one’s selection of a clock edge (“leading” versus “trailing”).

15N.3.1 Simplifying or minimizing logic

When a logic network is not utterly simple, you may wonder if your implementation is minimal—as simpleas possible. Once upon a time, achieving that simplest design was a serious part of a designer’s work. Onemight use Boolean algebra to simplify an equation—factoring, for example. If, in those dark old days, youwere given a truth table like the following,2 how would you implement it?

Figure 2: A truth table to implement

In the old days, it would have been worthwhile to try to find the simplest way to build this circuit.

2A fair and relevant question is whether life is likely to deliver a problem in this form. The truth table arises only if you find thisa convenient way to think about the design task. If you start, instead, by drawing gates to describe the design, this design-from-tableproblem does not arise.


1. You might simply stare at the table for a while, and discover the pattern. Some people like to work thatway.

2. You might write the Boolean expression for each input combination that gives a 1 out:

f = A*B* + A*B + AB

Then you could use Boolean algebra to simplify this expression. Try factoring:

f = A*(B* + B) + AB = A* + AB

Thus you discover that you can toss out one variable, A, from two of the terms. After that, if youare on your toes, you recognize a chance to apply another Boolean postulate, and you end up with anagreeably simple equation:3

f = A* + B

But such skills in using Boolean algebra are obsolete. So are the graphic aids to simplification providedby Karnaugh Maps. Both are obsolete because anyone with access to a computer can take advantage of anautomated logic compiler. The compiler implements a “Hardware Description Language” (HDL), normallyVHDL or Verilog. In this course we use Verilog.

The compiler cheerfully simplifies what you type (or draw—some compilers will accept graphical input). So,let’s not give any more attention to a problem that mercifully has been removed from a designer’s life. Wecan save our intellectual energy for more interesting tasks.

15N.4 Active-Low, again

Last time, we met an example using signals that were active low, in the somewhat-silly missile-launch circuit.Here, let’s look at an example that is a little closer to a realistic case. This case includes some signals that areactive-high, but a larger number that are active-low, as most control signals are.4

15N.4.1 Diagram it with Gates

Draw gates that will. . .

Assert DOIT if. . .

• WRITE, VALID and TIMED all are asserted,

– so long as neither PROTECTED nor BLOCK is asserted;

• or if either WILLY or NILLY is asserted.

3You might find it simpler, still, to write an equation for the single case that produces a low output: f* = AB*.4The reason for the predominance of active-low signal is simply historical. Such signals were advantageous in the era of bipolar

logic, as we argued in classnotes D1.


Figure 3: Active-low signals mixed with a few active-high

15N.4.1.1 The only hard part: agreeing on what we mean

Curiously enough, this exercise presents the only point in the course when students sometimes get angry,disgusted with us teachers for talking nonsense, or worse. It’s as if we’re suddenly reciting blasphemous andinconsistent remarks about the students’ religions.

Why? Because the phrase, “WRITE is asserted” is ambiguous. We don’t want to insist that our understand-ing of this phrase is the only reasonable one; we only want to ask you to join us in what we admit is only aconvention—a way that we understand this phrase. We want you to understand it the way that we do; thatway, we’ll not misunderstand each other.

We intend “WRITE is asserted” to mean that the signal named “WRITE” is low. The bar over the signal’sname, here, means that the signal is active low. AoE §10.1.2.1

Indignant students sometimes protest, “No! To say that “WRITE is asserted” is to say that WRITE is false.If WRITE is false, it is low, and its complement, “WRITE” is high.

Such a protest is not wrong; it just does not follow the convention that we are trying to impose on you—andwhich is widely recognized: many signals (most, by a wide margin) are active-low, and one indicates thisactive-low quality by using a “bar” or asterisk. Such a signal normally is born active-low, rather than beingthe complement of an active-high signal of the same name.

We did write the word “WRITE” (without a bar over its name) to the left of the boundary and circle (oftencalled a “bubble”), in figures ?? and ??. But we did not thereby mean to imply that any such signal exists.Probably it does not exist, and in those drawings there is no point indicated where one could apply a probe totest an active-high WRITE signal. Only the active-low “WRITE” is available for probing.

In the case of “DOIT ,” we used this active-low labelling because the label is placed to the left of the bubble,out in the world where the signals run and are available for probing. On the leftmost part of the diagram, incontrast, we used labels without bars (showing “WRITE,” for instance), because a bubble intervenes betweenthis fictitious point and the outside world where “WRITE” travels.

Well, we have expended a lot of words to make a small point—but it is one on which we must agree, if weare to able to talk to one another about signals that are active-low.


15N.4.1.2 Draw a solution, with gates

Here is a drawing meant to implement the logic that we described in words:

Figure 4: Gates drawn to implement the logic described earlier

15N.4.1.3 . . . It’s not quite as simple as “let bubbles meet bubbles”

For most of the signals shown in figure ??, “bubbles meet bubbles,” so that one can see inversions cancellingeach other. But you don’t want to apply such a rule mechanically.

This simple-minded rule does workwhen you are using gates to detect assertion of signals. It does not work—as we noted back in § ?? on page ??— in a case where a gate is to detect dis-assertion. The leftmost two-inputAND gate, above, is used to detect such a disassertion of the signals PROTECTED and BLOCK . So, inthis case, bubbles do not meet bubbles. The mismatch, obvious to your eye, reveals at a glance that the job ofthis AND gate is to sense falsehood, or disassertion.

15N.4.1.4 . . . and deMorgan sometimes allows two equally-good symbols

DeMorgan teaches that two alternative symbols always are available to draw a logical function, and we haveshown these alternatives in figure ??, for the logic used to sense disassertion or falsehood. Usually, one ofthe two deMorgan-equivalent symbols shows more clearly than the other what is going on in the circuit. Youshould make the choice that seems to you to represent best what your circuit is doing.

Once in a while, however—as in the case of the logic applied to PROTECTED and BLOCK—the twoalternative symbols are equally good. The one we drew first senses that both signals are false, or “dis-asserted.” The alternative form, shown lower, senses that either signal is asserted . . . and uses that event todisassert the input to the next gate. The results are logically identical, of course. Use whichever you prefer.The OR shape does the better job of reflecting the language of the design specification, “neither . . . nor” . . . .But the AND shape, sensing “both signals false,” shows logic that may be easier to think about.

15N.4.2 Do it with a logic compiler: ABELAoE §11.3.4.1

All this huffing and puffing about active-low’s becomes unnecessary if you happen to be implementing yourlogic with the ABEL hardware-description language. ABEL, despite its obsolescence, does a better job than


more recent languages at handling signals that are active-low.5 If, again, you’d like to skip over a littlehistory, skip these paragraphs about ABEL; go right on to § ?? on page ??, which treats a contemporary logiccompiler, Verilog.

Using a logic compiler, we assign variables to pins on PAL or FPGA. As we assign them, we have a ready-made opportunity to state whether each signal is active HIGH (the default) or active LOW (expressed byplacing an exclamation point, read as “bang,” ahead of the variable name). This opportunity applies to bothinput and output signals. In the ABEL code below, we have used “bangs” to indicate every active-low signal.

The happy consequence is that when we write the equation that implements the logic, we can forget aboutwhether signals are active-high or active-low. In the sheltered world we have created for ourselves, there isno such thing as active-low. In this sheltered place, a bang means what one would hope it could mean: that asignal is disasserted or false. That’s the case for PROTECTED and BLOCK, in the equation below:

// INPUTS!WRITE, VALID, !TIMED, !PROTECTED, !BLOCK, !WILLY, NILLY pin 1..7; // Bang all signals that are

// active low

//OUTPUTS!DOIT pin 23 istype ’com’; // Reiterate default signal type: combinational rather than sequential

// (no flop needed)

EQUATIONS

DOIT = WRITE & VALID & TIMED & (!PROTECTED & !BLOCK) # (WILLY # NILLY); // ( & means AND, # means OR)

15N.4.3 Do it with another logic compiler: VerilogAoE §11.3.4.2

Verilog does not make things so easy—but we must get used to the way Verilog works, because it has takenover from ABEL. Verilog makes it possible, but not easy, to mimic ABEL’s nice trick of hiding active-lows.

15N.4.3.1 One can force Verilog to mimic ABEL, suppressing active-low’s . . .

One can do it by introducing extra signal-names that are purely active-high—the complements of any nastyactive-low signals that the world imposes on us. We have done this in the Verilog listing below, and you’llnotice that the resulting equation looks almost exactly like ABEL’s (the same except for use of the magicword “assign,” and a different symbol for OR: “|” rather than “#”).

module act_lo_verilog(write_bar, valid, timed_bar, prot_bar, block_bar, willy_bar, nilly, doit_bar);input write_bar;input valid;input timed_bar;input prot_bar;input block_bar;input willy_bar;input nilly;output doit_bar;

wire doit;// all inputs and outputs are ordinary signals ("wire"), versus the sort that holds a value ("reg")

// by default; "doit"---one never brought out to a pin but used as input to a function--// is explicitly called "wire"

// Now flip all active-low signals, so we can treat ALL signals as active-high as we write equationsassign write = !write_bar; // makes a temporary internal signal (write) never assigned to a pinassign timed = !timed_bar;assign prot = !prot_bar;

5We don’t know why, but here’s a guess: ABEL was written by people familiar with hardware; the later languages, Verilog andVHDL, were written by people familiar with computers but whose work kept them remote from tiresome details such as the active levelof signal lines.


assign block = !block_bar;assign willy = !willy_bar;assign doit_bar = !doit; // this output logic is reversed because the active-high "doit"

// will be an input to this logic, used to generate the OUTPUT

assign doit = write & valid & timed & (!prot & ! block) |(willy | nilly); // ( & means AND, | means OR)

endmodule

The ugly active-low signals, with names like “willy bar,” do not appear in our equations. Our equation lookssimple and tidy.

15N.4.3.2 . . . Some say it’s probably wiser not to ask Verilog to act like ABEL; instead, use signalnames to indicate active levels

Some Verilog users scorn such a crutch. But we think it’s nice not to have to worry about active levels whenwriting equations. In an active-high world, whenever you see a “bang” (“!” or “˜”), you can take that to meandisassertion of a signal.

If you don’t force signals into active-high form, then the best you can do is to give the variable a name thatreveals whether it is active low. Following such a scheme, the equations are not so neat: they include bangsto show assertion of signals that are active-low:

module act_lo_verilog(write_bar, valid, timed_bar, prot_bar, block_bar, willy_bar, nilly, doit_bar);input write_bar;input valid;input timed_bar;input prot_bar;input block_bar;input willy_bar;input nilly;output doit_bar;

wire write_bar,valid,timed_bar,prot_bar,block_bar,willy_bar,nilly,doit_bar;// specify all inputs and outputs and intermediate "doit" as ordinary signal ("wire")

// versus the sort that holds a value ("reg")

assign doit_bar = !( (!write_bar & valid & !timed_bar) & !(!prot_bar | !block_bar) |(!willy_bar | nilly) ); // NOR of assertions of prot_bar* and block_bar*, this time

endmodule

You can judge for yourself which of the two schemes is the less confusing.

The two versions evoke exactly the same designs from the logic compiler, and Verilog will draw a schematicgate diagram to show its implementation.6 For a simple design, it may be worthwhile to look at the schematic:

6Verilog offers two schematic versions of its implementation, under “Synthesize:”

Figure 5: Two schematic versions are availableRTL (“RTL” stands for “Register Transfer Logic,” referring apparently to the not-very-interesting point that the typical circuit includes

“registers” (flip-flops) linked to other registers, describes a generic design and is usually the simpler and clearer. “Technologyschematic”shows the way the design will be implemented in the particular piece of hardware chosen for the circuit. Sometimes RTL is quite useless:


it’s reassuring, when it looks right, and the graphic representation can render obvious some errors that are notevident in the text of the source file.

Here’s Verilog’s drawing of the doit bar logic: no surprises, but reassuring. Verilog uses a wide ANDfunction where the hand-drawn figure used two levels; Verilog’s design is better, imposing less delay than thehand-drawn version would.

Figure 6: Schematic gate diagram drawn by Verilog compiler (RTL version)

Xilinx’s ISE11 and later allow you to decide which signals you want to see in the schematic. That’s a usefulfeature in a design with lots of signals.

15N.5 Considering Gates as ‘Do This/Do That’ Functions

A truth table describes a logic function fully, so you may be inclined to think that you can leave your under-standing of gates at that level: just write out (or memorize) the truth tables for the fundamental functions:perhaps AND, OR, and XOR.

Another way to think about gates, though, can be useful as well. Sometimes it helps to think of a two-inputgate as using one of its inputs to operate upon the other. That probably sounds cryptic. Some examples willmake the point:

15N.5.1 AND as Pass/Block* Function

Treat input A as control. Then the AND gate will pass B if A is high, block B if A is low.

Figure 7: AND gate viewed as Pass/Block* function

Xilinx Verilog sometimes will use an adder to design a counter in RTL, when told “count <= count + 1.” The technology schematic, incontrast, shows Verilog coming to its senses, drawing the simpler traditional counter design. So, to play it safe, look at the technologyschematic if RTL is far from what you expected


You will see AND used this way to implement a synchronous clear* in a counter described in Classnotes D3.You will see it again when we treat software masking in Classnotes Micro 3.

Note that when the gate does what we describe as “block,” it is driving its output Low, not simply passing“nothing” as a 3-state buffer would. So, such a “blocked” signal must be fed to an OR gate, if combined witha “passed” signal, as in a 2:1 multiplexer:

Figure 8: AND gates, when “blocking” must be fed to an OR, which ignores lows

The OR gate has the good sense to ignore a Low. Simply joining the two AND outputs would fail, of course,setting up a fight between the two gates.7

15N.5.2 AND as “IF”

Another wording of what the AND function occasionally can help, as well: think of the AND function aspassing or permitting a signal “IF” a condition is fulfilled (pass B if A is asserted).

Ordinary language occasionally uses the word “and” to mean “if”—well, it did in Shakespeare’s time, any-way. No doubt you recall these lines from Romeo and Juliet8

An you be mine, I’ll give you to my friend;And you be not, hang, beg, starve, die in the streets

For “an” and “and” in this passage we would, of course, write “if.”

15N.6 XOR as Invert/Pass* Function

An XOR gate can do the useful work of acting as a controllable inverter. The XOR will invert B if A is high,pass B if A is low.

Figure 9: XOR gate viewed as controllable inverter

You will see the XOR put to this use in § ?? on page ??.

7This point is noted elsewhere: in a worked example on multiplexing.8Just kidding. If you remember these lines, you’ve probably stumbled into the wrong classroom or have picked up the wrong book.

The lines are from Romeo and Juliet, Act III, Scene 5.


15N.7 OR as Set/Pass* Function

The OR gate will set the output (force output high) if A is high, pass B if A is low.

Figure 10: OR gate viewed as Force/Pass* function

You will meet this use of OR in the discussion of software masking in Classnotes Micro 3.

Flip-Flops

15N.8 Sequential Circuits, generally, and Flip-Flops. . .

The combinational circuits that we looked at in the first day of digital “live in the present,” like the resistivecircuits we met in the first day of analog. Sequential circuits offer a contrasting behavior that neatly parallelsthe contrast we saw between day two and day one of analog: RC circuits care about the past, and thus offerbehaviors that are more complex and more interesting than those of purely-resistive circuits. The same is trueof sequential digital circuits in contrast to combinational.

Aƒ(A,B,…)B

Aƒ(A,B,… and past)

B ......

combinational logic… …sequential logic

Figure 11: Combinational versus Sequential Logic Circuits: block diagrams contrasted

If combinational logic were the whole of digital electronics, the digital part of this course would now be justabout finished. You could close the book and congratulate yourself.

But, no: the interesting part of digital lies in sequential circuits. These permit building counters, memories,processors—and computers.

Flip-flops are easy to understand. A harder question arises, however, when we look at flops in detail: why areclocked circuits useful? We will work our way from primitive circuits toward a good clocked flip-flop, andalong the way we will try to see why such a device is preferable to the simpler design.

15N.8.1 The Simplest Flip-Flop: the “latch,” made from a few transistors

The feedback shown in the block diagram just above (fig. ?? on page ??) appears below, in fig. ?? on page ??on the right, as the link between the output of each transistor switch and the gate controlling the other MOS-FET switch. This is a circuit that will lock itself into one “state” or the other: one or the other switch will beheld ON while the other is held OFF.

AoE §14.5.3, andcompare the figureshowing staticRAM flop, fig.14.20


Figure 12: Simplest flip-flop: cross-coupled inverters

At first glance, this circuit seems to be quite useless: a circuit that is stuck forever—and, even worse, unpre-dictable. But the circuit is not really stuck, because it is easy to force it to a desired state. If you turn OFFthe transistor that is ON, for a moment (by connecting the gate of the ON transistor to ground), then the ONswitch turns off and as a result the formerly-OFF switch turns ON. Thus the momentary grounding of a FET’sgate can flip the circuit; doing the same to the other transistor can flop it back to its other state.

The name “flip-flop” provides a charmingly-simple description of the circuit’s behavior. (Engineers knowhow to speak simply; more hifalutin’ people like to obscure the circuit’s behavior by calling it a “bistablemultivibrator” (!)).

This transistor latch can store one bit of information; in an integrated version, the pullup resistors would beimplemented with transistors, as shown below. Two more transistors would permit both writing and reading(that is, writing by forcing the cross-coupled transistors to the desired state, reading by simply connectingthe Q’s to the outside world).

Figure 13: Simplest flip-flop as applied to store one bit in a static memory (RAM)

15N.8.2 The Simplest Flip-Flop again: the “latch,” made with two gates

Here is the cross-coupled latch done with gates rather than plain transistors. This is the version you will buildin lab.AoE §10.4.1


Figure 14: Cross-coupled NAND’s form a simple “S-R” latch

The bubbles on the inputs of the NAND gates remind us that these gates will respond to low’s: it is a low atthe S input9 that will “set” the flop (that is, will send Q high); a low at the R input will “reset” the flop (thatis, will send Q low).

As was true for the equivalent latches built with transistors, the useful property of the circuit is its ability tohold the state into which it was forced, once the forcing signal is removed. What input levels, then, let itperform this holding task?10 (Those input levels might be said to define the circuit’s resting state.)

This device works, but is hard to design with. It is useful to debounce a switch; but nearly useless for otherpurposes, in this simplest, barebones form.

15N.8.3 Switch DebouncersAoE §10.4.1.1

There are several ways to debounce a switch. The SR provides one way—for double-throw switches only(not for the simpler sort of switch that simply makes or breaks contact between two points). Here is an SRlatch wired as debouncer, and waveforms at S* and R*, and at the debounced output.

Figure 15: Switch bounce: first hit sets or resets flop: bounce does not appear at output

Fig. ?? shows the S-R flop’s ability to remember the last state into which it was forced. When S* rises to+5, and bounces low a few times, Q does not change in response to this bounce; the bounce simply drivesthe flop alternately into SET and REMEMBER modes. When R* first goes low, it forces Q low; when R*bounces high, Q does not change in response, because the flop simply remembers the Low state into which itwas forced. Again, it alternates between RESET and REMEMBER modes.

9Strictly, the “S” input should be labelled “S,” since it is active low. We didn’t dare label it that way, fearing we would start peoplethinking that this was the complement of some signal. Perhaps we should have been more courageous. But this flop is conventionally iscalled “SR” rather than “S-bar R-bar,” so maybe this labelling is tolerable.

10The input combination for ‘holding’ or ‘remembering’ the last state into which it was pushed, is 11: high on both inputs, disassertingboth S and R.


15N.8.4 . . .But SR Usually is Not Good Enough

But in other settings this flop would be a pain in the designer’s neck. To appreciate the difficulty, imagine acircuit made of such primitive latches, and including some feedback. Imagine trying to predict the circuit’sbehavior, for all possible input combinations and histories. Painful.

Figure 16: Example meant to suggest that asynchronous circuits are hard to analyze or design

Designers wanted a device that would let them worry less about what went on at all times in their circuits.They wanted to be able to get away with letting several signals change in uncertain sequence, for part of thetime.

This was the basic scheme they had in mind:

Figure 17: Relaxing circuit requirements somewhat: a designer’s goal

This permits less perfect circuit behavior without alarming results.11AoE §10.4.2

The gated S-R latch, or transparent latch takes a step in the right direction. This circuit is just the NANDlatch plus an input stage that can make the latch indifferent to signals at S and R: the input stage works like acamera’s shutter.

The two-input SR version shown on the left-hand side of fig. ?? on page ?? normally is simplified to its Dform shown to the right in that figure. This single input is more convenient, and eliminates the problematicinput case for the SR, in which both inputs are asserted.

Figure 18: Clocked or gated S-R latch, and the more useful “transparent” D latch

This achieves more or less what we wanted; but not quite:

11Does this waveform remind you of the average undergraduate’s week, except that a student’s “do right” duty cycle may be lower:perhaps a narrow pulse on Sunday evening?


Figure 19: Transparent latch moves in the right direction: now we can stand screwy input levels part of the time

The trouble is that this circuit still is hard to design with. Consider what sort of clock signal you would want,to avoid problems with feedback. You would need an ENABLE pulse of just the right width: wide enoughto update all the flops, but not so wide that an output change would have time to wrap around and call for asecond state change. Ticklish.

Because the simple NAND latch is so hard to work with, the practical flip-flops that people actually use nearlyalways are more complex devices that are edge-triggered.

15N.8.5 Edge-triggeringAoE §10.4.2.1

Edge-triggered flip flops care about the level of their inputs only during a short time just before (and in somerare cases after) the transition (“edge”) of the timing signal called “clock.”

Figure 20: Edge-triggering relaxes design requirements

An older design, called by the nasty name, master-slave, sometimes behaved nastily12 and was generallyreplaced by the edge-trigger circuit. The master-slave offers the single virtue that it is easy to understand.But we will not examine it here. (If you are curious to meet this circuit, see AoE 10.4.2).

The behavior called edge-triggering may sound simple, but it usually takes people a longish time to takeit seriously. Apparently the idea violates intuition: the flop acts on what happened before it was clocked,not after. This behavior does not violate causality. How is this behavior possible? (Hint: you have seensomething a lot like it on your scopes, which can show you the waveform as it was a short time before thetrigger event. How is that magic done?13)

Set* and Reset*(normally dis-asserted)

“Data” input

clock(edge-sensitive)

Figure 21: 74HC74 edge-triggered D flip-flop

12Some master-slave J-K flops showed a pathology called “ones-catching”: they were sensitive to events that occurred while the clockwas at a single level, High, rather than being responsive only to a change in clock level.

13An answer to this riddle appears in Classnotes D3.


Here are its crucial timing characteristics:AoE §10.4.2.3

Figure 22: D-flop timing: setup time and propagation delay; hold time should be zero

A D flop only saves information. It does not transform it; just saves it. But that simple service is enormouslyuseful.

15N.8.5.1 Digression on the signal name “clock”

The name “clock” for the updating signal introduced in § ?? is potentially misleading. It suggests, to a thoughtfulreader, several notions that do not apply:

• the term suggests something that keeps track of, measures or accumulates time;

• or, even short of that, it suggests at least something that ticks regularly: a sort of strobe or heartbeat.Neither notion applies to the clock of a flip-flop. (A clock may be—and fairly often is—a steady square wave; butit need not be.)a

A clock is no more than a trigger signal that determines when the flip-flop updates its memory.A better word for the signal might be “update.” But we are stuck with the term “clock.” Just get used to disbelievingits metaphor. The engineers who named it were not competent poets.

aIt is not a steady wave, for example, when the clock signal comes from a pushbutton—as in the single-step logic of the lab microcomputer.In that circuit, a user presses a button; a debounced version of this button-press applies a rising edge to a D flop whose D input is tied high.Such schemes are quite common.

15N.8.5.2 Triggering on Rising- versus Falling- Edge

The D flop shown on the left in fig. ?? responds to a rising edge. Some flops respond to a falling edge,instead. A flop never responds to both edges.14 As with gates, the default assumption is that the clock isactive high. An inversion bubble indicates active low: a falling edge clock:

Figure 23: Clock edges: rising or falling edge

Edge- versus Level-sensitive flops & inputs Some flip-flops or flop functions respond to a clock-like sig-nal, but not to the edge itself: that is, the device does not lock out further changes that occur after the levelbegins. The transparent latch is such a device. We met this circuit a few pages back, in fig. ??.

14Well, hardly ever. Some one-shots do trigger on both edges: e.g., the 74HC423 and the 8T20. Flip-flops using both edges seem tobe confined to programmable logic such as the Xilinx Coolrunner II.


Examples of level-sensitive inputs:

• A “transparent latch”:

The character displays we sometimes use in these labs work this way (called “HP Displays” in labnotes):

Figure 24: Level-sensitive: transparent latch: Output follows or displays input while en* is low

• the latches included on the AD558 Digital-to-Analog Converter (“DAC”), which you will meet in theADC lab, work this way. The transparent behavior allows one to ignore the input register, getting a“live” image of the digital input, simply by tying en* low.

Figure 25: Transparent latch on DAC allows one to use the DAC as continuous converter, if necessary

• Reset on a flip-flop AoE §10.4.2.1

Figure 26: Reset* and Set* on 74xx74 D flop

The Reset* and Set* signals reach into the D flop’s output latch, and prevail over the fancy edge-triggercircuit that precedes the out latch. This so-called “jam type” takes effect at once. This set-or-resetscheme is universal on flip-flops, not quite universal on counters. But a reset is never treated as a clockitself—even in the cases (called “synchronous”) where the action of resetting ‘waits for the clock.’The edge-triggered behavior is reserved for clocks, with only the rarest exceptions (like the 8051’sInterrupt-request lines).15

15These INT* lines are not quite true edge-triggered inputs, but “pseudo-edge sensitive;” they respond to a transition, detected as a


Edge triggering usually works better than level-action (that is, makes a designer’s tasks easier); edge-triggeringtherefore is much the more common configuration.

Applications

15N.9 More Debouncers

15N.9.1 D Flop and slow clock

A D flop can debounce a switch, if you have a slow clock available to you. The strategy is to make sure thatthe flop cannot be clocked twice during bounce. If it cannot, then the output—Q—cannot double back.

Unlike the S-R debouncer, this method introduces a delay between switch-closing and output. Occasionally,that matters (for example, in the reaction timer described in a separate note); usually it doesn’t. This de-bouncing method has the virtue of working with the simpler, cheaper switch: the single-pole type (SPST).Here’s the dead-simple circuit:

period > tbouncebounce

from anytype of switch

D Q

CLK

Figure 27: Another debouncer: D flop and slow clock

Below, in figs. ?? and ??, are some waveforms making the point that the clock period must exceed bouncetime. When the clock runs too fast, as in fig. ??, the flop passes the bounce to the output: not good.

Figure 28: D-flop debouncer must use a clock period greater than bounce time: here, clock is too fast

A slower clock does the job:

difference between levels before and after a processor clock. Their behavior is, however, very close to edge-sensitive.


Figure 29: D-flop debouncer must use a clock period greater than bounce time: here, period is long enough

The main drawback of this debounce method—in addition to the uncertain delay—is the need to generatethe slow-clock signal. If you need to debounce a single switch, it is not an appealing method. If you needto debounce several lines—as in our powered breadboards, where two switches are debounced, or in themicrocomputer keypads that you soon will meet, where five lines need debouncing—the slow-clocked flopmethod makes sense.

15N.9.2 Positive-Feedback Debouncer

The simplest debouncer, for a double-throw switch (“SPDT”) is just a non-inverting CMOS gate with feed-back:

+5

(CMOS)(SPDT only)

resistor Ok butnot required

Figure 30: Another debouncer: positive-feedback with CMOS gate

At first glance, this may look too simple to work—but work it does. The key notion is that the gate inputnever floats; the gate input is always driven by the gate output, even when the switch is in transition, nottouching either +5 or ground.

15N.10 Counters

15N.10.1 Ripple counters

AoE §10.4.2.4

Figure 31: Simple “counters”: “divide-by-two”; “divide-by-four” (ripple type)

Ripple counters are simple, but their weakness is that their Q’s cannot change all at the same time. Theprogressing waveform visible in fig. ?? gives the counter its name.

Because the several flops change state not all at once but in succession, not only are they slow to reach astable state but also they necessarily produce transient states that ought not to be present.


clock

Q0

Q1rippledelay (9ns)

ripple counter made from 74HC74 flip-flops

Figure 32: 2-bit ripple counter shows delay between Q’s—thus false transient states

This two-bit counter is a down counter, because the second flop changes only when the first is low before theclock edge. It is easily transformed into an up counter.16

An integrated ripple counter, like the 74HC393 forms an UP counter by using a falling-edge clock. Its rippledelays are less than those shown by the counter built from 74HC74 D flops (fig.??). The ’393 flop-to-flopdelays are about 4ns:

clock

Q0

Q1

74HC393 ripple counter

delay(4ns)

Figure 33: Integrated ripple counter shows less delay between Q’s—but still ripples

15N.11 Synchronous countersAoE §10.4.3.6

15N.11.1 What “synchronous” means

A synchronous circuit sends a common clock to all of its flip-flops; so, they all change at the same time.17

This is the sort of design one usually strives for.

The signature of the synchronous counter, on a circuit diagram, is just the connection of a common clock lineto all flops (⇐⇒ syn-chron: same-time). The synchronous counter—like synchronous circuits generally—ispreferable to the ripple or asynchronous type. The latter exist only because their internal simplicity lets onestring a lot of flops on one chip (e.g., the “divide by 16k” counter we have in the lab–the ’4020, or the morespectacular ’4536: divide-by-16M!).

Here’s a generic synchronous circuit; there’s no clue to what it may be doing—but its synchronous quality isvery obvious.

16How? Just treat the Q’s as the outputs; or, equivalently, treat Q’s as outputs but use Q’s to do the ripple clocking.17. . . Except to the small extent that propagation delays of the several flops may differ.


Figure 34: Generic synchronous circuit: common clock is its signature feature

15N.11.2 . . . Synchronous counting requires a smarter flip-flop

Making a counter that works this way requires a flop smarter than the one used in the ripple counter. Whereasthe ripple counter’s flops change state whenever clocked, the sync counter’s flops are clocked continually,and should change only sometimes. More specifically, the second flop—Q1—should change on every secondflop; if there were a third flop, Q2, it should change on every fourth clock, and so on. In order to get thisbehavior from flops that are clocked continually we need a flop (to implement Q1, here) that will, underexternal control, either hold its present state or toggle (flip to the other state). That behavior is called “ToggleFlop” or “T flop” behavior.

15N.11.2.1 . . . and XOR can make a D flop into a “T”

It turns out that an XOR gate is just what we need in order to convert a humble D flop into the smarter “T”flop. We noted, back in § ??, that the XOR function can be described as one that lets one input determinewhether the other input is passed or inverted. With the help of the XOR, then, we can make a D flop into aT—one that changes on the next clock only if its “T” input is driven high:

Figure 35: An XOR as pass*/block can convert a D flop into a T

15N.11.3 The counter behavior we want . . .

Here is a timing diagram for a synchronous divide-by-four, noting the cases where we want Q1 to change andthose where it should hold. We will connect D and T flops as required, to get this desired behavior.

Figure 36: Timing diagram showing how we’d like our synchronous divide-by-four counter to behave


Since the low-order flop, Q0, changes on every clock, it doesn’t need to be smart: just tie Q0* back to D0, asin the ripple counter. It’s Q1 that needs to be a little smarter.

In two cases shown above in fig.?? Q1 holds its present state after clocking; in two other cases it changesstate. What we need to arrange, then, is to have the second flop’s “T” input driven high each time we wantchange on the next clock, and driven low when we want Q1 to hold on the next clock.

15N.11.3.1 Setup-time: an important subtlety

In making a synchronous design, it is essential to drive all the inputs properly before the clock edge (in ourcase, the rising edge). It won’t do, therefore, to look at the timing diagram above and say, “Oh, I see: Q1should change whenever Q0 falls.’ That information—that ‘Q0 has fallen’— comes too late. Our circuitneeds to drive T1 appropriately before the next clock edge. More precisely, it needs to drive T1 early enoughso that D1 is in the correct state by setup-time before the clock edge. (For the 74HC74, tsetup is 16ns, max;the typical value (versus max) is just a few nanoseconds.)

So, Q1 will behave as we want if we tell it, “Change on the next clock if Q0 is high.” This simple wiringimplements that design:

Figure 37: Synchronous counter

15N.12 Another flop application: Shift-RegisterAoE §10.5.3

This circuit is about as simple a flop circuit as one could imagine: just a sort of daisy chain.

Figure 38: Lab shift register

A shift-register generates predictable, orderly delay; it shifts a signal in time; it can convert a serial stream ofdata into parallel form, or vice-versa. Serial to parallel is the easy direction:

QØ … Qn

Parallel Out

Serial In

Clock

n

D0>

>

>

Figure 39: Shift-register can convert data from serial form into parallel

Such a circuit is useful because it permits using a small number of lines to transmit many bits of information(the minimum number of lines for a simple shift register would be two: data and clock; some schemes—


more complex—can omit the clock).18 Converting from parallel to serial is not quite so simple. It requiresmultiplexer logic feeding each D (except the first): one must be able, first, to steer parallel data into each D,then to revert to the normal daisy-chained shift-register wiring, in order to shift out the serial stream.

In the lab, you will use a shift register for a different purpose: to generate a pulse; that is, to act like a so-called “one-shot.” A NAND gate added to the shift-register does the job. (We use two, because in a later labwe need a double-barreled one-shot). See if you can sketch its timing diagram, and then what happens if youwire a NAND gate, as in the lab, to detect Q0Q1.

15N.13 AoE Reading

Reading:

Chapter 10 (Digital Logic I):

• §10.4: sequential logic

• in §10.5, Sequential Functions available as ICs, see especially

– §10.5.1: latches and registers

– §10.5.4: PLDs

• §10.8: logic pathology, especially

– §10.8.2: switching problems

– §10.8.3: weaknesses of TTL and CMOSChapter 11 (Digital Logic II):

• §11.1: PLD history

• §11.2.1: PAL structure

• give just a hasty glance at the FPGA (§11.2.3)

Specific advice:

• You need not worry about Karnaugh-mapping. It was a useful device in the era before computer logic compilers.These have now made Karnaugh-mapping obsolete.

• AoE §10.5.4 introduces PALs;• Concentrate on flip-flops and counters in §10.4.

class notes dig2 headerfile june14b.tex;March 7, 2015

18We will glimpse these clock-less serial protocols later in the course: we will see it in the traditional RS232 serial scheme, and inthe more recent USB (which, however, uses two data lines, because it uses differential signalling, for good noise immunity at modestvoltages).

2 class d2: logic...

Documents