2 december 2003 – itrs public conference tsinchu, taiwan itrs 2003 front end process itrs...

2 December 2003 – ITRS Public Conference — Tsinchu, Taiwan

ITRS 2003 Front End Process

ITRS Conference December 2, 2003Hsinchu, Taiwan

2 December 2003 – ITRS Public Conference — Hsin Chu, Taiwan

FEP Technology Working Groups

• Starting Materials: H. Huff, D. Meyers• Surface Preparation: J. Butterbaugh, J. Barnett• Thermal Films: C. Osburn, H. Huff• FEOL Etch: G. Smith, Y. Kim• Doping: L. Larson, D. Mercer• DRAM Trench Capacitor: Europe FEP, B. Vollmer, M.

Gutsche• DRAM Stack Capacitor: Japan FEP, M. Kubota, K.

Kaneda• Flash Memory: M. Alessandri, (Eur)H.K Kang (S. Kor • FeRAM: Japan FEP, M. Kubota


FEP- The Grand Challenges

• Introduction of many new materials into the CMOS Logic and DRAM process flows (2003-2007) – High k gate dielectric layers

– Dual metal gates

– New DRAM storage capacitor structures and materials

– New substrate materials such as SOI and strained silicon

– Alternate memory devices and materials, e.g. MRAM, FeRAM

• Beyond 2007, the probable introduction and CMOS integration of non-standard, dual-gate MOSFET’s e.g. FINFET


MOSFET Scaling- One scenario

• 2003-2007- Enhanced bulk devices– Strained silicon channels

– Dual work function metal gates (for p-MOS and N-MOS

– High-k gate dielectric

• 2008-2011- Planar fully depleted SOI– Incorporate bulk enhancements

– Silicon film thickness ~0.4 Lgate

– Elevated contacts

• 2012-2018- Fully Depleted Double Gate


Bulk Scaling Challenges- Year 2003-7

1/2X every 4-6 years

2 metals replace dual doped poly

High-k replaces Silicon Oxynitride

NiSi replaces CoSi2

Strained Si:Ge replaces Si

Drain extension Rs problems

Metal/Silicon Contact Rs problems

Gate Length Scaling and 10% 3 CD Control !!!!!


Challenges:

•Dual metal gate integration

•CD Control (10% 3)

•Spacer integrity

•Silicide/Si contact Rs

•Active Layer t control

•Hi-k integration

•Zero Damage Cleaning

•Box layer t control

•Drain extension Rs and gate drain overlap

•Epi-Bulk interface contamination

FD SOI Scaling Challenges 2008-2011

Box Layer

Dual metal gates (nMOS, pMOS)

Contact NiSi

Epi Elevated Contact

Strained Silicon Active Layer

High-k DielectricSidewall spacer

Active layer thickness ~0.4 Lgate, must scale with gate length


Double- or Tri-Gate Device Scaling 2011-2018

Buried Oxide Layer

Source Drain

Silicon Fin ChannelMetal Gates 1 & 2

1

2

= High N doping

= Light P doping

Gate Dielectric Layer (not shown)


FIN FET Challenges

Gate 1

Gate 2

Source Drain

Sidewall SpacersHi-k Gate Dielectric Layers

Drain ExtensionsChallenges:

•Gate CD Control

•Metal Gate Integration

•Fin Thickness control

•Drain Extension parasitic resistance

•Silicon/Silicide contact Resistance

•Sidewall spacer integrity

•High-k gate dielectric integration

•Zero damage cleaning

Fin Thickness ~0.8 Lgate, must scale with gate length scaling


Starting Materials, Near- Term Issues & Challenges

• Production Ramp of SOI substrates-– Production capacity & capability– Metrology capability

• New Substrate Materials Likely- – Strained silicon on bulk– Strained silicon on SOI– May be a family of products

• Site Flatness (FEP Difficult Challenge)– Difficult to achieve– Wafer/chuck interactions add to overall non-flatness– Wafer/Chuck interactions poorly understood


FEP Surface Preparation• Near-tem red wall

– FEP surface cleaning with very low silicon loss– FEP surface cleaning with very low silicon oxide loss

• Cleaning process for newly introduced materials– High-k gate dielectric material(s)– Dual work function metal gates– DRAM High-k capacitor dielectric materials– Strained silicon

• Cleaning of high aspect ratio structures– Stacked and Trench capacitors– Vias

• Fragile structures limit cleaning options


FEP Surface-Preparation, Near-Term Red Wall

Note: Loss is defined as the average lost per pass, experienced after multiple cleaning passes: e.g. 0.2 Angstrom loss/pass is equivalent to 2 Angstrom loss after 10 cleaning passes

Dry strip and clean processes more complex process flows with more cleans, combined with more shallow structures combine to mandate low substrate loss cleaning processes

Year of Production 2003 2004 2005 2006 2007 2008 2009 DriverTechnology Node hp90 hp65DRAM 1/2 Pitch (nm) 100 90 80 70 65 57 50 DRAMCritical Particle Diameter (nm) 50 45 40 35 32.5 28.5 25 DRAMCritical Particle Count (#//Wafer) 59 75 97 64 80 54 68 DRAMSilicon Loss per Cleaning Step (A) 1.2 1.0 0.8 0.7 0.5 0.4 0.4 LogicOxide Loss per Cleaning Step (A) 1.2 1.0 0.8 0.7 0.5 0.4 0.4 Logic


Front-End Etch• 10% 3 control of Gate Length represents a

significant near term challenge– Lithography variances contribute to overall

variance

– Resist & Trim variances also contribute

• Near Term work-arounds are assume to exist– Design for greater variance

– Accept lesser binning yields


Etch Challenges

Work-arounds exist


FEP Thermal/Films• Most challenging issue remains the introduction of High-k gate

dielectric layers• Candidate materials are emerging but none are free of major

disadvantages– Interface states at channel and at polysilicon gate electrode– Poor charge carrier mobility– Threshold voltage shifts– CMOS integration challenges

• High-k gate dielectric layers require introduction before 2007 for low standby power MOSFETS

– Lowered gate leakage allowance (vs 2001 ITRS) for HP drives need High-k gate dielectric in 2007

– Gate leakage for Low Standby Power Devices drives need for high-k gate dielectric in 2006

• Gate Dielectric Layer Thickness control is emerging as an important challenge

• STI added for 2003 Roadmap


Year of Production 2003 2004 2005 2006 2007 2008 2009 DriverMPU Physical Gate Length (nm) 45 37 32 28 25 22 20 MPULow Operating Power Physical Gate Length (nm) 65 53 45 37 32 28 25 Low PowerLow Standby Power Physical Gate Length (nm) 75 65 53 45 37 32 28 LSTPEquivalent Oxide Thickness for MPU/ASIC, Tox (nm) 1.3 1.2 1.1 1.0 0.9 0.8 0.8 MPUGate Dielectric Leakage at 100oC (nA/m) MPU/ASIC 100 170 170 170 230 230 230 MPUEquivalent Oxide Thickness for Low Operating Power Tox (nm) 1.6 1.5 1.4 1.3 1.2 1.1 1.2 Low PowerGate Dielectric Leakage (nA/m) Low Operating Power 0.33 1.0 1.0 1.0 1.67 1.67 1.67 Low PowerEquivalent Oxide Thickness for Low Standby Power Tox (nm) 2.2 2.1 2.1 1.9 1.6 1.5 1.4 LSTPGate Dielectric Leakage (pA/m) Low Standby Power 3 3 5 7 8 10 13 LSTPEOT Thickness Control (%3 <4 <4 <4 <4 <4 <4 <4 MPU/ASIC

Thermal/Films Red Walls


STI Thermal Films Requirements

Year of Production 2003 2004 2005 2006 2007 2008 2009 Driver

MPU / ASIC ½ Pitch (nm) 107 90 80 70 65 57 50 MPU

MPU Physical Gate Length (nm) 45 37 32 28 25 22 20 MPU

STI depth (nm) [X] 400 384 367 359 353 339 335 Bulk

Trench width at top (nm) [Y] 107 90 80 70 65 57 50 Bulk

Trench sidewall angle (degrees) [Z} >86.2 >86.6 >86.9 >87.2 >87.4 >87.6 >87.9 Bulk

Trench fill aspect ratio 4.2 4.8 5.1 5.6 5.9 6.5 7.2 Bulk

SOI STI depth (nm) [AA] 36 30 26 22 20 18 16 SOI

SOI Trench aspect ratio 0.8 0.8 0.8 0.8 0.8 0.8 0.8 SOI


FEP/Doping• Major challenges continue to surround the achievement of ultra-

shallow, abrupt, highly activated drain extensions. – Drives innovation in ion implantation processes & equipments– Drives R&D for very rapid activation processes

• Attempts at more sophisticated model-based forecasting of Source/Drain requirements have not yet yielded conclusive results– S/D requirements highly interactive with overall transistor

design– S/D requirements for bulk devices are different from SOI and

future non-planar double gate devices– Drain Extension requirements are listed as target values

• Modeling of polysilicon gate depletion suggest that metal gates have potential to significantly extend the life of SiON gate dielectric materials


Doping Challenges


HP Logic, Metal Gate Delays Need for High-k Gate Dielectric

Modeling done by H. Gossmann, Axcelis Technologies Inc.

Year of Production 2003 2004 2005 2006 2007 2008 2009 DriverMPU Physical Gate Length (nm) 45 37 32 28 25 22 20 MPU

For the Case of 1E20/cm3 poly doping 1.42 1.32 1.09 0.97 0.88 0.41 0.41 MPU/ASICFor the Case of 2E20/cm3 poly doping 1.69 1.59 1.38 1.25 1.15 0.74 0.74 MPU/ASICFor the Case of Metal Gate 2.04 1.94 1.74 1.64 1.54 1.15 1.15 MPU/ASIC

Gate Electrode Depletion Effect- Required Gate Dielectric EOT (in nm) to meet device EIT based on Gate Material Choice


• Chip Size Model modified, based on survey of DRAM manufacturers

– Storage cell area increased from prior ITRS

– DRAM peripheral area decreased from prior ITRS

– Need for very high-k storage capacitor dielectric materials (e.g. BST) delayed beyond 2009

– Aluminum Oxide, Aluminates (e.g. HfAlOx) and Tantalum oxide remain capacitor materials of consideration for the 2003-9 time period

• Capacitor structure migrates from MIS to MIM in order to avoid challenges regarding capacitor dielectric thickness

• Total interlevel metal +dielectric (except storage node) is assumed to be 1.08nm at the 180nm node, and to decrease at a rate of 10% every three years.

• Storage node heights, dielectric constants of high-k materials, and capacitor structures (cylinder, etc) remain unchanged from prior roadmaps

DRAM Stacked Capacitor

2 december 2003 – itrs public conference tsinchu, taiwan itrs 2003 front end process itrs...

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