(2) logic design lec foe-rd
TRANSCRIPT
Dr. Ihab Talkhan
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LOGIC DESIGN
First Year - Computer Eng. Dept.
Dr. Ihab Talkhan
Dr. Ihab Talkhan
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Cairo UniversityFaculty of EngineeringComputer Engineering Department
Introduction to Logic DesignSunday/Thursday –2007/2008
Course Description:Digital Logic Design, The nature of digital logic, numbering system, Boolean algebra, karnaugh maps, decision –making elements, memory elements, latches, flip-flops, design of combinational and sequential circuits, integrated circuits and logic families, shift registers, counters and combinational circuits, adders, substraters ,multiplication and division circuits, memory types. Exposure to logic design automation software.
Credit: This course consists of 1 1 /2 lectures per week
Text book: M. Morris Mano, “ Digital Design” , third edition, Prentice Hall, 2002References: •M. Mano and C. R. Kime , “Logic and Computer Design Fundamentals”, Prentice Hall, 2000.•Daniel Gajski, “Principles of Digital Design”, Prentice Hall, 1997.
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Instructor(s): Dr. Ihab E. Talkhan
This course is designed to introduce the student to the basic techniques of design and analysis of digital circuits
Course contents:
#TitleAssignments
1Number Systems, 1’s and 2’s complements
# 1 2Basic Gates
3Boolean Algebra
4Analysis of Combinational Circuits
# 2 5Synthesis of Combinational Circuits using Karnaugh maps
6NAND/NOR networks, don’t care conditions, duality
7Design Automation Software (PSPICE A/D)
8Multiplexers, demultiplexers, decoders, encoders and parity circuits
# 3 9Arithmetic circuits
10Latches and Flip-Flops
11Design of clocked sequential circuits using counters as examples
# 412Shift registers and different types of counters
13Semiconductor memories
14Design of circuits using ROMs and PLAs
15Introduction to PLDs , CPLDs, & FPGAs and also VHDL (brief)
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Grading: 60% (2 tests - no make-ups) 15% Attendance 25% Assignments (all assignments from the text
book, end of chapter selected problems) Testing dates: to be announced later Final test date: refer to First term Schedule Assistant: to be announced later Office hours: to be announced later
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Design Cycle
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The Packaging Sequence
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ASIC Design Flow
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Course Ouline
Course Outline
Digital Circuits Digital Design Hardware Components
•Gates
•Flip-Flops
•Combinational
•Sequential
•Register Transfer Level
•Various components of a
computer Hardware
•Control Logic
•CPU (Central Processing
Unit)
•I/O
•Memory
Analysis & Design Hardware & Micro-program method
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Binary Logic
AND OR NOT (inverter)
-Represented by any of the following notations:
• X .AND. Y
• X . Y
• X Y
-Function definition:
Z = 1 only if X=Y=1
0 otherwise
-Represented by any of the following notations:
• X .OR. Y
• X + Y
• X v Y
-Function definition:
Z = 1 if X=1 or Y =1 or both X=Y=1
0 if X=Y=0
-Represented by a bar over the variable
•
-Function definition:
Z is what X is not
-It is also called complement operation , as it changes 1’s to 0’s and 0’s to 1’s.
X
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Binary Logic
AND OR NOT (inverter)
-Symbol:
-Truth Table
-Symbol
-Truth Table
-Symbol
-Truth Table
XYZ
0
0
1
1
0
1
0
1
0
0
0
1
XYZ
0
0
1
1
0
1
0
1
0
1
1
1
XZ
0
1
1
0
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Important Notes
Various binary systems suitable for representing information in digital components [ decimal & Alphanumeric].
Digital system has a property of manipulating discrete elements of information, discrete information is contained in any set that is restricted to a finite number of elements, e.g. 10 decimal digits, the 26 letters of the alphabet, 25 playing cards, and other discrete quantities.
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Important Notes (cont.)
Early digital computers were used mostly for numeric computations, in this case the discrete elements used were the digits, from which the term digital computer has emerged.
Discrete elements of information are represented in a digital system by physical quantities called signal [voltages & currents] which have only two discrete values and are said to be binary.
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Electrical Signals [ voltages or currents ] that exist throughout a digital system is in either of two recognizable values [ logic-1 or logic 0 ]
Voltage
time
Logic – 1 range
Logic – 0 range
Transition , occurs between the two limits
Intermediate region, crossed only during state transition
5
0.8
0
2
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Important Notes (cont.)
Digital computers use the binary number system that has two digits “0” and “1”, a binary digit is called a “bit”, thus information is represented in digital computers in groups of bits.
By using various coding technique, groups of bits can be made to represent not only binary numbers but also any other group of discrete symbols.
To simulate a process in a digital computer, the quantities must be quantized, i.e. a process whose variables are presented by continuous real-time signals needs its signals to be quantized using an analog-to-digital (A/D) conversion device.
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Memory or Storage Unit
ControlUnit
ProcessorUnit
Output devicesInput devices
CPUCentral Processing Unit
Block Diagram of a Digital Computer
The memory unit: stores programs, inputs, outputs and other intermediate data.
The processor unit: performs arithmetic and other data-processing operations as specified by the program.
The control unit: supervises the flow of information between the various units. It also retrieves the instructions, one by one, from the program stored in memory and informs the processor to execute them
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Important Notes (cont.)
A CPU enclosed in a small integrated circuit package is called a microprocessor.
The program and data prepared by the user are transferred into the memory unit by means of an input devices such as a keyboard.
An output device, such as a printer, receives the results of the computations and the printed results are presented to the user.
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Numbering Systems
A number is base “r” contains r digits 0,1,2,…..(r-1) and is expressed with a power series in “r”.
A number can also be expressed by a string of coefficients [positional notation].
....... 22
11
11
11
rArArArArArA oo
nn
nn
........ 2111 AAAAAA onn
Radix point
Least significant digitMost significant digit
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Numbering Systems (cont.)
The Ai coefficients contain “r” digits, and the subscript “ i ” gives the position of the coefficient, hence the weight ri by which the coefficient must be multiplied.
To distinguish between numbers of different bases, we enclose the coefficients in parentheses and place a subscript after the right parenthesis to indicate the base of the number.
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Decimal Numbers
The decimal number system is of base or radix r = 10, because the coefficients are multiplied by powers of 10 and the system uses ten distinct digits [0,1,2,…9].
Decimal number is represented by a string of digits, each digit position has an associated value of an integer raised to the power of 10.
Consider the number (724.5)10
1012 1051041021075.724
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Conversion from Any numbering System to Decimal System
To convert any numbering system to decimal, you expand the number to a power series with its base.
Example: Convert (312.4)5 to its equivalent decimal, note that the number is in
base 5.
10
10125
82.8
0.825 75
545251534.312
Radix 5
Conversion from base 5 number to its
equivalent decimal number
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Computer Numbering Systems
BinaryBase 2
OctalBase 8
HexadecimalBase 16
- It is a base 2 system with two digits “0” &
“1”
- The decimal equivalent can be
found by expanding the binary number to a power series with a
base of 2.
- It is a base 8 system with eight digits from
0 - 7
- The decimal equivalent can be
found by expanding the Octal number to a
power series with a base of 8.
- It is a base 16 system with sixteen digits
from 0 – 9 plus A,B,C,D,E,F letters from the alphabet.
- The decimal equivalent can be
found by expanding the Hexadecimal
number to a power series with a base of
16.
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Binary Numbers
Converting a Binary number to its equivalent Decimal:
(11010.11)2
10
21012342
26.75
0.250.528 16
2121202120212111.11010
Note that, when a bit is equal to “0”, it does not contribute to the sum during the conversion. Therefore, the conversion to decimal can be
obtained by adding the numbers with powers of two corresponding to the bits that are equal to “1’.
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Computer Units
210 = 1024 is referred to as Kilo “K”220 = 1,048,567 is referred to as Mega “M”230 is referred to as Giga “G”
Example: 16M = 224 = 16,777,216
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Conversion from Decimal to Binary(Integer numbers only)
The conversion of a decimal number to binary is achieved by a method that successively subtracts powers of two from the decimal number, i.e. it is required to find the greatest number (power of two) that can be subtracted from the decimal number and produce a positive difference and repeating the same procedure on the obtained number till the difference is zero.
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Example
Find the binary equivalent of (625)10
625 – 512 = 113 512 = 29
113 – 64 = 49 64 = 26
49 – 32 = 17 32 = 25
17 – 16 = 1 16 = 24
1 – 1 = 0 1 = 20
(625)10 = 29 + 26 + 25 + 24 + 20 = (1001110001)
LSB MSB
Position 10
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General Method
If the number includes a radix point, it is necessary to separate it into an integer part and a fraction part, since each part must be converted differently. The conversion of a decimal integer to a number in base “r“ is done by
dividing the number and all successive quotients by “ r “ and accumulating the remainders.
The conversion of a decimal fraction to base “ r “ is accomplished by a method similar to that used for integer, except that multiplication by “ r
“ is used instead of division, and integers are accumulated instead of remainders.
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Example
Find the binary equivalent of (41.6875)10
Separate the number into an integer part & a fraction part.
Integer Part:
2
2
2
2
2
2
41
20 + ½
10
5
2 + ½
1
0 + ½
= 1
= 0
= 0
= 1
= 0
= 1
LSB
MSB
remainder
(41)10 = (101001)2
Fraction Part:
0.6875 x 2 = 1.3750
0.3750 x 2 = 0.7500
0.7500 x 2 = 1.5000
0.5000 x 2 = 1.0000
1 0 1 1
MSB
LSB
Integer
( .6875)10 = ( .1011)2
Thus: (41.6875)10 L (101001.1011)2
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Important Note
The process of multiplying fractions by “ r “ does not necessarily end with zero, so we must stop at a certain accuracy , i.e. number of fraction digits, otherwise this process might go forever.
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Octal Numbers
Octal number system is a base 8 system with eight digits [ 0,1,2,3,4,5,6,7 ].
To find the equivalent decimal value, we expand the number in a power series with a base of “ 8 ”.
Example:(127.4)8 = 1 x 82 + 2 x 81 + 7 x 80 + 4 x 8-1
= (87.5)10
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Hexadecimal Numbers
The Hexadecimal number system is a base 16 system with the first ten digits borrowed from the decimal system and the letters A,B,C,D,E,F are used for digits 10,11,12,13,14 and 15 respectively.
To find the equivalent decimal value, we expand the number in a power series with a base of “ 16 ”.
Example:(B65F)16 = 11 x 163 + 6 x 162 + 5 x 161 + 15 x 160
= (46687)10
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Note
It is customary to borrow the needed “ r “ digits for the coefficients from the decimal system, when the base of the numbering system is less than 10.
The letters of the alphabet are used to supplement the digits when the base of the number is greater than 10.
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DecimalBinaryOctalHexadecimal
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
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Important Property
The Octal & Hexadecimal systems are useful for representing binary quantities indirectly because they posses the property that their bases are powers of “2”.
Octal base = 8 = 23 & Hexadecimal base = 16 = 24, from which we conclude:Each Octal digit correspond to three binary digitsEach Hexadecimal digit correspond to four binary digits.
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Conversion from Binary to Octal/Hexadecimal
The conversion from Binary to either Octal or Hexadecimal is accomplished by partitioning the Binary number into groups of three or four digits each respectively, starting from the binary point and proceeding to the left and to the right. Then, the corresponding Octal or Hexadecimal is assigned to each group.
Note that, 0’s can be freely added to the left or right to the Binary number to make the total number of bits a multiple of three or four.
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Example
Find the Octal equivalent of the Binary number:
( 10110001101011.11110000011)2
010 110 001 101 011 . 111 100 000 110
2 6 1 5 3 7 4 0 6
(010110001101011.111100000110)2 L(26153.7406)8
Added “0’s”
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Example
Find the Hexadecimal equivalent of the Binary number:
( 10110001101011.11110000011)2
0010 1100 0110 1011 . 1111 0000 0110
2 C 6 B F 0 6
(10110001101011.11110000011)2 L(2C6B.F06)16
Added “0’s”
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Conversion from Octal/Hexadecimal to Binary
Conversion from Octal or Hexadecimal to Binary is done by a procedure reverse to the previous one.
Each Octal digit is converted to a three-digit binary equivalent. Each Hexadecimal digit is converted to its four-digit binary
equivalent.
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Example
Find the Binary equivalent of (673.12)8
6 7 3 . 1 2
110 111 011 001 010
(673.12)8 = (110111011.001010)2
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Example
Find the Binary equivalent of (3A6.C)16
3 A 6 . C
0011 1010 0110 1100
(3A6.C)16 = (110111011.001010)2
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Important Note
The Octal or Hexadecimal equivalent representation is more convenient because the number can be expressed more compactly with a third or fourth of the number of digits.
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Arithmetic 1 + 1 = 10
Binary 1 + 1 = 1
Two digitsCarry
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Arithmetic operations with numbers in base “ r “ follow the same rules as for decimal numbers
Addition11
Augend10110
Addend+10011
Sum101001
Subtraction22
Minuend10110
Subtrahend-10011
Result00011
Arithmetic Operations
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Arithmetic Operations (cont.)
Multiplicand1011
Multiplierx101
1011
0000
1011
Product110111
Multiplication Division111010111010
11011110
10010
1110
01001
0000
10010
1110
100
1110
1001101
14
413
14
186
dividenddivisor
subtract
remainder
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Notes
The rules for subtraction are the same as in decimal, except that a borrow from a given column adds “2” to the minuend digit.
In division, we have only two choices for the greatest multiple of the divisor Zero and the divisor itself.
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Arithmetic Operations with Base “r” Systems
Arithmetic operations with Octal , Hexadecimal or any other base “r” system is done by using the following methods:
Formulation of tables from which one obtains sums and products of two digits in base “r”.
Converting each pair of digits in a column to decimal , add the digits in decimal, and then convert the result to the
corresponding sum and carry in base “r” system.
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Example
Add : (59F)16 + (E46)16
Hexadecimal
59F
+E46
13E5
Equivalent Decimal
1
5915
+144 6
1914 21
=16+5
Carry 1
=16+3
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Note
The idea is to add F+6 in hexadecimal, by adding the equivalent decimals 15+6 = 21, then converting (21)10 back to hexadecimal knowing that;
21 = 16+5 gives a sum digit of 5 and a
carry “1” to the next higher
order column digit
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Multiplication
The multiplication of two base “r” numbers is done by performing all arithmetic operations in decimal and converting intermediate results one at a time.
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Example
Multiply (762)8 x (45)8
OctalOctalDecimalOctal
7625 x 210=8+212
455 x 6 +131=24+737
46725 x 7 + 338=32+646
37104 x 28=8+010
437724 x 6 +125=24+131
4 x 7 + 331=24+737
carry
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Complements
Complements are used to simplify the subtraction operation and for logical manipulation.
Types
Radix Complement Diminished radix Complement
r’s complement (r-1)’s complement
Given n-digit number N in base r, its r’s complement is;
0 0
0
N
NNr n
Given n-digit number N in base r, its r’s complement is;
Nr n )1(
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Important Notes
The r’s complement is obtained by adding “1” to the (r-1)’s complement.
r’s complement of N can be formed by leaving all least significant 0’s unchanged, then subtracting the first nonzero least significant digit from “r”, and subtracting all higher significant digits from (r-1).
(r-1)’s complement of N can be formed by subtracting each digit from (r-1).
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Examples
10’s complement of : 246700 7533009’s complement of : 246700 753299
106-246700
(106-1)-246700
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Binary 1’s & 2’s Complements
Note that ; 2n = a binary number which consists of a “1” followed by n 0’s.
2n – 1= a binary number represented by n 1’s.2’s complement is formed by leaving all least significant 0’s
and the first “1” unchanged, then replacing 1’s with 0’s and 0’s by 1’s in all other higher significant bits.
1’s complement is obtained by changing 1’s to 0’s and 0’s to 1’s.
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Note
The (r-1)’s complement of Octal or Hexadecimal numbers is obtained by subtracting each digit from 7 or f (15) respectively.
If the number contains a radix point, then the point should be removed temporarily in order to form the r’s or (r-1)’s complement. The radix point is then restored to the complemented number in the same relative position.
The complement of the complement restores the number to its original value.
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Subtraction with Complements
The subtraction method that is based or uses the borrow concept is less efficient than the method that uses complements, when subtraction is implemented with digital hardware.
The subtraction of two n-digit unsigned numbers, M-N in base “r” is done as follows:
1. Add the minuend M to the r’s complement of the subtrahend N;M + (rn – N) = M- N + rn
2. If M≥N, the sum will produce an end carry rn, which is discarded, what is left is the result “ M-N “.
3. If M < N, the sum does not produce an end carry and is equal to rn – (N-M)
which is the r’s complement of (N-M). to obtain the answer in a familiar form, take the r’s complement of the sum and place a negative sign in front.
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Example (using 10’s complement)
Consider the two numbers 72532 & 3250, it is required to apply the rules for subtraction with complements with these two numbers, thus we have two cases:
Case # 1: M = 72532 & N = 3250, required M-N. In this case M > N Note that M has 5-digits and N has only 4-digits, rule number 1: both
numbers must have the same number of digits. Note also,, the occurrence of the end carry signifies that M > N and the
result is positive.
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M – N = 72532 – 03250
72532 72532
-03250 + 96750 10’s Complement
1 69282 sum
69282 is the required answer
Discard the end carry
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Example (using 10’s complement)
Case # 2: M = 3250 & N = 72532, required M-N.In this case M < NNote that M has 5-digits and N has only 4-digits, rule
number 1: both numbers must have the same number of digits.
Note also,, the absence of the end carry signifies that M < N and the result is negative.
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M – N = 03250 - 72532
03250 03250
-72532 + 27468 10’s Complement
30718 sum
The required answer = - ( 10’s complement of 30718)
= - 69282
no carry
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Notes
When subtracting with complements, the negative answer is recognized by the absence of the end carry and the complemented result.
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Subtracting with (r-1)’s Complements
The (r-1)’s complement can be used when subtracting two unsigned numbers as the (r-1)’s complement is one less than the r’s complement. Thus the result of adding the minuend to the complement of the subtrahend produces a sum which is one less than the correct difference when an end carry occurs.
Removing the end-carry and adding one to the sum is referred to as an end-around carry.
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1’s Complement
Example:
X – Y = 1010100 – 1000011
1010100 1010100
-1000011 + 0111100 1’s Complement
1 0010000 sum
1 End-around carry
0010001 answer (X-Y)
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1’s Complement (cont.)
Example (cont.):
Y – X = 1000011 – 1010100
1000011 1000011
-1010100 + 0101011 1’s Complement
1101110 sum
Note that, there is no carry in this case
Answer = Y – X = - ( 1’s complement of 1101110)
= - 0010001
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Signed Binary Number
Positive integers including zero can be represented as unsigned numbers.Because of hardware limitations, computers must represent
everything with 1’s & 0’s, including the sign of a number.The sign is represented with a bit, placed in the left-most
position of the number, where: 0 = positive sign & 1 = negative sign
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Binary number
The left most bit represents the sign and the rest of the bits represent the number
The left most bit is the most significant bit of the number
Binary Number
Signed number Unsigned number
X 1 0 1 0 1 0 1 0 1 1
The left most bit
X = 0 +ve
X = 1 -ve
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Signed & Unsigned numbers
01001
Unsigned 9
Signed + 9
11001
Unsigned 25
Signed - 9
Signed-magnitude System
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In computers, a signed-complement system is used to represent a negative number, i.e. negative number is
represented by its complement.
- 9
Signed-magnitude representation 10001001
+ 9 0 0001001
8-bit representation
Signed-1’s complement representation 11110110
Signed-2’s complement representation 11110111
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The addition of two signed numbers, with negative numbers represented in signed 2’s complement form, is obtained from
the addition of the two numbers including their sign bits. A carry out of the sign bit position is discarded.
Note that the negative numbers must be initially in 2’s complement and the sum obtained after the addition, if
negative, is in 2’s complement form.
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We must ensure that the result has sufficient number of bits to accommodate the sum, if we start with two n-bit numbers and
the sum occupies n+1 bits, we say that an overflow occurs.
+ 6 0000 0110
+ 13 0000 1101
+ 19 00010011
+ 6 0000 0110
- 13 1111 0011
- 7 1111 1001
2’s complement
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Note that binary numbers in the signed-complemented system are added and subtracted by the same basic addition and subtraction rules as unsigned numbers, therefore, computers need only one common hardware circuit to handle both types of arithmetic.
The user / programmer must interpret the results to distinguish between signed and unsigned numbers
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Decimal Codes
The binary code is a group (string) of n bits that assume up to distinct combinations of 1’s and 0’s, with each combination representing one element of the set that is being coded, the bit combination of an n-bit code is determined from the count in binary from 0 to -1.
Each element must be assigned a unique binary combination and no two elements can have the same value
n2
n2
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Binary Coded Decimal “BCD”DecimalBCD
0
1
2
3
4
5
6
7
8
9
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
012 2 2 2 32
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Note , a number with “n” decimal digit will require “4n” bits in BCD.
Note also, a decimal number in BCD is the same as its equivalent binary number, only when the number is between 0 – 9. A BCD number > 10 looks different from its equivalent binary number.
The binary combinations 1010 – 1111 are not used and have no meaning in the BCD.
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It is important to realize that BCD numbers are decimal numbers and not binary numbers.
210 101110010101 1000 0001185 BCD
12 bit 8 bit
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BCD Addition
Each digit in a BCD does not exceed 9, the sum can not be greater than 9+9+1 = 19, where the “1” being a carry.
The binary sum will produce a result in the range from 0 to 19, in binary it correspond to 0000 – 10011, but in BCD
0000 – 1 1001, thus when the binary sum is equal to or less 1001 (without a carry) the corresponding BCD is correct.
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BCD Addition (cont.)
When the binary sum is , the result is an invalid BCD digit.
To correct this problem, add binary 6 (0110) to the sum, which converts the sum to a correct BCD digit and produces a carry as required.
The value 6 corresponds to the 6 invalid combinations in the BCD code (1010 – 1111).
1010
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Examples
4 0100
+ 5 0101
9 1001
4 0100
+ 8 1000
12 1100
0110
1 0010
8 1000
+ 9 1001
17 1 0001
0110
1 0111
Sum greater than 9 Sum greater than 16
carry
Add 6
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Example (2)
1 1 BCD carry
184 0001 1000 0100
+ 576 0101 0111 0110
0111 0000 1010 Binary sum
0110 0110 add 6
760 0111 0110 0000 BCD sum
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BCD Multiplication
Multiply 15 x 16 in BCD
15 5 x 6 = 30 L0011 0000
x 16 6 x 1 + 3 = 9 L1001
1001 0000 1 x 5 = 5 L0101
0001 0101 1 x = 1 L0001
0010 1110 0000
0110
0010 0100 0000
1
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For signed decimal numbers, the sign is represented with “Four” bits to conform with the 4-bit code of the decimal digits, where:
-ve sign = 1001 (9)
+ve sign = 0000 (0)Many computers have special hardware to perform arithmetic
calculations directly with decimal numbers in BCD.
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Other Decimal Codes
Binary codes for decimal digits require a minimum 4-bits per digit. BCD 8 4 2 1 Repeated code 2 4 2 1 Excess-3 code Negative code 8 4 -2 -1 Weighted
codes
012 2 2 2 32
Note, some digits can be coded in two possible ways
Always add 3 (0011) to the original binary number, e.g
0000 0011
0001 0100 and so on
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Other Decimal Codes (cont.)
The 2421 & Excess-3 codes are self-complementing codes, i.e. the 9’s complement of a decimal number is obtained directly by changing 1’s to 0’s and 0’s to 1’s.
BCD is not a self-complementing codeThe 84-2-1 accepts positive & negative weights.
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Notes
You should distinguish between conversion of a decimal number to binary and the binary coding of a decimal number.
It is important to realize that a string of bits in a computer sometimes represents a binary number and at other times it represents information as specified by a given binary code.
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Alphanumeric Codes
ASCII = American Standard Code for
Information Interchange ASCII consists of 7-bits to code 128 characters
26 upper-case letters [ A,B,C,…]
26 lower-case letters [a,b,c,….]
10 decimal numbers [ 0- 9]
32 special printable characters [ #,$,%,&,*,…..]
34 control characters (non-printing C/Cs)
128 characters
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Note that, binary codes merely change the symbols not the meaning of the element of information.
The 34 control characters are used for routing data and arranging the printed text into the prescribed format
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The 34 control Characters
Control Characters
Format effectors Information separatorsCommunication
Control characters
Layout of printingSeparate data into
paragraphs & pages
Transmission of textbetween remote
terminals
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Parity bit
ASCII code was modified to 8-bits instead of 7-bits. (ASCII is 1 byte in length)
1 byte = 8 bitsThe extra bit, whose position is in the most significant bit
[ default is “0”] , is used for:Providing additional symbols such as the Greek Alphabet
or italic type format……etcIndicating the parity of the character when used for data
communication.
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Parity bit (cont.)
The parity bit is an extra bit included to make the total number of 1’s in a row either even or odd.
The bit is helpful in detecting errors during the transmission of information from one location to another.
0
1
1
1
0011101
0011010
0101001
0011001
Even parity
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Other Alphanumeric Codes
EBCDIC = Extended BCD Interchange Code, used in IBM. It is 8-bits for each character and a 9th bit for parity.
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Binary Logic
Digital circuits are hardware components that manipulate binary information.
Gates are circuits that are constructed with electronics components [ transistors, diodes, and resistors]
Boolean algebra is a binary logic system which is a mathematical notation that specifies the operation of a gate [ Boolean => the English mathematician “George Boole” 1854 ]
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Electrical Signals [ voltages or currents ] that exist throughout a digital system is in either of two recognizable values [ logic-1 or logic 0 ]
Voltage
time
Logic – 1 range
Logic – 0 range
Transition , occurs between the two limits
Intermediate region, crossed only during state transition
5
0.8
0
2
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You should distinguish between binary logic and binary arithmetic. Arithmetic variables are numbers that consist of many digits. A logic variable is always either 1 or 0.
A Truth Table is a table of combinations of the binary variables showing the relationship between the values that the variables take and the result of the operation.
The number of rows in the Truth Table is , n = number of variables in the function.
The binary combinations are obtained from the binary number by counting from 0 to
n2
12n
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Arithmetic 1 + 1 = 10
Binary 1 + 1 = 1
Two digitsCarry
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Binary Logic
AND OR NOT (inverter)
-Represented by any of the following notations:
• X .AND. Y
• X . Y
• X Y
-Function definition:
Z = 1 only if X=Y=1
0 otherwise
-Represented by any of the following notations:
• X .OR. Y
• X + Y
• X v Y
-Function definition:
Z = 1 if X=1 or Y =1 or both X=Y=1
0 if X=Y=0
-Represented by a bar over the variable
•
-Function definition:
Z is what X is not
-It is also called complement operation , as it changes 1’s to 0’s and 0’s to 1’s.
X
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Binary Logic
AND OR NOT (inverter)
-Symbol:
-Truth Table
-Symbol
-Truth Table
-Symbol
-Truth Table
XYZ
0
0
1
1
0
1
0
1
0
0
0
1
XYZ
0
0
1
1
0
1
0
1
0
1
1
1
XZ
0
1
1
0
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AND and OR gates may have more than two inputs.Timing diagrams illustrate the response of any gate to all
possible input signal combinations. The horizontal axis of the timing diagram represents time and
th vertical axis represents the signal as it changes between the two possible voltage levels
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Timing Diagram
input 1 X 0 0 1 1
input 2 Y 0 1 0 1
AND X . Y 0 0 0 1
OR X + Y 0 1 1 1
NOT X 1 1 0 0
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Logic Function Definition
Language descriptionFunction descriptionBoolean EquationGraphic SymbolsTruth Table Timing DiagramCoding (HDL)
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Other Gates
NAND = AND-Invert NOR – Invert-OR XOR ( odd )
-Symbol:
-Truth Table
-Symbol
-Truth Table
-Symbol
-Truth Table
XNOR (even )
-Symbol
-Truth Table
YXZ YXZ
XYZ
0
0
1
1
0
1
0
1
1
0
0
1
XYZ
0
0
1
1
0
1
0
1
0
1
1
0
XYZ
0
0
1
1
0
1
0
1
1
1
1
0
XYZ
0
0
1
1
0
1
0
1
1
0
0
0
Z = X . Y Z = X + Y
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Building the Basic Functions from Other gates
A A NOT (inverter)
Using NAND Gates Basic Function Using NOR Gates
A
BAB
AND
A
B
A+B OR
AA
A+B
ABA
B
A
B
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Boolean Algebra
It is an algebra that deals with binary variables and logic operations:
A Boolean function consists of:An algebraic expression formed with binary variables.The constants “0” and “1”The logic operation symbol ( . , +, NOT)Parentheses and an equal sign
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Example
Given a logic function “F”, defined as follows:
F = 1 if X = 1 or if both Y & Z are equal to 1
0 otherwise The logic equation that represents the above function is given
by:
ZYXF
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The truth table for the given function is as shown.
The Boolean function can be transformed from an algebraic expression into a circuit diagram composed of logic gates.
XYZF
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
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Logic Circuit Diagram
ZYXF
X
Y
Z
ZYXF
Note : the number of inputs equal the number of variables
output
Complement = need an inverter
AND
OR
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Notes
There is only one way to represent a Boolean function in a Truth Table, where there are a variety of ways to represent the function when it is in algebraic form.
By manipulating a Boolean expression according to Boolean Algebra rules, it is sometimes possible to obtain a simpler expression for the same function, thus reducing the number of gates in the circuit.
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Basic Identities of Boolean Algebradescription
Commutative
Associative
Distributive
DeMorgan
X + 0 =X
X + 1 = 1
X + X = X
X + X = 1
X = X
X + Y = Y +X
X+(Y+Z) = (X+Y)+Z
X(Y+Z) = XY + XZ
X . 1 = X
X . 0 = 0
X . X = X
X . X = 0
XY = YX
X(YZ) = (XY)Z
X+YZ=(X+Y)(X+Z)
Y.XYX YXY.X
Duality
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Duality
The dual of an algebraic expression is obtained by interchanging OR and AND operations and replacing 1’s by 0’s and 0’s by 1’s.
Notice that when evaluating an expression, the complement over a single variable is evaluated first , then the AND operation and the OR operation
( ) NOT AND OR
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Extension of DeMorgan’s Theorem
n321n321
n321n321
X..XXXX.....X.X.X
X..X.X.XX...XXX
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Algebraic Manipulation
XX.1 using XZ YX
1XX using XZ Y.1X
XZXYZ)X(Y using XZZZYX
XZZYXYZXF
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XZZYXYZXF
XZYXF
X Y Z F0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1
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The Consensus Theorem
Which Shows that the term YZ is redundant and can be eliminated Proof:
ZXXYYZZXXY
ZX XY
Y)Z(1XZ)XY(1
YZXZXXYZXY
YZXXYZZXXY
)XX(YZZXXYYZZXXY
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The Dual of Consensus Theorem
Notice that, two terms are associated with one variable and its complement and the redundant term is the one which not contain the same variable.
ZXYXZYZXYX
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Complement of a Function “F”
The complement of a function “F” is obtained by interchanging 1’s to 0’s and 0’s to 1’s in the values of “F” in the Truth Table.
OR, it can be derived algebraically by applying DeMorgan’s Theorem.
The complement of an expression is obtained by interchanging AND and OR operations and complementing each variable.
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Example
Or by taking the dual of the expression: The original function The dual of F Complement each literal
The complement of a function is done by taking the dual of the function and complement each literal.
ZYX.ZYX
ZYX.ZYX
ZYXZYXF
ZYXZYXF
ZYXZYX F
ZYX.ZYXF
ZYXZYXF
dual
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Standard Forms
A product term in which all the variables appear exactly once either complemented or uncomplemented is called a “minterm”, note that there are distinct “minterm” for n-variables.
Standard Forms
Product terms Sum Terms
AND operation among several variables
0 = complemented variable
1 = uncomplemented variable
OR operation among several variables
1 = complemented variable
0 = uncomplemented variable
n2
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An algebraic expression representing the function is derived from the Truth Table by finding the logical sun of all product terms for which the function assumes the binary value of “1”.
A symbol for each minterm , where “j” denotes the decimal equivalent of the binary number of the minterm.
A sum term that contain all the variables in complemented or uncomplemented form is called “maxterm”, symbol
Note that
jm
jM
jjmM
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term symbol sum symbol0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 11 1 0 01 1 1 1
SUMFX Y Z
Product
YZX
ZYXZYXZYX
ZYXZYXZXY
XYZ
0m
1m
2m
3m
4m
5m
6m
7m
ZYX ZYX ZYX ZYX ZYX ZYX ZYX ZYX
0M
1M
2M
3M
4M
5M
6M
7M
Example
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Example
Sum of Product SOP
Product of Sum POS
Note that the decimal numbers included in the product of maxterms will always be the same as the minterm list of the complement function
6,4,3,1mF
0,2,5,7m
m m m m
XYZZYXZYXZYXF
7520
1,3,4,6M
ZYXZYXZYXZYX
mmmm
mmmm
MMMMF
6431
6431
6431
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Properties of minterm
1. There are minterm for n-Boolean variables which can be evaluated from the binary numbers 0 to
2. Any Boolean function can be expressed as a logical sum of minterms.
3. The complement of a function contains those minterms not included in the original function
4. A function that includes all minterms is equal to logic-1.
n2
n2
12n
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AND gates followed by OR gate forms a circuit configuration that is referred to as a Two-Level implementation (SOP).
Two-Level implementation is preferred as it produces the least amount of delay time through the system.
Delay is defined as the time that a signal spends to propagate from input to output.
Also, Product of Sum (POS) is a two-level implementation, as it consists of a group of OR gates followed by an AND gate.
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Example
CE CD AB EDCABF
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Karnaugh map (k-map)
Each square corresponds to a row of the Truth-Table and to one minterm of the algebraic equation.
Only one digit changing value between two adjacent rows and columns. One square represent one minterm, giving a term of four variables (in case
of 4-varaiable map). Two adjacent squares represent a term of three literals Four adjacent squares represent a term of two literals. Eight adjacent squares represent a term of one literal. Sixteen adjacent squares represent F=1. When a variable appears within a group in both inverted and non-inverted
state, then the variable can be eliminated.
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K-map Procedure
Fill the map from the Truth-Table. Look at 1’s (where F=1). Make the biggest group possible:
Any square can appear in more than one group. Get expression for each group. OR all expressions.
•Squares in a group = , n=0,1,2,…
•Adjacent cells
•Cover all 1’s
n2
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0 0 0 1 1 1 1 00 0 0 1 3 2
0 1 4 5 7 6
1 1 12 13 15 14
1 0 8 9 11 10
CDAB Cell
One digit change value at a time
DCBA
SOP DCBA
POS
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Note that there are cases where two squares in the map are considered to be adjacent,, even though they do not touch each other.
0 0 0 1 1 1 1 00 0 1 3 2
1 4 5 7 6
YZ
X
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Example
14,13,12,9,8,6,5,4,2,1,0mD,C,B,AF
0 0 0 1 1 1 1 00 0 0 1 3 2
0 1 4 5 7 6
1 1 12 13 15 14
1 0 8 9 11 10
CDAB
DBDACF
1
1
1
1
1
1
1
1
1
1
1
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Example 2
CBADBCADCBCBAD,C,B,AF
0 0 0 1 1 1 1 00 0 0 1 3 2
0 1 4 5 7 6
1 1 12 13 15 14
1 0 8 9 11 10
CDAB
DCACBDBF
1 1
1
1
1
1
1
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Prime Implicant
A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map.
If a minterm in a square is covered by only one prime implicant , that prime implicant is said to be essential.
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0 0 0 1 1 1 1 00 0 1 3 2
1 4 5 7 61 1
11 1
YZX
ZYZXZX
YXZXZXF
implicants prime essential-non ZY & YX
implicants prime essential ZX & ZX
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Example 1
0 0 0 1 1 1 1 00 0 0 1 3 2
0 1 4 5 7 6
1 1 12 13 15 14
1 0 8 9 11 10
1
1 1
1
1
1
1
1
BADBDAF
essential prime implicants
Non-essential prime implicant
CDAB
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Note that, once the essential prime implicants are taken, the third term is not needed (redundant), as all the minterms are already covered by the essential prime implicants, thus:
DBDAF
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Example 2
ABD
ACDCBACABDCBDCBAF or
0 0 0 1 1 1 1 00 0 0 1 3 2
0 1 4 5 7 6
1 1 12 13 15 14
1 0 8 9 11 101
1
1
1
1
1
1
CDAB
Non-essential
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Complement of a Function
The complement of a function is represented in the K-map by the squares (cells) not marked by 1’s.
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Product of Sums (POS)
To represent any function as a product of sums (POS), we take the dual of and complementing each literal, i.e. we get: F
FF
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Example
10,9,8,5,2,1,0D,C,B,AF
DBDCBAF
literaleach ingcomplement
DBDCBAF dual
DBCDABF
CD
AB
1 1
1
1 1 1
0 0 0 1 1 1 1 00 0 0 1 3 2
0 1 4 5 7 6
1 1 12 13 15 14
1 0 8 9 11 10
1
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Don’t Care Terms
There are applications where the function is not specified for certain combinations of variables, e.g. the four-bit binary code (BCD code) where there are six combinations from 10 – 15 which are not used and consequently are considered as unspecified.
These unspecified minterms are called “don’t care” terms and can be used on a map to provide further simplification of the function by considering it as 1’s or 0’s (depending on the situation).
Don’t care terms are represented by a cross “X” in the map.
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Example
DACDFBACDF 21 Algebraically these two functions are not equal , as both covers
different don’t care minterms, but the original function is satisfied as don’t care terms will not affect the original function
0 0 0 1 1 1 1 00 0 0 1 3 2
0 1 4 5 7 6
1 1 12 13 15 14
1 0 8 9 11 10
CDABX
X
X1 1
1
1
1
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K-map with more than 4-variables
Five-variable map needs 32-cell Six-variable map needs 64-cell & so on. In general, maps with six or more variables needs too many
cells and they are impractical to be analyzed manually, there special program (simulation programs) that can handle such situation.
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5-variables Map
We use two four-variables maps, the first one has a the variable A=0 as a common factor, and the second has a common factor A=1.
Each cell in the A=0 map is adjacent to the corresponding cell in the A=1 map, e.g.
Any adjacent cells , k=0,1,2,3,4, in the 5-variable map represents a product term of 5-k literals.
3115204 mm&mm
ka
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5-variables map
0 0 0 1 1 1 1 00 0 0 1 3 2
0 1 4 5 7 6
1 1 12 13 15 14
1 0 8 9 11 10
0 0 0 1 1 1 1 00 0 16 17 19 18
0 1 20 21 23 22
1 1 28 29 31 30
1 0 24 25 27 26
DEBC
DEBC
A=0 A=1
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Example )31,29,25,23,21,13,9,6,4,2,0(),,,,( mEDCBAF
0 0 0 1 1 1 1 00 0 0 1 3 2
0 1 4 5 7 6
1 1 12 13 15 14
1 0 8 9 11 10
0 0 0 1 1 1 1 00 0 16 17 19 18
0 1 20 21 23 22
1 1 28 29 31 30
1 0 24 25 27 26
1
1
1
1
1
1
1 1
1 1
1
A=0 A=1
DE DE
BC BC
common
ACEEDBEBAF
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Other Gates
NAND = AND-Invert NOR – Invert-OR
-Symbol:
-Truth Table
-Symbol
-Truth Table
-Symbol
-Truth Table
XZ
Buffer
Z = X + YZ = X . Y
XZ
0
1
0
1
XYZ
0
0
1
1
0
1
0
1
1
1
1
0
XYZ
0
0
1
1
0
1
0
1
1
0
0
0
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NAND and NOR gates are more popular than AND and OR gates, as they are easily constructed with electronic circuits and Boolean functions can be easily implemented with them.
X
Y
X
YXY XYYX
AND-invert Invert-OR
Two Graphic Symbols for a NAND gate
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Two Graphic Symbols for a NOR gate
X
Y
X
YYX YXYX
OR-invert invert-AND
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The implementation of Boolean functions with NAND gates requires that the function be in the SOP form.
CDABF Double inversion
AND & OR gates
NAND gatesMixed notation, both AND-invert & invert-
OR are present
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Example
7,5,4,3,2,1m)Z,Y,X(F
ZYXYXF
0 0 0 1 1 1 1 00 0 1 3 2
1 4 5 7 6
1 1 1
111
XY
XY
Z
F
Note that Z must have a one-input NAND gate to compensate for the small circle in
the second level gate X
Y
XY
Z
F
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Steps to Configure SOP with NAND gates
1. Simplify the function (SOP)
2. Draw a NAND gate for each product term and the inputs to each NAND gate are the literals of the product term. (group of the first-level gates)
3. Draw a single gate using AND-invert or invert-OR graphic symbol in the second level.
4. A term with a single literal requires an inverter in the first level.
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Another Rule for converting AND/OR into NAND
1. Convert all AND/OR using AND-invert/invert-OR.
2. Check all the small circles in the diagram. For every small circle that is not counteracted by anther small circle along the same line, insert an inverter (one-input NAND gate) or complement the input variable.
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Example DCBABAF
AB
AB
CD
F
AB
AB
CD
F
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Exclusive-OR Gate / Equivalence gate
XOR ( odd )
-Symbol
-Truth Table
-Symbol
-Truth Table
XNOR (even )
YXYX
YXZ
YXXY
YXZ
XOR is equal to “1” if only one variable is equal to “1” but
not both
XYZ
0
0
1
1
0
1
0
1
1
0
0
1
XYZ
0
0
1
1
0
1
0
1
0
1
1
0
XNOR is equal to “1” if both X & Y are equal
to “1” or both are equal to “0”
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XOR/XNOR identities
ZYX)ZY(XZ)YX(:eAssociativ
XYYX:eCommutativ
YXYX
YXYX
1XX
0XX
X1X
X0X
XYZZYXZYXZYX
Z)YXXY(ZYXYXZYX
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Parity Generation & Checking
It used for error detection.The circuit that generates the parity bit in the transmitter is
called a parity generator.The circuit that checks the parity in the receiver is called a
parity checker.
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Even parity generator/checker
X Y Z P C0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 01 0 0 1 01 0 1 0 01 1 0 0 01 1 1 1 0
PZYXC
ZYXP
Parity generator Parity Checker
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Transmission Gates
This gate is available with CMOS type electronic circuits.
TGX Y
C
C
Pass signal Open Switch0C
1C
1C
0C
X & Y are inputs
C & are control inputs C
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Using Transmission gates to construct An Exclusive-OR gate (XOR)
TG1
TG2
YXYX
YXZ
XYTG1TG2Z
0
0
1
1
0
1
0
1
Close
Close
Open
Open
Open
Open
Close
Close
0
1
1
0
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Integrated Circuits
It is a small silicon semiconductor crystal, called a chip, containing the electronic components for the digital gates.
Number of pins may range from 14 in a small OC package to 64 or more in a large package.
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Levels of Integration
Small Scale Integration
SSI
Medium Scale Integration
MSI
Large Scale Integration
LSI
Very Large Scale Integration
VLSI
Ultra Large Scale Integration
ULSI
•Thousands for gates
•Large memory arrays
•Complex microprocessors
•No. of gates < 10
•Inputs & outputs are connected directly to the pins
•10 -100 gates
•Decoder
•Adders
•Registers
•100 – few thousands gates
•Processors
•Memory chips
•Programmable modules
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Logic Circuits Technology
Basic circuits in each technology is a NAND, NOR or an inverter.
Digital Logic Families
DTL TTL ECL MOS CMOS
Diode-Transistor Logic
Transistor-Transistor Logic
Emitter-Coupled Logic
Metal-Oxide Semiconductor
Complementary Metal-Oxide
Semiconductor
•Diodes/transistors
•Power supply 5 V
•Two logic levels [0V - 3.5V]
•Standard
•High speed operation
•Super computers
•Signal processors
•High component density
•Simple processing technique during fabrication
•Low power consumption
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Notes
There are many type of the TTL familyHigh-speed TTLLow-power TTLSchottky TTLLow-power Schottky TTLAdvanced Low-power Shcottky TTL
ECL gates operates in a nano-saturated state, a condition that allows the achievement of propagation delays of 1-2 nanoseconds.
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Important Parameters that are evaluated and compared
Fan-outPower-dissipationPropagation delayNoise margin
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Fan-out
It specifies the number of standard loads that the output of a typical gate can drive without impairing its normal operation.
A standard load is usually defined as the amount of current needed by an input of another similar gate of the same family.
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Power Dissipation
It is the power consumed by the gate which must be available from the power supply.
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Propagation Delay
It is the average transition delay time for the signal to propagate from input to output when the binary changes in value. The operating speed is inversely proportional to the propagation delay.
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Noise Margin
It is the maximum external noise voltage that causes an undesirable change in the circuit output.
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Positive & Negative Logic
Choosing the high-level “H” to represent logic “1” defines a positive logic system.
Choosing the low-level “L” to represent logic “1” defines a negative logic system.
Positive logic Negative logic
Logic value Logic valueSignal value Signal value
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The signal values “H” & “L” are usually used in the components data sheets
The actual truth table is defined according to the definition of “H” and “L” in the data sheet.
Notes
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XYZ
0
0
1
1
0
1
0
1
1
1
1
0
XYZ
0
0
1
1
0
1
0
1
0
0
0
1
XYZ
L
L
H
H
L
H
L
H
L
L
L
H
TTL Gate
X
YZData
Sheet
YY
XXZ
Z
These small triangle in the inputs & output designate a
polarity indicator
Depending on the definition of H & L in the data sheet
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Logic Circuits
Consists of logic gates whose outputs at any time are determined directly from the values of the present inputs.
No feedback or storage elements are involved.
It involves storage elements (Flip-Flops).
Outputs are a function of inputs and the state of the storage elements, where the state of the storage elements is a function of the previous inputs.
Circuit behavior must be specified by a time sequence of inputs and internal states.
Logic Circuits
Combinational Sequential
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Logic Circuits
Logic Circuits
Combinational Sequential
Combinational Circuit
m
outputs
n
inputs
n2 possible input combination
One possible output for each
binary combination of input variables
Combinational Circuit
Storage
elements
Present state
Next
state
Inputs Outputs
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A sequential circuit is specified by a time sequence of inputs, outputs and internal states. It contain memory and thus can remember the changes of input signals that occurred in the past.
Inputs for the sequential circuit are functions of external inputs and the present state of the storage elements.
Both external inputs and the present states determine the binary value of the outputs and the condition for changing the state of the storage state.
Outputs = f( external inputs , present states)
Next state = f( external inputs , present states)
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Analysis Procedure
To obtain the output Boolean functions from a logic diagram:
1. Label all gate outputs that are a function of input variables with arbitrary symbols. Determine the Boolean functions for each gate.
2. Label the gates that are a function of input variables and previous labeled gates with different arbitrary symbols. Find the Boolean functions for these gates.
3. Repeat step 2 until the outputs of the circuit are obtained in terms of the input variables.
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Example
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DBADTT
DBADDBAD)BA(DTT
CBATAT
BATCBT
25
24
13
21
,
Thus the Boolean functions of F1 and F2 are:
DBATF
DBDBCBA
DBADDBACBATTF
52
431
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Another Way using the Truth Table
1. Determine the number of input variables in the circuit for n-inputs, list the binary number from 0 to 2n-1 in a table.
2. Label the outputs of the selected gates with arbitrary symbols.
3. Obtain the Truth Table for the outputs of those gates that are a function of the input variables only.
4. Proceed to obtain the Truth Table for the outputs of those gates that are a function of previously defined values until the columns for all outputs are determined.
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ABCDT1T2T3T4T5F1F2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
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Design Procedure
1. Form the specifications of the circuit, determine the required number of inputs and outputs and assign a letter (symbol) to each.
2. Derive the Truth Table that defines the required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a function of the input variables.
4. Draw the logic diagram.
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Need to Accomplish
1. Minimum number of gates
2. Minimum number of inputs to a gate
3. Minimum propagation delay of the signal through the gates
4. Minimum number of interconnections
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Example
Design a combinational circuit with three inputs and one output. The output must equal “1” when the inputs are less than three and “0” otherwise. [use only NAND gates]
XYZF
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
0
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0 0 0 1 1 1 1 00 0 1 3 2
1 4 5 7 6
1 1 1
YZX
ZXYXF
Mixed-symbol notation
XY
Z
ZXYXF
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Note
When a combinational circuit has two or more outputs, each output must be expressed separately as a function of all the input variables.
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Code Converter ExampleDecimal
DigitBCD codeExcess-3 code
ABCDWXYZ
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
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00011110
00
01111
11XXXX
1011XX
CDAB
00011110
00111
011
11XXXX
101XX
CDAB
)DC(BA
BDBCAW
DCB)DC(B
DCBDBCBX
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00011110
0011
0111
11XXXX
101XX
CDAB
00011110
0011
0111
11XXXX
101XX
CDAB
DC
DCCDY
DZ
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Logic Diagram of BCD to Excess-3 code Converter
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BCD to Seven-Segment Decoder
Digital read-out found in electronic caculators and digital watches use display devices such as light emitting diodes LED or liquid crystal display LCD, each digit of the display is formed from seven segments.
Each consists of one LED or one crystal which can be illuminated by digital signals.
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ABCDabcdefg
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
10
11
12
13
14
15
All other input combinationsNot valid (don’t care)
a
b
c
g
d
f
e
7-outputs
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We cannot use the don’t care condition here for the six binary combinations 10101 – 1111, as the design will most
likely produce some arbitrary and meaningless display of the unused combinations.
CBACBACBADCAg
CBADBADCACBAf
DCBDCAe
DCBACBADCBCBADCAd
CBADCBDABAc
CBACDADCABAb
CBADCBBDACAa
14 AND gate and 7 OR
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Arithmetic Circuits
An arithmetic circuit is a combinational circuit that performs arithmetic operations such as addition, subtraction,
multiplication and division with binary numbers or with decimal numbers in a binary code.
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 10A combinational circuit that performs the addition of two bits
is called a “Half Adder”.
One digit
Two digits
Carry is added to the next higher
order pair of significant bits
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A combinational circuit that performs the addition of three bits (two significant bits and a previous carry) is called a “Full
Adder”.Two Half Adders are employed to implement a Full Adder.
The Full adder circuit is the basic arithmetic component from which all other arithmetic circuits are constructed.
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Half-Adder
It is an arithmetic circuit that generates the sum of two binary digits.
Half-Adder
XYC
YXYXYXS
InputsOuputs
XYCS
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
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Full-Adder
It is a combinational circuit that forms the arithmetic sum of three input bits.
Carry from the previous lower significant position
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)( YXZXYC
ZYXS
ZYX
XYZZYXZYXZYXS
)(
)(
YXZXY
YXYXZXY
YZXZXYC
InputsOutputs
XYZCS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
00011110
011
111
YZX
00011110
01
1111
YZX
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Binary Parallel Adder
The sum of two n-bit binary numbers can be generated in serial or parallel fashion.
The serial addition method uses only one Full Adder and a Storage device to hold the output carry.
The parallel method uses n-Full Adders and all bits are applied simultaneously to produce the sum.
4-bit Parallel Adder
FA FA FA FA
0A0B1A1B2A2B3A3B
0C1C2C3C
0S4C 1S2S3S
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ExampleA = 1011 B = 0011
Input Carry0110
Augend A1011
Addend B0011
Sum S1110
Output Carry0011
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Binary Adder/Subtractor
The subtraction of binary number can be done most conveniently by means of complements
The subtraction “ A-B “ is done by taking the 2’s complement of “ B “ and adding it to “ A “.
The 2’s complement can be obtained by taking the 1’s complement and adding “1” to the least significant bit.
The 1’s complement can be implemented easily with inverter circuit and we can add “1” to the sum by making the initial
input carry of the parallel adder equal to “1”.
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0A0B1A1B2A2B3A3B
FA FA FA FA 0C1C2C3C
0S4C 1S2S3S
Adder/Subtractor Circuit
S = C0 = 0 additionS = C0 = 1 Subtraction
S
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BCD Adder
An adder that perform arithmetic operations directly with decimal number system employ arithmetic circuit that accept decimal numbers and present
results in the same code. It requires a minimum of nine inputs and five outputs, Four bits to code
each decimal digit and the circuit must have an input and output carry. When C=0 , nothing is added to the binary sum
When C=1, binary 0110 is added to the binary sum through the second 4-bit adder.
Any output carry from the second binary adder can be neglected. A decimal parallel adder that adds two n-decimal digits needs n BCD
adders, the output carry from each BCD adder must be connected to the input carry of the adder in the next higher position.
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4-bit binary adder
4-bit binary adder
K
0S1S2S3S
0Z1Z2Z3Z
C
00
3231 ZZZZKC
Output carry
Output carry from the first Adder
Detect the binary output from 1010 - 1111
Condition for correction:
input
carry
BCD sum
AugendAddend
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Binary Multiplier
The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit.
Such multiplication forms a partial products.Successive partial products are shifted one position to the left.The final product is obtained from the sum of the partial
products.For “j” multiplier bits and “k” multiplicand bits , we need jxk
AND gates and (j-1)k bit adders to produce a product of j+k bits.
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0C1C2C3C
HA HA
0A
1A
0B1B
0B1B
2-bit by 2-bit binary multiplier
B1B0
A1A0
A0 B1A0 B0
A1 B1A1 B0
C3C2C1C0
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Decoders
Discrete quantities of information are represented in digital computers with binary codes.
A binary code of n-bits is capable of representing up to 2n distinct elements of coded information.
A decoder is a combinational circuit that converts binary information from n-coded inputs to a maximum of 2n unique
outputs.A decoder has n inputs and m outputs and is referred to as “
nxm decoder”
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2-to-4 line Decoder with an Enable Input
EA1A0D0D1D2D3
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
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D0
D1
D2
D3
A0
A1
E
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Example
Implement a Full Adder circuit with a decoder and OR gates:
Three inputs a total of eight minterms we need a 3-to-8 line decoder.
This Decoder generates the eight minterms of X,Y,Z.The OR gate for output S forms the logical sum of minterm
1,2,4,aand 7.The OR gate of output C forms the logical sum of minterms
3,5,6 and 7.
)7,6,5,3(m)Z,Y,X(C
)7,4,2,1(m)Z,Y,X(S
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XYZCS
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
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3x8 Decoder
Z
Y
X
S
C
20
21
22
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Encoders
An Encoder has 2n (or less) input lines and n output lines.
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Priority Encoder
It is a combinatinal circuit that implements the priority function. The operation of the priority Encoder is such that, if two or more inputs are
equal to “1” at the same time, the input having the highest priority will take precedence.
The input D3 in the following Truth Table has the highest priority, regardless of the values of the other inputs.
Thus, if D3 is “1” , the output will indicate that A1A0 = 11, i.e. the code A1A0 = 11 means that any data appears on line D3 will have the highest
priority and pass through the system irrespective of the other inputs. If D2 = “1” and D3 = “0” the code A1A0 = 10 and this means that D2 has the
highest priority in this case.
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InputsOutputs
D3D2D1D0A1A0V
0
0
0
0
1
0
0
0
1
X
0
0
1
X
X
0
1
X
X
X
0
0
0
1
1
0
0
1
0
1
0
1
1
1
1
00011110
00
011111
111111
101111
D1D0
D3D2
00011110
0011
01
111111
101111
D1D0
D3D2
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3210
321
2130
DDDDV
DDA
DDDA
D3
D2
D1
D0
A0
A1
V
4-input Priority Encoder
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Multiplexers
It is a combinational circuit that selects binary information from one of many lines and directs it to a single output line.
The selection of a particular input line is controlled by a set of selection variables.
Normally, there are 2n input lines and “n” selection variables whose bit combinations determine which input is selected.
As in decoders, multiplexers may have an enable input to control the operation of the unit.
When the enable input is in the active state, the outputs are disabled.
The enable input is useful for expanding two or more multiplexers onto a multiplexer with a larger number of inputs.
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S0
S1
D0
D1
D2
D3
Y
Function Table
S0S1Y
0
0
1
1
0
1
0
1
D0
D1
D2
D3
4-to-1 line Multiplexer ( MUX )
[ Data Selector ]
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Implementing a Boolean Function of “n” variables with a Multiplexer that “n-1”
Selection Inputs
The first “n-1” variables of the function are connected to the selection inputs of the multiplexer.
The remaining single variable of the function is used for the data inputs.
If the single variable is “Z”, the data input of the multiplexer will be either ;
01,Z,Z or
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Example 7,6,2,1mZ,Y,XF
XYZF
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
0
1
1
0
0
0
1
0
0
1
1
1
1
0
1
1
1
ZF
ZF
0F
1F
4 x 1 MUX
F
YX
ZZ01
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General Steps
The Boolean function is first listed in a truth table.The first “n-1” variables listed in the table are applied to the
selection inputs of the MUX.For each combination of the selection variables, we evaluate
the output as a function of the last variable.This can be 0, 1, the variable or the complement of the
variable.
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Demultiplexer
It is a digital function that performs the inverse operation of a MUX.
It receives information from a single line and transmits it to one of 2n possible output lines.
The selection of the specific output is controlled by the bit combination of n-selection lines.
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E
S0
S1
D0
D1
D2
D3
1-to-4 Demultiplexer
220
Sequential Circuits
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Logic Circuits
Consists of logic gates whose outputs at any time are determined directly from the values of the present inputs.
No feedback or storage elements are involved.
It involves storage elements (Flip-Flops).
Outputs are a function of inputs and the state of the storage elements, where the state of the storage elements is a function of the previous inputs.
Circuit behavior must be specified by a time sequence of inputs and internal states.
Logic Circuits
Combinational Sequential
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Logic Circuits
Logic Circuits
Combinational Sequential
Combinational Circuit
m
outputs
n
inputs
n2 possible input combination
One possible output for
each binary combination
of input variables
Combinational Circuit
Storage
elements
Present state
Next
state
Inputs Outputs
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A sequential circuit is specified by a time sequence of inputs, outputs and internal states. It contain memory and thus can remember the changes of input signals that occurred in the past.
Inputs for the sequential circuit are functions of external inputs and the present state of the storage elements.
Both external inputs and the present states determine the binary value of the outputs and the condition for changing the state of the storage state.
Outputs = f( external inputs , present states)
Next state = f( external inputs , present states)
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Sequential Circuits
It is a system whose behavior can be defined
from the knowledge of its signals at discrete instants of
time
It is a system whose behavior depends upon the order in which the inputs
change, and the state of the circuit can be affected at
any instant of time
Sequential Circuits
Synchronous Asynchronous
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An asynchronous sequential circuit may be regarded as a combinational circuit with feedback, thus the system may operate in an unpredictable manner and sometimes may even become unstable.
The various problems encountered in asynchronous systems impose many difficulties on the designer, and for this reason they are seldom used.
A synchronous sequential circuit employs signals that affect the storage elements only at discrete instant of time, as synchronization is achieved by a timing device called a “Clock Generator” that produces a periodic train of clock pulses.
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The clock pulses are distributed throughout the system in such a way that storage elements are affected only upon the arrival of each pulse, the outputs of the storage elements change only when clock pulses are present.
The storage elements employed in clocked sequential circuits are called “Flip-Flops”.
A Flip-Flop is a binary storage device capable of storing one bit of information.
When a clock pulse is not active, the feedback loop is broken because the Flip-Flop outputs cannot change even if the outputs of the combinational circuit change in value, thus the transition from one state to the other occurs only at predetermined time intervals dictated by the clock pulses.
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Combinational Circuit
FLIP-Flop
Outputsinputs
Clock pulses
Next
state
Present state
Next state change only
during a clock pulse
transition
Synchronous clocked sequential circuit
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A Flip-Flop circuit has two outputs, one for the normal value and the other for the complemented value of the bit that is stored in it.
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Latches
A Flip-Flop circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit), until directed by an input signal to switch states.
Latches are the basic circuit from which all Flip-Flops are constructed.
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SR-Latch (NOR gates)
SRQAction
1010 Set
state0010
0101Reset
State0001
1100Undefined
reset
set
SR-Latch with NOR gates
Q
Action that must be taken
No change
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SR-Latch (NAND gates)
SRQAction
0110 Set
state1110
1001Reset
State1101
0011Undefined
set
reset
SR-Latch with NAND gates
Q
Action that must be taken
No change
RS
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Notice that, the S input in the SR NOR-Latch must go back to “0” before any other changes can occur.
There are two input conditions that cause the circuit to be in the SET state, the first is the action that must be taken by input S to bring the circuit to the SET state, the second is the removing of the active input from S leaving the circuit in the same state.
When S=R=1 (NOR-gate latch), both outputs go to “0”, this produces an undefined state and it also violates the requirement that output Q and Q be the complement of each other.
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Comparing the SR NAND-Latch and the SR NOR-Latch, we note that the input signals for the NAND required the complement values of those used for the NOR-Latch.
Because the NAND-Latch require a “0” signal to change its state, it is sometimes referred to as an S-R Latch, the bar
above the letters designates the fact that the inputs must be in their complement form to activate the circuit.
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SR-Latch (NAND gates)
CSRNext state of Q
0XXNo change
100No change
101Q=0 : reset state
110Q=1 : set state
111undetermined
set
reset
SR-Latch with NAND gates
and a control input
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235
An additional control input which determines when the state of the latch can be changed is added to the basic SR-Latch to improve its operation
The control input C acts as an enable signal for the other two inputs.
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236
D-Latch
CDNext state of Q
0XNo change
10Q=0: reset state
11Q=1: set state
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One way to eliminate the undesirable condition of the indeterminate state in the SR-Latch is to insure that inputs S & R are never equal to 1 at the same time.
As long as the control input is at “0”, the cross-coupled SR latch has both inputs at the 1 level and the circuit can not change regardless of the value of D.
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JK Flip-Flop
CJKNext state of Q
0XXNo change
100No change
101Q=0 : reset state
110Q=1 : set state
111Complement (toggle)
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T Flip-Flop
CTNext state of Q
0XNo change
10No change
11complement
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Flip-Flops Characteristic Tables & Equations
SR Flip-Flop
SRQ(t+1)Operation
0
0
1
1
0
1
0
1
Q(t)
0
1
N/A
No change
Reset
Set
Indeterminate
JK Flip-Flop
JKQ(t+1)Operation
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)
No change
Reset
Set
Complement
D Flip-Flop
DQ(t+1)Operation
0
1
0
1
Reset
Set
T Flip-Flop
TQ(t+1)Operation
0
1
Q(t)
Q(t)
No change
Complement
QKQJ)1t(Q 0SR,QRS)1t(Q
QTQT)1t(Q D)1t(Q
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Analysis Procedure
Obtain the binary values of each Flip-Flop input equation in terms of the present state and input variables
Use the corresponding Flip-Flop characteristic table to determine the next state.
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The characteristic tables are a shorter version of the truth table, it gives for every set of input values and the state of the Flip-Flop before the rising-end (edge) the corresponding state of the Flip-Flop after the rising edge of the clock signal.
By using K-map we can derive the characteristic equation for each Flip-Flop
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Flip-Flop Excitation Tables
SR Flip-Flop Excitation Table
Q(t)Q(t+1)SR
0
0
1
1
0
1
0
1
0
1
0
X
X
0
1
0
JK Flip-Flop Excitation Table
Q(t)Q(t+1)JK
0
0
1
1
0
1
0
1
0
1
X
X
X
X
1
0
T Flip-Flop Excitation Table
Q(t)Q(t+1)T
0
0
1
1
0
1
0
1
0
1
1
0
D Flip-Flop Excitation Table
Q(t)Q(t+1)D
0
0
1
1
0
1
0
1
0
1
0
1
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The excitation for each Flip-Flop, is used during the analysis of sequential circuits. It is derived from the characteristic table by transposing input and output columns.
It gives the value of the Flip-Flop‘s inputs that are necessary to change the Flip-Flop’s present state to the desired next state after the rising edge of the clock signal.
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In addition to graphical symbols, tables, or equations, Flip-Flops can also be described uniquely by means of State
diagrams or State graphs, in which case each state would be represented by a circle , and a transition between state would
be represented by an arrow.
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State Diagram for various Flip-Flops
Q=0
Q=1
SR = 10
SR = 01
SR =00 or 10SR =00 or 01
SR Flip-Flop
Q=0
Q=1
JK = 10 or 11
JK = 01or 11
JK =00 or 10JK =00 or 01
JK Flip-Flop
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State Diagram for various Flip-Flops
Q=0
Q=1
D = 1
D = 0
D = 1D = 0
D Flip-Flop
Q=0
Q=1
T = 1
T = 1
T = 0T = 0
T Flip-Flop
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The State Diagram
The state diagram can be obtained directly from the state table.The state is represented by a circle and the transition between
state is indicated by a directed lines connecting the circles.The directed lines are labeled with two binary numbers separated by a slash, the input value during present state and
the second is the output during the present state.Same state can represent both the source and destination of a
transition.Each state can be thought of as a time interval between two
rising edges of the clock signal.
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The State Diagram (cont.)
Q=0
Q=1
Input / output
State of a Flip-Flop
During present state
Directed line
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Example
Consider a sequential circuit with two JK Flip-Flops (A & B) and one input “X”, specified by the following input equations:
XAXAXJ
XBBJ
B
A
B
A
K
K
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XAXAXJ
XBBJ
B
A
B
A
K
K
A B
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State TablePresent StateInputNext StateFlip-Flop
Inputs
ABXAB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
0
1
1
0
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
1
0
BJAJ AK BK
JK Flip-Flop Excitation Table
Q(t)Q(t+1)JK
0
0
1
1
0
1
0
1
0
1
X
X
X
X
1
0
JK Flip-Flop Characteristic Table
JKQ(t+1)Operation
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)
No change
Reset
Set
Complement
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Steps
Find , , , from the equations Find the next state from the corresponding J & K inputs using the
characteristic table of the JK Flip-Flop.
BJAJ AK BK
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State Diagram
00 01
01
10 11
0
11
0
0
0
Value of input X
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Master-Slave Flip-Flop
It consists of two Latches and an inverter. When clock pulse input C=“1”, then the output of the inverter is “0”. Thus
the Master is enabled and its output Y is equal to the external input D and the Slave is disabled.
When clock pulse input C=“0”, then the output of the inverter is “1”. Thus the Slave is enabled and its output Q is equal to the Master output Y and the Master is disabled.
Any changes in the external D input changes the master output Y but cannot affect the Slave output Q.
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C
D
Y
Q
MASTER SLAVE
External D
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Master-Slave with a JK Flip-Flop
Replacing the Master D Latch with an SR Latch with control input, the result is a Master-Slave SR Flip-Flop. But the SP Flip-Flop has the undesirable condition of producing an indeterminate next state when S=R=1.
A modified version of the SR Flip-Flop that eliminates the undesirable condition is the JK Flip-Flop, in this case when J=K=1, it causes the output to complement its value
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Master-Slave with a JK Flip-Flop (cont.)
S
MASTER SLAVE
R
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Flip-Flips with Asynchronous Inputs
Each Flip-Flop is usually available with and without asynchronous inputs, that are used to preset and clear the Flip-Flops independently of other Flip-Flop inputs.
These inputs are used to set the Flip-Flops into initial state for their standard operation, as when power is turned on, the state of each Flip-Flop is not predictable, thus we must use asynchronous inputs to set the Flip-Flop properly.
Asynchronous means, inputs do not depend on the clock signal and therefore have precedence over all other operations.
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Flip-Flips with Asynchronous Inputs
CLR & PRS are asynchronous inputs
C
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Active-low CLR & PRS Active-high CLR & PRS
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Edge Triggered Flip-Flop (Latch)
It is divided into three Latches:The SET latchThe Reset LatchThe Output Latch
A low value of asynchronous signals affects the FLIP-Flop:The Latch is preset by the signal PRS = 0The Latch is cleared by the signal CLR = 0
Note that, the preset and clear signals force all the latches into proper states that correspond to Q = 1 & Q = 0 respectively.
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SET Latch
RESET Latch
OUTPUT Latch
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Active-low preset and clear signals are more frequently found in practice.
Note that, the SET latch follows the changes in the CLK signal if D is equal to “1” at the rising edge of the CLK signal, while the RESET latch follows the CLK signal if D=0 at the rising edge of the CLK signal.
Edge Triggered Flip-Flop (Latch) (cont.)
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Registers
The simplest of the storage components.Each register consists of n-Flip-Flops driven by a common
clock signal.SET (Preset) and RESET (Clear) inputs are independent of the
clock signal and have priority over it.The register store any new data automatically on every rising
edge of the clock.
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4-bit registerI3 I2 I1 I0
Q3 Q2 Q1 Q0
CLK
Preset
Clear
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Register with a Selector (Mutliplexer)
To control the input data of a register, a selector (Multiplexer [MUX]) unit is used, where a selector is a device that accepts many inputs and selects only one of them at a time to represent the output [ 2n-inputs, n-control and one output ].
A control signal “LOAD” or “Enable” is used, which allows loading the data into the register [parallel-load register].
The selector, selects either input data or data already stored in the register.
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0 enter previous stored data (Qi , i = 0,1,2,3)
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Shift Register
It shifts its contents one bit in the specified direction when the control signal “SHIFT” is equal to “1”.
It is used to convert a serial data stream into a parallel stream.
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4-bit serial-in/parallel-out
Shift-right register
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A Multi-Functional Register
By using a 4-to-1 Selector, you can combine the SHIFT and LOADING functions into one unit.
It either shift its contents or load new data. It could shift one-bit either to the left or to the right depending on the
selection mode.
Present stateOperationNext State
S1S0Q3Q2Q1Q0
0
0
1
1
0
1
0
1
No change
Load input
Shift Left
Shift Right
Q3
I3
Q2
IL
Q2
I2
Q1
Q3
Q1
I1
Q0
Q2
Q0
I0
IR
Q1
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A Multi-Functional Register (cont.)
L01201301301
1i011i01i01i01i
101R010010010
ISSQSSISSQSS
QSSQSSISSQSSD
QSSISSISSQSSD
3D
2i1
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3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
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Counters A counter is a special type of a register. It incorporates an incremental, which allows it to count upward or downward. The incremental consists of a series of Half-Adders [HA] arranged such that an HA
in bit position “i” will have two inputs connected to the output of the Flip-Flop Q i and the carry Ci from he HA in position “i-1”.
The counter equation is as follows:
As long as E=1, the counter will count-up modulo 4, adding “1” to its content on every rising edge of the clock.
iii
iii
CQC
CQD
1
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PresentNextF.F.
Q2Q1Q0EQ2Q1Q0D2D1D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
Counter>EEnable
Clear Q2 Q1 Q0
Enable = 0 no change
= 1 count
D Flip-Flop Excitation Table
Q(t)Q(t+1)D
0
0
1
1
0
1
0
1
0
1
0
1
Three states 3 Flip-Flops, we will use D F.F. as an example
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10
10011
QQQQD
00011110
011
111
00 QD
00011110
011
111
Q1Q0
Q2
012
012012
012012
01202122
QQQ
QQQQQQ
QQQQQQ
QQQQQQQD
00011110
01
1111
Q1Q0
Q2
Q1Q0
Q2
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Q2 Q1 Q0
C0C1
C2
C3
E
D1 D0D2
carry
3-bit up-counter
Half-Adder
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Up/Down Counter
The previous counter can be extended to represent an up/down counter, if we replace the Half-Adder with a Half-Adder/Subtractor [HAS], which can increment or decrement under the control of a direction signal “ D “, in this case the counter equation will be:
iiiii
iii
CQDCQDC
CQD
1
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D
E
C3
C2
C1
C0
D2D1 D0
Q2 Q1 Q0
CLKCLEAR
Carry
4-bit up/down Binary Counter
Direction signal , D = 0 count up, D = 1 count down
ED
0
1
1
X
0
1
No change
Count-up
Count-down
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Half-Adder/Subtractor[ HAS ]
iQ
iQ
D
D
E = CiCi+1
Di
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3-bit up/down Counter with Parallel Load[ Presetable Counter ]
I0I1I2
D
E
Output carry
Load
CLKClear
Selector Selector Selector
HAS HAS HAS
Q0Q1Q2
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LoadEDOperation
0
0
0
1
0
1
1
X
X
0
1
X
No change
Count-up
Count-down
Load input
4-bit up/down Counter with Parallel Load[ Presetable Counter ] [cont.]
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BCD Counter
It can be constructed by detecting when the counter reaches a count of “9” and loading “0” instead of “10” in the next clock cycle.
The detection is accomplished by an AND gate whose output is equal to “1” when the content of the counter is equal to “1001”.
The output of the AND is connected to the Counter's Load input, which allows the counter to load “0” at the next rising edge of the clock.
In the up direction we must load “0” into the counter when it reaches a count of “9”, while in the down direction we must load “9” when the counter reaches a count of “0”.
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Up/Down Counter
0
0 0 0 0
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Selector
Up/Down Counter
Up/Down BCD Counter
S
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Asynchronous Counter All Flip-Flops are not all clocked by the same clock signal There is no need to use an incremental or decremental, counting is
achieved by toggling each Flip-Flop at half the frequency of the preceding Flip-Flop.
The Flip-Flop will change its state on every 0-to-1 transition of its clock input.
Note, the clock signal “CLK” is used to only clock the Flip-Flop in the least significant position.
The clock-to-output delay of the ith Flip-Flop is equal to “i”. The maximum counting frequency of an n-bit asynchronous counter is:
n
1f
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TTTT
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CLK012345678
Q34
Q2 3
Q12
Q0
t0 t1 t2 t3 t4 t5 t6 t7
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Mixed-mode Counters
To speed up an asynchronous counter, we must make it partly synchronous.
To do this, we divide a large counter into n-bit slices, so that the operation within each slice is asynchronous, while the propagation between slices is synchronous, or vice versa.
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Asynchronous Counter
Asynchronous Counter
Synchronous Counter with 4-bit Asynchronous Slices
8-bit Mixed-mode Counter
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Synchronous Counter
Synchronous Counter
Asynchronous Counter with 4-bit Synchronous Slices
8-bit Mixed-mode Counter
295
Memory & Programmable Logic
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Major Units
For any system, there are three major units:Central processing unit CPUMemory unitInput/Output unit
In digital system, memory is a collection of cells capable of storing binary information (permanent or temporary).
It contains electronic circuits for storing and retrieving information.
It interacts with the CPU and input/output units.
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Memory types
Random Access MemoryRAM
Read Only MemoryROM
• It is a programmable logic devices PLDs, which are integrated circuits with internal logic gates connected through electronic fuses.
• Programming is done by blowing these fuses to obtain the desired logic function.
• Accept new information for storage to be available later for use (write)
• Transfer stored information out of memory (read)
• RAMs may range on size from hundreds to billions of bits.
• It is volatile
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Conventional Symbol
Array Logic Symbol
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Example of a PLD Chip
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Programming Technology
To establish the programmable connections the following technologies are used:EPROM EEPROM FLASH
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EPROM
used to create a wired –AND function. The transistor has two gates, a select gate and a floating gate, charge can be accumulated and trapped on the floating gate by a mechanism called avalanche injection or hot electron injection. These transistors are referred to as FAMOS (Floating gate Avalanche-injection MOS). Note that without a charge on the floating gate the FAMOS acts as a normal n-channel transistor in that when a voltage is applied to the gate, the transistor is turned on. EPROM cells provide a mechanism to hold a programmed state, which is used in PLDs or CPLDs to establish or not establish a connection. To erase the cell remove charge from the floating gate by exposing the device to ultraviolet light. (typical erasure time is about 35 minutes under high-intensity UV light.
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EEPROM
E2PROM, used to create a wired AND-function. It consists of two transistors (select & storage transistors). These transistors are referred to as FLOTOX (Floating gate Tunnel Oxide transistors). It is similar to the FAMOS except that the oxide region over the drain is considerably smaller, less than 10 Ao (Angstroms) compared to 200 Ao for the FAMOS. This allows charges to be accumulated and trapped on the floating gate by a mechanism called Fowler-Nordheim tunneling. E2PROM cells require a select transistor because when the floating gate does not hold a charge, the threshold voltage of the FLOTOX transistor is negative.
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FLASH
like E2PROM, FLASH cells consist of two transistors (select & storage transistors). They create a wired AND function. The storage Transistor is a FAMOS, so programming is accomplished via hot electron injection. However the floating gate is shared by an eraser transistor that take charge off it via tunneling.
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RAM
Random access from any random location. It stores information in groups of bits (called “words”.A word is a group of 1’s & 0’s (represents numbers,
instructions, alphanumeric characters, binary coded information).
Normally, a word is a multiples of 8 bits (1 byte) in length, where 1 byte = 8 bits.
Capacity of memory = total number of bytes.
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Communications between Memory & Environment
Communications between memory and environment is done through:In/Out linesAddress selection linesControl lines
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Memory Unit Block Diagram
Memory Unit
2k words
n bits/word
n data-in lines
n data-out lines
K-address
linesReadWriteK-address = specify particular
word chosen
R/W Control = Direction of transfer
• Computer range from 210=1024 words (requiring address of 10-bits) to
232 (requiring 32 address bits)
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Units
Kilo “K” = 210
Mega “M” = 220
Gega “G” = 230
64 K = 216 (26 x 210 )2 M = 221
4 G = 232
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Memory Address
BinaryDecimalMemory Content
0000000000
1111111111
0
1023
1101100101011100
Content of 1024 x 16 Memory L 1K x 16bit
i.e. 10 address lines & 16-bit wordNote: 64K x 10 16 bits in address , 10-bits word
2k = m , m total number of words, K number of address bits (lines)
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Write & Read
WriteTransfer binary address of desired word to address lines.Transfer data bits that must be stored to data-in linesActivate write-in
ReadTransfer binary address to address lines.Activate read-in
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Memory Chip Control
Select
Out
R/W
IN
Basic Cell
S
R
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Memory SelectRead/WriteOperation
0XNone
10Write
11Read
Basic
Cell
OUTIN
R/W
Select
m words of n-bits/word consists of n x m binary storage cells
R/W = 1 read path from F.F to output
0 In to F.F.
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Data-IN
Data-OUT
RAM
16 x 4Address-
lines
Memory Select
R/W
Memory Chip Symbol
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3-State Buffer
It exhibits three distinct states, two of the states are the logic 1 and logic 0 of conventional logic. The third state is the high-impedance (Hi-Z) state.
The high-impedance state behaves like an open circuit, i.e. looking back into the logic circuit, we would find that the output appears to be disconnected.
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IN OUT
ENABLE ) EN)
ENINOUT
0
1
1
X
0
1
Hi-Z
0
1
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Properties of Memory
Integrated circuit “RAM” may be either Static or Dynamic
RAM
Static RAM (SRAM) Dynamic RAM (DRAM)
• It consists of internal latches that store the binary information.
• The stored information remain valid as long as power is applied to the RAM
• It stores the binary information in the form of electric charges on capacitors, the capacitors are accessed inside the chip by n-channel MOS transistors.
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• The stored charge on the capacitors tends to discharge with time, and the capacitors must be periodically recharged by refreshing the DRAM. This is done by cycling through the words every few milliseconds, reading and rewriting them to restore the decaying charge.
• It offers reduced power consumption and larger storage capacity in a single DRAM chip
RAM
Static RAM (SRAM) Dynamic RAM (DRAM)
• SRAM is easier to use and has shorter read/write cycles.
• No refresh is required
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Memory units that lose stored information when power is turned-off are said to be Volatile.
Both SRAM & DRAM are of this category, since the binary cells needs external power to maitain the stored information.
Magnetic disks, CDs as well as ROM are non-volatile memories, as they retain their stored information after the removal of power.
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Array of RAM Chips
Combine a number of chips in an array to form the required memory size.
Capacity = number of words & number of bits/word increase in words increase in addressUsually input and output ports are combined, to reduce the
number of pins on the memory package.
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4 x 4 memory
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4 x 4 Memory
It consists of 16 memory cells “MCs”. For each memory access, the address decoder decodes the address and
selects one of the rows. If RWS & CS are both equal to “1” the new content will be written into
each cell of the row selected. Note that the output drivers are disabled to allow the new data to be written-in
If RWS = 0 & CS = 1 the data from the row selected will be passed through the tri-state drivers to the IO pins.
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Design Flow Diagram
Design descriptionSynthesisPlacementRoutingTest Benches for design verification
Design flow diagram
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Design Constraints
Time-to-marketCostDesign FeaturesPerformanceManufacturing capabilities
Design constraints
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System Design Requirements
Increasing FunctionalityHigher performanceLower costLower power consumptionSmaller dimensions
· Need to create highly integrated, complex systems with fewer IC devices and less printed-circuit-
board PCB area.
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Technologies available
PCB technologySurface mounting Devices (SMD)Multi-chip Modules MCMSCustom Design Application Specific Integrated Circuit ASIC (SC, GA,
PLD, CPLD, FPGA)
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How to Define your Hardware
Function descriptionAlgorithmsEquationSymbols (schematic capture)Data from graphsNetlistTruth tableWaveforms (timing diagrams)VHDL
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Future Integrated CAD
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Schematic Capture (Small Designs)
It provides a graphical view of the design It uses software tools that support schematic hierarchy Design modularity ( التجزؤ ( قابلية
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But Capturing Large designs is difficult:
Control logic must still be generated using traditional design techniques
Schematic is difficult to maintain Schematic capture environment are proprietary ( خاص ، so a ,( إمتالكى
designer who works in a schematic capture environment for one project may not be able to reuse material when working on a new project that requires the use of a new schematic capture environment
The simulation environment supported by PLD schematic capture tool may not fit with the system design environment, making design verification difficult at best.
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Bottleneck with increasing complexity of designs
Electronic Design Automation (EDA) tools Accelerated time-to-market schedules
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Appropriate Design Methodologies
Increase the efficiency of designers Facilitate capturing, understanding and
maintaining a design Not open to interpretation Open, not proprietary, standard accepted by
industry Allow designs to be ported from one EDA
environment to another, thus modules can be packaged and reused
VHDL&
VerilogLanguages
satisfyThese
requirements
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Appropriate Design Methodologies (cont.)
Support complex designs and hierarchy and gate-level to system-level design
May be used for description, simulation and synthesis of logic circuits
Support different design entries Supports multiple levels of design
description
VHDL&
VerilogLanguages
satisfyThese
requirements
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Modern Methodologies in design and test
Semi-custom & Full-custom Application Specific Integrated Circuit ASIC
High-density Programmable Logic Devices PLDs
Complex High-density Programmable Logic Devices CPLDs
Field Programmable Gate Arrays FPGAs Hardware Description Language VHDL Very High Speed Integrated Circuit VHSIC
Hardware Description Language
500 to more than 100,000 gates, thus Boolean
equations or gate-level
descriptions are no longer
efficient to quickly
complete a design
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VHDL History VHDL ( a product of the VHSIC (Very High Speed
Integrated Circuit) program funded by the Department of Defense (US government) in 1970s & 1980s) is well suited for designing with programmable logic devices (it is one language for design & simulation).
It was endorsed by IEEE in 1986 in its attempt at standardization.
By December 1987 the IEEE 1076.1 standard for VHDL was approved and a VHDL Language Reference Manual (LRM) was published.
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VHDL properties
it provides high-level language constructs that enable designers to describe large circuits and bring products to market rapidly.
It supports the creation of design libraries for reuse in subsequent designs.
It is a standard language (IEEE standard 1076), thus it provides portability of code between synthesis and simulation tools as well as technology-independent design.
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VHDL properties (cont.)
Reduction of a design description to lower-levels (such as netlist), and it serves the needs of designers at any level
It facilitates converting a design from programmable logic to an ASIC implementation.
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VHDL Advantages
StandardGovernment Support Industry SupportPortabilityModeling Capability (Power & Flexibility)ReusabilityTechnology & Foundry independenceDocumentationNew Design methodology
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Standard
VHDL is an IEEE standard (such as graphic X-windows standard, bus communication interface standard, and so on).
It reduces confusion and makes interfaces between tools, companies, and products easier.
Any development to the standard would have better chances of lasting longer and have less chance of becoming obsolete due to incompatibility with others.
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Government Support
VHDL is a result of the VHSIC program, so it is clear that the US government supports the VHDL standard for electronic procurement.
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Industry Support
Companies use VHDL tools not only with regard to defense contractors, but also for their commercial designs.
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Portability
VHDL permits you to simulate the same design description that you synthesized, simulating a several-thousand-gate design description before synthesizing can save a considerable amount of time & effort.
VHDL is standard, design description can be taken from one simulator to another, one synthesis tool to another, and one platform to another, i.e. VHDL design descriptions can be used in multiple projects.
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VHDLCODE
CompilerB
CompilerA
CompilerC
CustomPCB ASIC
One design
Any Synthesis tool
Any vendor/device
VHDL Portability property
VHDL provides portability between compilers & Device independent design
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Modeling Capability(Power & Flexibility)
It has powerful language constructs (code description of complex control logic)
It has multiple levels of design description for controlling design implementation
It supports design libraries & the creation of reusable components
It provides for design hierarchies to create modular designs
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Device-independent Design
You can create a design without having to first choose a device for implementation, with one design description you can target many device architecture.
It permits multiple styles of design description, i.e. it permits several classes of design description.
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Device-independent Design
U1: xor2 port map(a(0),b(0),x(0)));U2: xor2 port map(a(1),b(1),x(10);U3: nor2 port map(x(0),x(1),aeqb);
aeqb (a(0) XOR b(0)) NOR (a(1) XOR b(1));
aeqb `1` when a = b else `0`;If a = b then aeqb `1`;
Else aeqb `0`;End if;
Netlist Boolean equationst
Concurrent statements Sequential statements
2-bit Comparator
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Benchmarking Capabilities
Device-independent design & portability allow you benchmark a design using different architectures and different synthesis tools.
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ASIC Migration
The efficiency the VHDL generates allows your product to hit the market quickly.
When production volumes reach appropriate levels, VHDL facilitate the development of an ASIC, sometimes the exact code used with the PLD can be used with the ASIC.
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Quick time-to-market & Low Cost
VHDL & programmable logic pair facilitate a speady design process, as VHDL permits designs to be described quickly and Programmable logic eliminates NRE expenses and facilitates quick design iterations.
VHDL & programmable logic combine as a powerful vehicle to bring your products to market in record time.
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