20-port, 10gbe switch chip pcs register speciﬁcation€¦ · • axel-x initialization flow...

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MB8AA3020

20-port, 10GbE Switch Chip

PCS Register Specification

MB8AA3020

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Fujitsu Microelectronics America, Inc.

Confidential

Revision: 2.1

Last Updated: June, 2007

Document #: 10GE-RM-21248-6/2007

Copyright © 2006 Fujitsu Laboratories of America, Inc. All rights reserved.

This document contains confidential information and trade secrets of Fujitsu Laboratories of America, Inc. which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission of Fujitsu Laboratories of America, Inc. Use of copyright notice is precautionary and does not imply publication or intent thereof.

All information contained in this document is subject to change without notice. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness.



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Table of Contents

1. Overview ..........................................................................................................................................................................1

1.1 Introduction .............................................................................................................................................................11.2 AXEL-X Initialization Flow .......................................................................................................................................1

2. 10G Port Configuration Flows ............................................................................................................................................3

2.1 Configuration Flows ..................................................................................................................................................32.2 Disable 10G Port Flow...............................................................................................................................................32.3 Enable 10G Port with Fixed Gain Mode Flow ...............................................................................................................32.4 Enable 10G Port with Adaptive Mode Flow...................................................................................................................6

3. Tx Parameters .................................................................................................................................................................10

3.1 Equalizer Control ....................................................................................................................................................103.2 Tx Synchronizer Initialization ...................................................................................................................................12

4. Rx Parameters.................................................................................................................................................................13

4.1 Bypass Rx Equalizer.................................................................................................................................................134.2 Fixed Rx Equalizer Gain...........................................................................................................................................134.3 Adaptive Rx Equalizer Gain ......................................................................................................................................13

5. Register Specifications ......................................................................................................................................................14

5.1 Overview ................................................................................................................................................................145.2 Detailed Register Definitions.....................................................................................................................................17

Appendix A. Parameters for AXEL-X Evaluation Board ...........................................................................................................56

A.1 Disable 10G Port ....................................................................................................................................................56A.2 Enable 10G Port with Fixed Gain for XAUI ...............................................................................................................57A.3 Enable 10G Port with Fixed Gain for XFI..................................................................................................................58A.4 Enable 10G Port with Adaptive Mode for XAUI..........................................................................................................59A.5 Enable 10G Port with Adaptive Mode for XFI ............................................................................................................60

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1. Overview

1.1 Introduction

AXEL-X has twenty 10G ports (Port-0 ~ 19), and each can be configured as 10GBASE-X (XAUI, CX4) mode or 10GBASE-R (XFI) mode individually.

This document describes how to configure AXEL-X 10G ports and provides the following specification and/or information for an actual application of AXEL-X chip:

• AXEL-X initialization flow overview

• 10G port PCS-PHY configuration flows

• How to choose PCS-PHY Tx parameters

• How to choose PCS-PHY Rx parameters

• PCS register specification

1.2 AXEL-X Initialization Flow

After powering on AXEL-X or applying the hardware reset, AXEL-X chip loads the on-chip code from EEPROM and the micro-engine starts executing the on-chip code by itself. The on-chip code configures all twenty 10G PCS-PHY ports as a part of the AXEL-X initialization.

Figure 1 shows the AXEL-X initialization flow.

Figure 1: AXEL-X Initialization Flow

S1

S2

S3

S4 Initialize Switch Core

Disable 10G Port S6 S7

Hardware Reset

Software Reset

S5 Enable 10G Port Enable 10G Port

with Adaptive Mode

Power up AXEL-X

Apply HW Reset

Load On-Chip Code from

Each 10G Port (Port by Port Control)

and GbE Ports

EEPROM and Start ME

with Fixed Gain Mode

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The following is the brief explanation of each step in the AXEL-X initialization flow:

Step 1:

Power up AXEL-X and XI_POWER_GOOD signal of AXEL-X input pin goes high when the AXEL-X power voltage reaches a certain level. Refer to “AXEL-X MB8AA3020 Chip Specification” document for details.

Step 2:

Apply hardware reset. XI_RESET_PLL_N and XI_RESET_N signals of AXEL-X input pins go high at the specific sequence and timing. Refer to “AXEL-X Chip Specification” document for details.

Step 3:

The on-chip code is loaded from EEPROM through I2C bus and the micro engine starts executing the code by itself. Refer to “AXEL-X MB8AA3020 Chip Specification” document for details.

Step 4:

Initialize switch core and GbE ports (port-21 and 23) by the on-chip code. Refer to “AXEL-X MB8AA3020 On-Chip Code Specification” document for details.

Step 5:

Disable 10G port. This is one of three possible configurations of a 10G port. The selection is made port by port. This step is done as a part of the AXEL-X initialization by the on-chip code originally stored in EEPROM. This step is described in details later in this document.

Step 6:

Enable 10G port with Fixed Gain Mode. This is one of three possible configurations of a 10G port. The selection is made port by port. This step is done as a part of the AXEL-X initialization by the on-chip code originally stored in EEPROM. This step is described in details later in this document.

Step 7:

Enable 10G port with Adaptive Mode. This is one of three possible configurations of a 10G port. The selection is made port by port. This step is done as a part of the AXEL-X initialization by the on-chip code originally stored in EEPROM. This step is described in details later in this document.



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2. 10G Port Configuration Flows

2.1 Configuration Flows

The following three sections describe steps 5, 6, and 7 flows in Figure 1.

Each step consists of sub steps which are described in a table. Each table shows the register access sequence. In the register access sequences, the register write values are written in actual values in hex or parameters whose name starts with “$” sign.

In the case of hex values, the write values are fixed. In the case of parameters, the write values differ depending on each application case and are stored in EEPROM as a set of data for the AXEL-X initialization.

2.2 Disable 10G Port Flow

When a port is not used, the port should be disabled by using this flow to reduce the total power dissipation of AXEL-X chip.

Table 1 shows the register access sequence to disable the corresponding port.

2.3 Enable 10G Port with Fixed Gain Mode Flow

When a port is used for XAUI or XFI with fixed gain mode, the port should be enabled by using the flow described in Figure 2.

Figure 2: Enable 10G Port with Fixed Gain Mode

Table 1. Register Access Sequence in Step 5

Reg Type Register Name Reg Addr Write Data Description

Core PORT_DIS 0x0014 (Corresponding port bit = 0) Enable port clock.

PCS PHY_PWR_DOWN_CTL 0xc000 0x80ff Assert PHY all PD signals.

Core PORT_DIS 0x0014 (Corresponding port bit = 1) Disable port clock.

S6.6

S6

S6.1

S6.5 Enable Raw Link FaultStatus Signal to MAC

S6

S6.4 Wait for 50mS

Start

Set PCS-PHY

End

Enable MAC Tx and Rx

with Fixed Gain Mode

S6.2 Wait for 1mS

S6.3 Reset PHY-PCS Gear Boxes

(S2)

(W1)

(W2)

(S6)

(S10)

(S11)

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Table 2 shows the register access sequence in Step-6.1.

Table 2. Register Access Sequence in Step-6.1



PCS PCS_CTL2 0x0007 0x0001 (for XAUI)0x0000 (for XFI)

Select XAUI or XFI mode.

PCS XL_LANE_SWAP_CTL 0xc002 $XL_LANE_SWAP_CTL Set Tx/Rx lane and polarity swap.

PCS PHY_PLL_MODE_CTL 0xc003 $PHY_PLL_MODE_CTL Set PHY PLL mode.

PCS PHY_PWR_DOWN_CTL 0xc000 0x00ff Assert PHY Tx/Rx PD signals. Deassert PHY USR PD signal if it has been asserted.

PCS PCS_CTL1 0x0000 0x8000 Reset PCS.

PCS PHY_TX0_EQ_CFG0 0xc010 $PHY_TX0_EQ_CFG0 Set Tx lane-0 equalizer tap-0.










PCS PHY_TX2_EQ_CFG0 0xc01a $PHY_TX2_EQ_CFG0 Set Tx lane-2 equalizer tap-0.

PCS PHY_TX2_EQ_CFG1 0xc01b $PHY_TX2_EQ_CFG1 Set Tx lane-2 equalizer tap-1.

PCS PHY_TX2_EQ_CFG2 0xc01c $PHY_TX2_EQ_CFG2 Set Tx lane-2 equalizer tap-2.

PCS PHY_TX2_EQ_CFG3 0xc01d $PHY_TX2_EQ_CFG3 Set Tx lane-2 equalizer tap-3.

PCS PHY_TX2_EQ_CFG4 0xc01e $PHY_TX2_EQ_CFG4 Set Tx lane-2 equalizer tap-4.

PCS PHY_TX3_EQ_CFG0 0xc01f $PHY_TX3_EQ_CFG0 Set Tx lane-3 equalizer tap-0.





PCS PHY_TX23_MISC_CTL 0xc052 0x0000 (XAUI)0x4000 (XFI)

Set Tx lane-3 misc control bit-6.

PCS PHY_PWR_DOWN_CTL 0xc000 0x0000 (XAUI)0x00e6 (XFI)

Deassert PHY Tx/Rx PD signals.

PCS PHY_EL0_REG_CTL 0xc030 $PHY_EL0_REG_CTL Set Rx equalizer parameters.

PCS PHY_EL_MODE_CTL 0xc036 0x0002 Enable Rx equalizer controls.



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PCS PHY_TX01_MISC_CTL 0xc051 0x1010 Assert PHY Tx lane-01 synchronizer reset.

PCS PHY_TX01_MISC_CTL 0xc051 0x0000 Deassert PHY Tx lane-01 synchronizer reset.


Assert PHY Tx lane-23 synchronizer reset.


Deassert PHY Tx lane-23 synchronizer reset.

PCS XAUI_GBOX_CTL (XAUI)XFI_GBOX_CTL (XFI)

0xc106 (XAUI)0xc203 (XFI)

0x0022 Assert PCS XAUI Tx and Rx gear box reset. (XAUI)Assert PCS XFI Tx and Rx gear box reset. (XFI)



0x0000 Deassert PCS XAUI Tx and Rx gear box reset. (XAUI)Deassert PCS XFI Tx and Rx gear box reset. (XFI)

PCS PHY_SIG_DET 0xc008 0x800f Enable signal detect signals.



PCS XL_LINK_FAULT_CTL 0xc009 0x0000 Enable raw link fault status signal to MAC.

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2.4 Enable 10G Port with Adaptive Mode Flow

When a port is used for XAUI or XFI with adaptive mode, the port should be enabled by using the flow described in Figure 3.

Figure 3: Enable 10G Port with Adaptive Mode

S7.12

S7

S7.4

CheckPCS InternalLH Link Fault

S7.8

Link Fault

Link Up

S7.11 Enable LH Link FaultStatus Signal to MAC

CheckPCS Internal

LH Link FaultS7.14

S7.15

Link Up

Link Fault

Start

Start Adaptive with Boost

Enable MAC Tx and Rx

Disable MAC Tx and Rx

S7.5 Wait for 25mS

S7.13 Wait for >10mS

S7.1Set PCS-PHY

with Adaptive Mode

S7.6 Clear PCS LH Link Fault

S7.7 Wait for 25mS

S7.9 Disable Boost

S7.10 Wait for 100mS

S7.2 Wait for 1mS

S7.3 Reset PHY-PCS Gear Boxes

(S2)

(W1)

(W2)

(S7)

(S3)

(S4)

(S6)

(C0)

(S8)

(S9)

(S10)

(S11)

(S13)

(C2)

(S14)



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PCS PCS_CTL2 0x0007 0x0001 (for XAUI)0x0000 (for XFI)

Select XAUI or XFI mode.

PCS XL_LANE_SWAP_CTL 0xc002 $XL_LANE_SWAP_CTL Set Tx/Rx lane and polarity swap.

PCS PHY_PLL_MODE_CTL 0xc003 $PHY_PLL_MODE_CTL Set PHY PLL mode.

PCS PHY_PWR_DOWN_CTL 0xc000 0x00ff Assert PHY Tx/Rx PD signals.Deassert PHY USR PD signal if it has been asserted.

PCS PCS_CTRL1 0x0000 0x8000 Reset PCS.











PCS PHY_TX2_EQ_CFG0 0xc01a $PHY_TX2_EQ_CFG0 Set Tx lane-2 equalizer tap-0.

PCS PHY_TX2_EQ_CFG1 0xc01b $PHY_TX2_EQ_CFG1 Set Tx lane-2 equalizer tap-1.

PCS PHY_TX2_EQ_CFG2 0xc01c $PHY_TX2_EQ_CFG2 Set Tx lane-2 equalizer tap-2.

PCS PHY_TX2_EQ_CFG3 0xc01d $PHY_TX2_EQ_CFG3 Set Tx lane-2 equalizer tap-3.

PCS PHY_TX2_EQ_CFG4 0xc01e $PHY_TX2_EQ_CFG4 Set Tx lane-2 equalizer tap-4.

PCS PHY_TX3_EQ_CFG0 0xc01f $PHY_TX3_EQ_CFG0 Set Tx lane-3 equalizer tap-0.






Set Tx lane-3 misc control bit-6.

PCS PHY_PWR_DOWN_CTL 0xc000 0x0000 (XAUI)0x00e6 (XFI)

Deassert PHY Tx/Rx PD signals.

PCS PHY_EL_MODE_CTL 0xc036 0x0001 Set EL programmable mode.

PCS PHY_EL0_REG_CTL 0xc030 0xd140 Write GCTL1 with 0x40.

PCS PHY_EL0_REG_CTL 0xc030 0xc001 Write MISCCTL with 0x01.


PCS PHY_EL0_REG_CTL 0xc030 0xd43f Write GCTL4 with 0x3f.

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PCS PHY_TX01_MISC_CTL 0xc051 0x1010 Assert PHY Tx lane-01 synchronizer reset.

PCS PHY_TX01_MISC_CTL 0xc051 0x0000 Deassert PHY Tx lane-01 synchronizer reset.


Assert PHY Tx lane-23 synchronizer reset.


Deassert PHY Tx lane-23 synchronizer reset.



0x0022 Assert PCS XAUI Tx and Rx gear box reset. (XAUI)Assert PCS XFI Tx and Rx gear box reset. (XFI)



0x0000 Deassert PCS XAUI Tx and Rx gear box reset. (XAUI)Deassert PCS XFI Tx and Rx gear box reset. (XFI)

PCS PHY_SIG_DET 0xc008 0x800f Enable signal detect signals.



PCS PHY_EL_MODE_CTL 0xc036 0x002f Start adaptive control with boost.



PCS XL_LINK_FAULT_STS 0xc00a (Read Operation) Clear latching-high link fault signal.



PCS XL_LINK_FAULT_CTL 0xc009 (Read Operation) Check bit-1 value.0: Link Up1: Link Fault



PCS PHY_EL_MODE_CTL 0xc036 0x0007 Disable boost in adaptive control.



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PCS XL_LINK_FAULT_CTL 0xc009 0x0080 Enable latching-high link fault signal to MAC.



PCS XL_LINK_FAULT_CTL 0xc009 (Read Operation) Check bit-1 value.0: Link Up1: Link Fault

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3. Tx Parameters

3.1 Equalizer Control

The transmitter has a five-tap FIR equalization filter. The output amplitude and pre-emphasis level can be configured by setting the parameters of coefficient magnitude, delay (in UI), and coefficient polarity for each tap. The related registers are:

PHY_TXn_EQ_CFGm: (n = 0~3: lane number, m = 0~4: tap number)TXnNEGm = 0: Polarity is positive, 1: Polarity is negativeTXnCEm[5:0] = 0: Coefficient is minimum (zero) ~ 63: Coefficient is maximumTXnDLYm[2:0] = 0: Delay is 0 UI ~ 7: Delay is 7 UI

Figure 4 shows how the final Tx output is generated by setting each tap parameters.

Figure 4: TX Equalizer Configuration

serialdata

Tap-0

Tap-1

Tap-2

Tap-3

Tap-4

CE=63DLY=0NEG=0

CE=40DLY=0NEG=0

CE=63DLY=1NEG=1

CE=0DLY=0NEG=0

CE=0DLY=0NEG=0

Tx output

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Each tap is identical, and the output amplitude can be added by multiple taps if they are configured as same delay value. Figure 5 shows the relationship between the output amplitude and the coefficient value.

Figure 5: Coefficient Value vs. Amplitude

The differential peak-to-peak amplitude basically follows the equation: [62mV x total CE value], but if the value becomes bigger than 200, the amplitude is slightly less than the calculated value due to the circuit saturation.

Table 13 shows the parameter example of the CX4 mode. This parameters should be set to the lane-0, 1, 2, and 3.

Table 13. Parameter Example (CX4 mode).


PCS PHY_TX0_EQ_CFG0 0xc010 0x03f0 NEG = 0, CE = 63, DLY = 0

PCS PHY_TX0_EQ_CFG1 0Xc011 0x03f0 NEG = 0, CE = 63, DLY = 0

PCS PHY_TX0_EQ_CFG2 0xc012 0x0330 NEG = 0, CE = 51, DLY = 0



PCS PHY_TX1_EQ_CFG0~4 0xc015~0xc019 Same as PHY_TX0_EQ_CFG0~4

PCS PHY_TX2_EQ_CFG0~4 0xc01a~0xc01e Same as PHY_TX0_EQ_CFG0~4

PCS PHY_TX3_EQ_CFG0~4 0xc01f~0xc023 Same as PHY_TX0_EQ_CFG0~4

PCS PHY_TX01_MISC_CTL 0xc051 0x0000 No special Tx control for lane 0 and 1

PCS PHY_TX23_MISC_CTL 0xc052 0x0000 No special Tx control for lane 2 and 3

Tx

Am

plit

ud

e (d

iff-

pp

mV

)

Coefficient value (total)

1600

1400

1200

1000

800

600

400

200

00 50 100 150 200 250 300

y = 62mV x total CE value

Ex. 63(tap0) + 37(tap1)

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Table 14 shows the parameter example of the 10G serial mode. Lane-0 is configured as 10G serial data channel and lane-3 is configured as the clock output for XFP module. This example also includes the Tx special control for lane-3 (clock output) to slow down the rise/fall time.

3.2 Tx Synchronizer Initialization

There is an data synchronizer inside the Tx macro and it has to be initialized whenever the Tx channel comes out of the power-down state. Figure 6 shows how to initialize the Tx macro synchronizer.

Figure 6: TX synchronizer initialization

Table 14. Parameter Example (10G serial mode).



PCS PHY_TX0_EQ_CFG1 0xc011 0x10e1 NEG = 1, CE = 14, DLY = 1




PCS PHY_TX1_EQ_CFG0~4 0xc015~0xc019 0x0000 All off

PCS PHY_TX2_EQ_CFG0~4 0xc01a~0xc01e 0x0000 All off

PCS PHY_TX3_EQ_CFG0 0xc01f 0x03f0 NEG = 0, CE = 63, DLY = 0





PCS PHY_TX01_MISC_CTL 0xc051 0x0000 No special Tx control for lane-0 and 1

PCS PHY_TX23_MISC_CTL 0xc052 0x4000 No special Tx control for lane-2.Slow rise/fall enabled by TX3_CTL[6] = 1

User PD

Tx channel PD

Macro PLL start Tx start

≥0µs

≥10µsTx synchronizer reset.Write the registers in the following order:PHY_TX01_MISC_CTL(0xc051) ≤ 0x0101PHY_TX01_MISC_CTL(0xc051) ≤ 0x0000PHY_TX23_MISC_CTL(0xc052) ≤ 0x0101PHY_TX23_MISC_CTL(0xc052) ≤ 0x0000



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4. Rx Parameters

4.1 Bypass Rx Equalizer

If the channel loss is known to be small in 10GBASE-X mode (e.g. up to 3 meters in AWG28 CX4 cable), Rx equalizer can be bypassed by the sequence shown in Table 15.

4.2 Fixed Rx Equalizer Gain

If the channel loss is rather constant, Rx equalizer gain can be set to a fixed value (0 ~ 126) by the sequence shown in Table 16. The compensation is minimum for gain value 0, and maximum for gain value 126. Recommended gain values are shown in Table 17.

4.3 Adaptive Rx Equalizer Gain

If the channel loss is unknown, Rx equalizer gain can be adapted to the channel loss by the sequence shown in Table 18. This sequence needs to be restarted after receiving the incoming signal, which can be checked by the link fault status.

Table 15. Register Access Sequence to Bypass Rx Equalizer.


PCS PHY_EL0_REG_CTL 0xc030 0x8000 Bypass Rx equalizer.

Table 16. Register Access Sequence to Set Fixed Rx Equalizer Gain.


PCS PHY_EL0_REG_CTL 0xc030 0x807f - (gain value) Set fixed Rx equalizer gain.

Table 17. Recommended gain values.

Loss Recommended gain value CX4 mode XFI mode

Small 32 0 ~ 5 meters, AWG28 CX4 cable N/A

Moderate 94 10 meters, AWG28 CX4 cable 20cm PCB (FR4)

Large 104 15 meters, AWG26 CX4 cable 40m PCB (FR4)

Table 18. Register Access Sequence to Set Adaptive Rx Equalizer Gain.


PCS PHY_EL_MODE_CTL 0xc036 0x0001 Set EL programmable mode.



PCS PHY_EL0_REG_CTL 0xc030 0xc001 Write MISCCTL with 0x01.


PCS PHY_EL0_REG_CTL 0xc030 0xd43f Write GCTL4 with 0x3f.

PCS PHY_EL_MODE_CTL 0xc036 0x002f Restart adaptive cont. w/ boost.

Wait for more than 25ms Do coarse adjustment.

PCS PHY_EL_MODE_CTL 0xc036 0x0007 Set adaptive control w/o boost.

Wait for more than 100ms Do fine adjustment.

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5. Register Specifications

5.1 Overview

Table 19 shows the XL register overview.

Table 19. XL Register Overview

Page Address R/W Abbreviated Name Long Name

17 0000h R/W PCS_CTL1 PCS Control 1 Register

17 0001h RO PCS_STS1 PCS Status 1 Register

17 0002h RO PCS_DEV_ID0 PCS Device Identifier 0 Register

18 0003h RO PCS_DEV_ID1 PCS Device Identifier 1 Register

18 0004h RO PCS_SPEED PCS Speed Ability Register

18 0005h RO PCS_DEV_IN_PKG0 PCS Device In Package 0 Register

18 0006h RO PCS_DEV_IN_PKG1 PCS Device In Package 1 Register

18 0007h RW PCS_CTL2 PCS Control 2 Register

19 0008h RO PCS_STS2 PCS Status 2 Register

19 000eh RO PCS_PKG_ID0 PCS Package Identifier 0 Register

19 000fh RO PCS_PKG_ID1 PCS Package Identifier 1 Register

19 0018h RO PCS_XAUI_STS PCS XAUI Status Register

20 0019h R/W PCS_XAUI_TEST_CTL PCS XAUI Test Control Register

20 0020h RO PCS_XFI_STS1 PCS XFI Status 1 Register

20 0021h RO PCS_XFI_STS2 PCS XFI Status 2 Register

20 0022h R/W PCS_XFI_TEST_SEEDA0 PCS XFI Test Pattern Seed A0 Register




21 0026h R/W PCS_XFI_TEST_SEEDB0 PCS XFI Test Pattern Seed B0 Register




22 002ah R/W PCS_XFI_TEST_CTL PCS XFI Test Pattern Control Register

22 002bh RO PCS_XFI_TEST_ERR PCS XFI Test Pattern Error Counter Register

23 c000h R/W PHY_PWR_DOWN_CTL PHY Power Down Control Register

24 c001h R/W PHY_CURR_BIAS_CTL PHY Current Bias Control Register

25 c002h R/W XL_LANE_SWAP_CTL XL Lane Polarity Swap Control Register

26 c003h R/W PHY_PLL_MODE_CTL PHY PLL Mode Control Register

27 c004h R/W PHY_TX_MODE_CTL PHY Tx Mode Control Register

28 c005h R/W PHY_RX_MODE_CTL PHY Rx Mode Control Register

29 c006h R/W PHY_LOCK_CTL PHY Lock Control Register

29 c007h R/W PHY_CDR_CTL PHY CDR Control Register

30 c008h R/W PHY_SIG_DET PHY Signal Detect Register

30 c009h R/W XL_LINK_FAULT_CTL XL Link Fault Control Register



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30 c00ah RO XL_LINK_FAULT_STS XL Link Fault Status Register

31 c010h R/W PHY_TX0_EQ_CFG0 PHY Tx Lane-0 Equalizer Configuration Tap-0 Register










34 c01ah R/W PHY_TX2_EQ_CFG0 PHY Tx Lane-2 Equalizer Configuration Tap-0 Register

34 c01bh R/W PHY_TX2_EQ_CFG1 PHY Tx Lane-2 Equalizer Configuration Tap-1 Register

35 c01ch R/W PHY_TX2_EQ_CFG2 PHY Tx Lane-2 Equalizer Configuration Tap-2 Register

35 c01dh R/W PHY_TX2_EQ_CFG3 PHY Tx Lane-2 Equalizer Configuration Tap-3 Register

35 c01eh R/W PHY_TX2_EQ_CFG4 PHY Tx Lane-2 Equalizer Configuration Tap-4 Register

36 c01fh R/W PHY_TX3_EQ_CFG0 PHY Tx Lane-3 Equalizer Configuration Tap-0 Register





38 c030h R/W PHY_EL0_REG_CTL PHY EL Lane-0 Register Control Register




39 c034h RO PHY_EL01_REG_READ PHY EL Lane-01 Register Read Register

40 c035h RO PHY_EL23_REG_READ PHY EL Lane-23 Register Read Register

40 c036h R/W PHY_EL_MODE_CTL PHY EL Mode Control Register

41 c037h R/W PHY_EL_TEST_CTL PHY EL Test Control Register

41 c040h R/W PHY_PGEN_CTL PHY Test Pattern Generator Control Register

42 c041h R/W PHY_PCHK_CTL PHY Test Pattern Checker Control Register

42 c042h RO PHY_PCHK01_ERR PHY Test Pattern Checker Lane-01 Error Counter Register

43 c043h RO PHY_PCHK23_ERR PHY Test Pattern Checker Lane-23 Error Counter Register

43 c050h R/W XL_MON_CTL XL Monitor Control Register

43 c051h R/W PHY_TX01_MISC_CTL PHY Tx Lane-01 Misc Control Register

43 c052h R/W PHY_TX23_MISC_CTL PHY Tx Lane-23 Misc Control Register

44 c053h RO PHY_TX01_MON_DATA PHY Tx Lane-01 Monitor Data Register

44 c054h RO PHY_TX23_MON_DATA PHY Tx Lane-23 Monitor Data Register

44 c060h R/W XL_SCRATCH XL Scratch Register


(Continued)


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45 c100h RO XAUI_STS1 XAUI Status 1 Register






48 c106h R/W XAUI_GBOX_CTL XAUI Gear Box Control Register

48 c107h R/W XAUI_PGEN_CTL XAUI Test Pattern Generator Control Register

49 c108h R/W XAUI_PCHK_CTL XAUI Test Pattern Checker Control Register

49 c110h RO XAUI_PCHK0_CYC0 XAUI Test Pattern Checker Lane-0 Cycle Counter 0 Register


50 c112h RO XAUI_PCHK0_ERR0 XAUI Test Pattern Checker Lane-0 Error Counter 0 Register








51 c11ah RO XAUI_PCHK2_ERR0 XAUI Test Pattern Checker Lane-2 Error Counter 0 Register

51 c11bh RO XAUI_PCHK2_ERR1 XAUI Test Pattern Checker Lane-2 Error Counter 1 Register

51 c11ch RO XAUI_PCHK3_CYC0 XAUI Test Pattern Checker Lane-3 Cycle Counter 0 Register

51 c11dh RO XAUI_PCHK3_CYC1 XAUI Test Pattern Checker Lane-3 Cycle Counter 1 Register

51 c11eh RO XAUI_PCHK3_ERR0 XAUI Test Pattern Checker Lane-3 Error Counter 0 Register

52 c11fh RO XAUI_PCHK3_ERR1 XAUI Test Pattern Checker Lane-3 Error Counter 1 Register

52 c200h RO XFI_STS1 XFI Status 1 Register



54 c203h R/W XFI_GBOX_CTL XFI Gear Box Control Register

54 c204h R/W XFI_PGEN_CTL XFI Test Pattern Generator Control Register

55 c205h R/W XFI_PCHK_CTL XFI Test Pattern Checker Control Register

55 c206h RO XFI_PCHK_CYC0 XFI Test Pattern Checker Cycle Counter 0 Register

55 c207h RO XFI_PCHK_CYC1 XFI Test Pattern Checker Cycle Counter 1 Register

55 c208h RO XFI_PCHK_ERR0 XFI Test Pattern Checker Error Counter 0 Register

55 c209h RO XFI_PCHK_ERR1 XFI Test Pattern Checker Error Counter 1 Register


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5.2 Detailed Register DefinitionsThe registers are categorized into the following four groups.

• PCS: PCS registers which conform to IEEE 802.3ae subclause “45.2.3 PCS registers”. The address range is 0000h ~ 7fffh.

• PHY/XL: Vendor specific registers which are specific to PHY macro and XL logic which are used for 10GBASE-X(XAUI) and 10GBASE-R(XFI) in common. The address range is c000h ~ c0ffh.

• XAUI: Vendor specific registers which are specific to 10GBASE-X(XAUI). The address range is c100h ~ c1ffh.

• XFI: Vendor specific registers which are specific to 10GBASE-R(XFI). The address range is c200h ~ c2ffh.

PCS Control 1 Register

Note: This register is not reset by PCS reset (3.0.15).

PCS Status 1 Register

PCS Device Identifier 0 Register

PCS_CTL1 (0000h, 3.0)

Bit(s) Field Name Description R/W Default

15 Reset 0: Normal operation1: Reset(PCS reset pulse duration: 3.2nS x 31cycles = 99.2nS)

R/WSC

0

14 Loopback 0: Disable1: Enable

R/W 0

13 Speed Selection Value 1 means PCS always operates at 10Gb/s and above. RO 1

11 Low Power Mode Value 0 means PCS always operates in normal mode, not low power mode. RO 0

6 Speed Selection Value 1 means PCS always operates at 10Gb/s and above. RO 1

5:2 Speed Selection Value 0000 means PCS always operates at 10Gb/s. RO 0000

PCS_STS1 (0001h, 3.1)


7 Link Fault (before override) 0: Link up1: Link fault(This bit is logical-OR of 3.8.10 and 3.8.11.)

RO -

2 Receive Link Status 0: Receive link fault1: Receive link up(In 10GBASE-X mode, this bit is a latching low version of 3.24.12.)(In 10GBASE-R mode, this bit is a latching low version of 3.32.12.)

ROLL

-

1 Low Power Ability Value 0 means PCS doesn’t support low-power mode. RO 0

PCS_DEV_ID0 (0002h, 3.2)


15:0 PCS Device Identifier 0 Bit 15:0 portion of PCS device identifier bit-31:0The value comes from Core.

RO -

MB8AA3020

18 Fujitsu Microelectronics America, Inc. Confidential

PCS Device Identifier 1 Register

PCS Speed Ability Register

PCS Device In Package 0 Register

PCS Device In Package 1 Register

PCS Control 2 Register


PCS_DEV_ID1 (0003h, 3.3)


15:0 PCS Device Identifier 1 Bit 31:16 portion of PCS device identifier bit-31:0The value comes from Core.

RO -

PCS_SPEED (0004h, 3.4)


0 10G Capable Value 1 means PCS is capable of operating at 10 Gb/s. RO 1

PCS_DEV_IN_PKG0 (0005h, 3.5)


5 DTE XS Present Value 0 means DTE XS is not present. RO 0

4 PHY XS Present Value 0 means PHY XS is not present. RO 0

3 PCS Present Value 1 means PCS is present. RO 1

2 WIS Present Value 0 means WIS is not present. RO 0

1 PMA/PMD Present Value 0 means PMA/PMD are not present. RO 0

0 Clause 22 Registers Present Value 0 means Clause 22 registers are not present. RO 0

PCS_DEV_IN_PKG1 (0006h, 3.6)


15 Vendor Specific Device 2 Present Value 0 means Vendor Specific Device 2 is not present. RO 0

14 Vendor Specific Device 1 Present Value 0 means Vendor Specific Device 1 is not present. RO 0

PCS_CTL2 (0007h, 3.7)


1:0 Type Selection 00: Select 10GBASE-R PCS type (XFI)01: Select 10GBASE-X PCS type (XAUI)10: (Reserved)11: (Reserved)

R/W 01



PCS Status 2 Register

PCS Package Identifier 0 Register

PCS Package Identifier 1 Register

PCS XAUI Status Register

PCS_STS2 (0008h, 3.8)


15:14 Device Present Value 10 means device is responding at this address. RO 10

11 Transmit Fault 0: No fault condition on transmit path1: Fault condition on transmit path

ROLH

-

10 Receive Fault 0: No fault condition on receive path1: Fault condition on receive path

ROLH

-

2 10GBASE-W Capable (WAN) Value 0 means PCS is not able to support 10GBASE-W PCS type (WAN). RO 0

1 10GBASE-X Capable (XAUI) Value 1 means PCS is able to support 10GBASE-X PCS type (XAUI). RO 1

0 10GBASE-R Capable (XFI) Value 1 means PCS is able to support 10GBASE-R PCS type (XF1). RO 1

PCS_PKG_ID0 (000eh, 3.14)


15:0 Package Identifier 0 Bit-15:0 portion of package identifier bit-31:0 R0 0000h

Table 20. PCS_PKG_ID1 (000fh, 3.15)

Bit(S) Field Name Description R/W Default

15:0 Package Identifier 1 Bit-31:16 portion of package identifier bit-31:0 RO 0000h

PCS_XAUI_STS (0018h, 3.24)


12 XAUI Rx Lane Align Status (XAUI Receive Link Status)

0: XAUI Rx is not lane-aligned (link fault).1: XAUI Rx is lane-aligned (link up).

RO -

11 XAUI Tx Test Pattern Generator Ability Value 1 means PCS is able to generate 10GBASE-X test patterns. RO 1

3 XAUI Rx Lane-3 Comma Align Status 0: XAUI Rx Lane-3 is not comma-aligned.1: XAUI Rx Lane-3 is comma-aligned.

RO -


RO -


RO -


RO -

MB8AA3020


PCS XAUI Test Control Register

PCS XFI Status 1 Register

PCS XFI Status 2 Register

PCS XFI Test Pattern Seed A0 Register

PCS_XAUI_TEST_CTL (0019h, 3.25)


2 XAUI Tx Test Pattern Enable 0: Disable1: Enable

R/W 0

1:0 XAUI Tx Test Pattern Select 00: High frequency pattern (D21.5)01: Low frequency pattern (K28.7)10: Mixed frequency pattern (k28.5)11: (Reserved)

R/W 00

PCS_XFI_STS1 (0020h, 3.32)


12 XFI Receive Link Status 0: Link fault1: Link up

RO -

2 XFI PRBS31 Pattern Testing Ability Value 1 means PCS is able to support 10GBASE-R PRBS31 pattern testing. RO 1

1 XFI Rx High BER Status 0: Not high BER1: High BER

RO -

0 XFI Rx Block Lock Status 0: Not block-locked1: Block-locked

RO -

PCS_XFI_STS2 (0021h, 3.33)


15 XFI Rx Block Lock Status 0: Not block-locked1: Block-locked(This bit is a latching low version of 3.32.0.)

ROLL

-

14 XFI Rx High BER Status 0: Not high BER1: High BER(This bit is a latching high version of 3.32.1.)

ROLH

-

13:8 XFI Rx BER Counter 6-bit BER counter value RCNR

-

7:0 XFI Rx Errored Block Counter 8-bit errored block counter value RCNR

-

PCS_XFI_TEST_SEEDA0 (0022h, 3.34)


15:0 XFI Test Pattern Seed A0 Bit-15:0 portion of XFI test pattern seed A bit-57:0 R/W 0000h






PCS XFI Test Pattern Seed B0 Register






15:0 XFI Test Pattern Seed A1 Bit-31:16 Portion of XFI test pattern seed A bit-57:0 R/W 0000h







PCS_XFI_TEST_SEEDB0 (0026h, 3.38)


15:0 XFI Test Pattern Seed B0 Bit-15:0 portion of XFI test pattern seed B bit-57:0 R/W 0000h


Bit(3) Field Name Description R/W Default








MB8AA3020


PCS XFI Test Pattern Control Register

PCS XFI Test Pattern Error Counter Register

PCS_XFI_TEST_CTL (002ah, 3.42)


5 XFI Rx PRBS31 Pattern Checker Enable 0: Disable1: Enable

R/W 0

4 XFI Tx PRBS31 PatternGenerator Enable

0: Disable1: Enable

R/W 0

3 XFI Tx Test Pattern Generator Enable 0: Disable1: Enable(When this bit is one, bit-4 is ignored, i.e., this bit is stronger than bit-4.)

R/W 0

2 XFI Rx Test Pattern Checker Enable 0: Disable1: Enable

R/W 0

1 XFI Tx Test Pattern Select 0: Pseudo random pattern1: Square wave pattern (repeating 8 zeros and 8 ones)

R/W 0

0 XFI Tx Data Pattern Select 0: LF data pattern1: Zero data pattern

RW 0

PCS_XFI_TEST_ERR (002bh, 3.43)

Bit(s) Description Description R/W Default

15:0 XFI Rx Test Pattern Error Counter 16-bit test pattern error counter value RCNR

-



PHY Power Down Control Register


PHY_PWR_DOWN_CTL (c000h)

Bit(s) Field Names Description R/W Default

15 User Power Down(I_USRPD)

0: Normal operation1: Power down

R/W 1

7 Rx Lane-3 Power Down(I_RX3CHPD)


R/W 1



R/W 1



R/W 1



R/W 1

3 Tx Lane-3 Power Down(I_TX3CHPD)


R/W 1



R/W 1



R/W 1



R/W 1

MB8AA3020


PHY Current Bias Control Register


PHY_CURR_BIAS_CTL (c001h)


9:8 PLL Current Bias Control Code(I_EVPLLIBCTL[1:0])

00: 25%01: 50%10: 75%11: 100%

R/W 10

6:4 Internal Current Bias Control Code(I_EVIBCTL[2:0])

000: -6%001: -2%010: -10%011: -6%100: 0%101: +4%110: -4%111: 0%

R/W 100

2:0 Phase Interpolator Current Bias Control Code(I_EVRXPIIBCTL[2:0])

000: -75%001: -50%010: -25%011: 0%100: +25%101: +50%110: +75%111: +100%

R/W 011



XL Lane Polarity Swap Control Register


XL_LANE_SWAP_CTL (c002h)

Bit(s) Field Names Description R/W Default

13:12 Rx Lane Swap 00: Lane 0 → Lane-0, Lane-1 → Lane-1, Lane-2 → Lane-2, Lane-3 → Lane-301: Lane 0 → Lane-1, Lane-1 → Lane-0, Lane-2 → Lane-3, Lane-3 → Lane-210: Lane 0 → Lane-2, Lane-1 → Lane-3, Lane-2 → Lane-0, Lane-3 → Lane-111: Lane 0 → Lane-3, Lane-1 → Lane-2, Lane-2 → Lane-1, Lane-3 → Lane-0

R/W 00

11 Rx Lane-3 Polarity Swap 0: Normal1: Polarity swap

R/W 0


R/W 0


R/W 0


R/W 0

5:4 Tx Lane Swap 00: Lane 0 → Lane-0, Lane-1 → Lane-1, Lane-2 → Lane-2, Lane-3 → Lane-301: Lane 0 → Lane-1, Lane-1 → Lane-0, Lane-2 → Lane-3, Lane-3 → Lane-210: Lane 0 → Lane-2, Lane-1 → Lane-3, Lane-2 → Lane-0, Lane-3 → Lane-111: Lane 0 → Lane-3, Lane-1 → Lane-2, Lane-2 → Lane-1, Lane-3 → Lane-0

R/W 00

3 Tx Lane-3 Polarity Swap 0: Normal1: Polarity swap

R/W 0


R/W 0


R/W 0


R/W 0

MB8AA3020


PHY PLL Mode Control Register


PHY_PLL_MODE_CTL (c003h)


15 PLL Mode Setting Override Enable 0: Disable1: Enable

R/W 0

11:9 Divider Ratio for PLL (B) (I_PLLDIVSET[2:0])

000: (Reserved)001: (Reserved010: (Reserved)011: 1/40100: 1/33101: (Reserved)110: (Reserved)111: (Reserved)

R/W 011

8:6 Divider Ratio for Gear Box Clock (D)(I_PLLDIVCLKASET[2:0])

000: (Reserved)001: 1/16010: 1/32011: (Reserved)100: (Reserved)101: (Reserved)110: (Reserved)111: (Reserved)

R/W 010

5:4 Divider Ratio for Skewless Clock Tree (C)(I_PLLSPDSET[1:0])

00: 1/101: (Reserved)10: 1/411: (Reserved)

R/W 10

3:0 PLL Output Clock Frequency Fine Tune(I_PLLCTL[3:0])

0000: Maximum:1111: Minimum

R/W 0101



PHY Tx Mode Control Register


PHY_TX_MODE_CTL (c004h)


15 Tx Mode Setting Override Enable 0: Disable1: Enable

R/W 0

5:4 Tx Parallel Data Input Width(I_TXPWID[1:0])

00: 32-bit01: 16-bit10: (Reserved)11: (Reserved)

R/W 01

3 Tx Lane-3 Clock Divider Slave Mode(I_TX3MXDIVSLV)

0: Master1: Slave

R/W 1


0: Master1: Slave

R/W 1


0: Master1: Slave

R/W 1


0: Master1: Slave

R/W 0

MB8AA3020


PHY Rx Mode Control Register


PHY_RX_MODE_CTL (c005h)


15 Rx Mode Setting Override Enable 0: Disable1: Enable

R/W 0

13:12 Rx Parallel Data Output Width(I_RXPWID[1:0])

00: 32-bit01: 16-bit10: (Reserved)t11: (Reserved)

R/W 01

10:8 Rx PCLKA Divider Ratio(I_RXPCLKASET[2:0])

000: 1/33001: (Reserved)010: (Reserved)011: 1/5100: (Reserved101: (Reserved)110: (Reserved)111: (Reserved)

R/W 011

7:6 Rx Lane-3 Equalizer SpeedControl(I_RX3EQSPD[1:0])

00: XFI01: (Reserved)10: XAUI11: (Reserved)

R/W 10

5:4 Rx Lane-2 Equalizer Speed Control(I_RX2EQSPD[1:0])


R/W 10



R/W 10



R/W 10



PHY Lock Control Register


PHY CDR Control Register


PHY_LOCK_CTL (c006h)


7 Tx Lane-3 Synchronizer Lock Detection Status(O_TX3LOCK)

0: Not locked1: Locked

RO -



RO -



RO -



RO -

3 Tx Lane-3 Synchronizer Lock Hold(I_TX3LOCKED)

0: Automatically re-start process of obtaining lock when lock is lost.1: Hold lock once locked.

R/W 0



R/W 0



R/W 0



R/W 0

PHY_CDR_CTL (c007h)

Bit(s) Field Size Description R/W Default

14 Phase Interpolator Phase Code Control(I_EVRXPICODESEL)

0: Normal operation1: Code fixed

R/W 0

13:8 Phase Interpolator Phase Code(I_EVRXPICODE[5:0])

000000: Minimum:111111: Maximum

R/W 000000

7 Digital Filter Clock Select(I_RXDFCLKSEL)

0: Internal1: External (I_RXnDFCLK)

R/W 0

6 Digital Filter Output Code Control(I_RXDFMSEL)

0: Decrement1: Increment

R/W 0

5:3 Digital Filter G2 Code(I_EVRXDFG2SET[2:0])


R/W 011

2:0 Digital Filter G1 Code(I_EVRXDFG1SET[2:0])


R/W 010

MB8AA3020


PHY Signal Detect Register

XL Link Fault Control Register

XL Link Fault Status Register

PHY_SIG_DET (c008h)


15 Rx Signal Detect Override 0: Use PHY macro values1: Override with this register values

R/W 1

3 Rx Lane-3 Signal Detect(O_RX3SIGDETECT)

0: No signal detected1: Signal detected

R/W (bit15=1)RO (bit15=0)

0




0




0




0

XL_LINK_FAULT_CTL (c009h)


15 Link Fault Override 0: Use PCS signal after latching low control by bit-71: Override with bit-8

R/W 1

8 Link Fault Override Value 0: Link up1: Link fault

R/W 1

7 Link Fault Latching High Enable 0: Use original link fault signal from PCS (same value as bit-0)1: Use latching high link fault signal (same value as bit-1)

R/W 0

2 Link Fault Value to MAC(after override)

0: Link up1: Link fault

RO -

1 Link Fault Value(latching high output)

0: Link up1: Link fault(This bit is an output of XL_LINK_FAULT_STS bit-0. Note that reading this register won’t reset the value of XL_LINK_FAULT_STS bit-0.)

RO -

0 Link Fault Value(original output from PCS)

0: Link up1: Link fault

RO -

XL_LINK_FAULT_STS (c00ah)


0 Link Fault 0: Link up1: Link fault(This bit is a latching high version of XL_LINK_FAULT_CTL bit-0)

ROLH

-



PHY Tx Lane-0 Equalizer Configuration Tap-0 Register



PHY_TX0_EQ_CFG0 (c010h)


12 Tx-0 Equalizer Tap-0 Polarity(I_TX0NEG0)

0: Positive1: Negative

R/W 0

9:4 Tx-0 Equalizer Tap-0 Coefficient(I_TX0CE0[5:0])


R/W 111100 (60)

3:0 Tx-0 Equalizer Tap-0 Delay(I_TX0DLY0[3:0])

0000: 0 UI:0111: 7 UI1000: (reserved):1111: (reserved)

R/W 0





R/W 0



R/W 111100(60)



R/W 0





R/W 0



R/W 111100(60)



R/W 0

MB8AA3020









R/W 1



R/W 101000(40)



R/W 1





R/W 1



R/W 101000(40)



R/W 1





R/W 0



R/W 111100(60)



R/W 0










R/W 0



R/W 111100(60)



R/W 0





R/W 0



R/W 111100(60)



R/W 0





R/W 1



R/W 101000(40)



R/W 1

MB8AA3020









R/W 1



R/W 101000(40)



R/W 1

PHY_TX2_EQ_CFG0 (c01ah)




R/W 0



R/W 111100(60)



R/W 0

PHY_TX2_EQ_CFG1 (c01bh)




R/W 0



R/W 111100(60)



R/W 0






PHY_TX2_EQ_CFG2 (c01ch)




R/W 0



R/W 111100(60)



R/W 0

PHY_TX2_EQ_CFG3 (c01dh)




R/W 1



R/W 101000(40)



R/W 1

PHY_TX2_EQ_CFG4 (c01eh)




R/W 1



R/W 101000(40)



R/W 1

MB8AA3020





PHY_TX3_EQ_CFG0 (c01fh)




R/W 0



R/W 111100(60)



R/W 0





R/W 0



R/W 111100(60)



R/W 0





R/W 0



R/W 111100(60)



R/W 0









R/W 1



R/W 101000(40)



R/W 1





R/W 1



R/W 101000(40)



R/W 1

MB8AA3020


PHY EL Lane-0 Register Control Register


PHY_EL0_REG_CTL (c030h)


15 EL Register Read/Write All Lane Mode 0: Each lane1: All lanes(200nS pulse is generated with no delay when this bit is set.)

R/WSC

0

14 EL Lane-0 Register Write Enable(I_EVRX0ACWEN)

Reserved (Valid only in programmable mode) R/WSC

0

13:8 EL Lane-0 Register Address(I_EVRX0ACADDR[5:0])

Read/write address R/W 0

7:0 EL Lane-0 Preset Equalizer Control Code(I_EVRX0ACWDATA[7:0])

Preset equalizer control code:0: Bypass equalizer (valid only in 3G mode)1: Fixed equalizer gain 126 (strongest)2: Fixed equalizer gain 125:126: Fixed equalizer gain 1127: Fixed equalizer gain 0 (weakest)248: Adaptive equalizer gainOthers: Reserved

R/W 0





0





R/W 0





PHY EL Lane-01 Register Read Register





0





R/W 0





0





R/W 0

PHY_EL01_REG_READ (c034h)


15:8 EL Lane-1 Register Read Data(O_EVRX1ACRDATA[7:0])

Lane-1 read data RO -



MB8AA3020


PHY EL Lane-23 Register Read Register

PHY EL Mode Control Register

PHY_EL23_REG_READ (c035h)






PHY_EL_MODE_CTL (c036h)


5 EL Adaptation Restart(I_RX0ACRSTX)(I_RX1ACRSTX)(I_RX2ACRSTX)(I_RX3ACRSTX)

0: No action 1: Restart adaptation control by setting 1st order path gain to the initial value(100nS pulse is generated with no delay when this bit is set.)

R/W SC 0

4 EL Reserved Bit(I_RX0ACMODE[4])(I_RX1ACMODE[4])(I_RX2ACMODE[4])(I_RX3ACMODE[4])

Reserved bit R/W 0

3 EL Loop Constant Boost Enable(I_RX0ACMODE[3])(I_RX1ACMODE[3])(I_RX2ACMODE[3])(I_RX3ACMODE[3])

0: Disable1: Enable

R/W 0

2 EL Gain Control Enable(I_RX0ACMODE[2])(I_RX1ACMODE[2])(I_RX2ACMODE[2])(I_RX3ACMODE[2])

0: Disable1: Enable

R/W 0

1 EL Offset Cancel Enable(I_RX0ACMODE[1])(I_RX1ACMODE[1])(I_RX2ACMODE[1])(I_RX3ACMODE[1])

0: Disable1: Enable

R/W 0

0 EL Operation Mode(I_RX0ACMODE[0])(I_RX1ACMODE[0])(I_RX2ACMODE[0])(I_RX3ACMODE[0])

0: Preset Mode1: Reserved (Programmable mode)

R/W 0



PHY EL Test Control Register

PHY Test Pattern Generator Control Register

PHY_EL_TEST_CTL (c037h)


5 EL Event Counter Clear(I_EVRX0ACCNTCLRX) (I_EVRX1ACCNTCLRX) (I_EVRX2ACCNTCLRX) (I_EVRX3ACCNTCLRX)

0: No action 1: Clear(100nS pulse is generated with no delay when this bit is set.)

R/WSC

0

4 EL Event Counter Enable 2(I_EVRX0ACCNTEN)(I_EVRX1ACCNTEN)(I_EVRX2ACCNTEN)(I_EVRX3ACCNTEN)

0: Disable1: Enable(393.216uS pulse is generated with 100nS delay when this bit is set and ORed with bit-3 value, then sent to PHY.)

R/WSC

0

3 EL Event Counter Enable 1(I_EVRX0ACCNTEN)(I_EVRX1ACCNTEN)(I_EVRX2ACCNTEN)(I_EVRX3ACCNTEN)

0: Disable1: Enable(This bit is ORed with the pulse generated by bit-4, then sent to PHY.)

R/W 0

2 EL Test Clock Select(I_EVRX0ACTCLKSEL)(I_EVRX1ACTCLKSEL)(I_EVRX2ACTCLKSEL)(I_EVRX3ACTCLKSEL)

0: Internal1: External (RXACTCLK)

R/W 0

1:0 EL Test Mode(I_EVRX0ACTMODE[1:0])(I_EVRX1ACTMODE[1:0])(I_EVRX2ACTMODE[1:0])(I_EVRX3ACTMODE[1:0])

00: Normal mode01: Pattern test mode10: Increment test mode11: Decrement test mode

R/W 00

PHY_PGEN_CTL (c040h)


4 PRBS Pattern Generator Reset(I_TXPNGRSTX)

0: Normal operation1: Reset

R/W 0

3 PRBS Pattern Generator Enable(I_TXPNGEN)

0: Disable1: Enable

R/W 0

2:0 Test Pattern Generator Select(I_TXPNGCTL[2:0])

000: PRBS23 pattern001: 0101 pattern010: 20 ones and 20 zeros pattern011: Static-1 pattern100: PRBS7 pattern101: PRBS31 pattern110: 0011 pattern111: 0000011111 pattern

R/W 000

MB8AA3020


PHY Test Pattern Checker Control Register

PHY Test Pattern Checker Lane-01 Error Counter Register

PHY_PCHK_CTL (c041h)


5 Test Pattern Checker Error Hold Reset(I_RXPNERRRSTX)


R/W 0

4 Test Pattern Checker Reset(I_RXPNCRSTX)


R/W 0

3 Test Pattern Checker Enable(I_RXPNCEN)

0: Disable1: Enable

R/W 0

2:0 Test Pattern Checker Select(I_RXPNCCTL[2:0])

000: PRBS23 pattern001: (Reserved)010: (Reserved)011: (Reserved)100: PRBS7 pattern101: PRBS31 pattern110: (Reserved)111: (Reserved)

R/W 000

PHY_PCHK01_ERR (c042h)


15 Test Pattern Checker Lane-1 Error Hold(O_RX1PNEONCE)

0: No errors have been detected.1: Errors have been detected at least once after reset.

RO -

14 Test Pattern Checker Lane-1 Error(O_RX1PNERR)

0: No error1: Error detected

RO -

13:8 Test Pattern Checker Lane-1 Error Counter(O_RX1PNEBITCNT[5:0])

6-bit error counter value RO -



RO -



RO -





PHY Test Pattern Checker Lane-23 Error Counter Register

XL Monitor Control Register

PHY Tx Lane-01 Misc Control Register

PHY Tx Lane-23 Misc Control Register

PHY_PCHK23_ERR (c043h)




RO -



RO -





RO -



RO -



XL_MON_CTL (c050h)


4:0 XL Monitor Signal Select 00000: Select one of XL monitor signal sets:11111: Select one of XL monitor signal sets

R/W 00000

PHY_TX01_MISC_CTL (c051h)


15:8 PHY Tx Lane-1 Control(I_EVTX1CTL[7:0])

PHY Tx lane-1 misc control signals R/W 00h



PHY_TX23_MISC_CTL (c052h)






MB8AA3020


PHY Tx Lane-01 Monitor Data Register

PHY Tx Lane-23 Monitor Data Register

XL Scratch Register

PHY_TX01_MON_DATA (c053h)


15:8 PHY Tx Lane-1 Monitor Data(O_EVTX1MON[7:0])

Monitor data signals RO -



PHY_TX23_MON_DATA (c054h)






XL_SCRATCH (c060h)


15:0 Scratch Scratch register for write/read test R/W 0000h



XAUI Status 1 RegisterXAUI_STS1 (c100h)


15 Link Fault (before override) 0: Link up1: Link fault (Latching high version of bit-14)

ROLH

-

14 Link Fault (before override) 0: Link up1: Link fault

RO -

11 XAUI Tx Gear Box Not Locked 0: Locked1: Not locked(Latching high version of bit-10)

ROLH

-

10 XAUI Tx Gear Box Not Locked 0: Locked1: Not locked

RO -

9 XAUI Rx Lane Not Aligned 0: Aligned1: Not aligned(Latching high version of bit-8)

ROLH

-

8 XAUI Rx Lane Not Aligned 0: Aligned1: Not aligned

RO -

7 XAUI Rx Lane-3 Comma Not Aligned 0: Aligned1: Not aligned(Latching high version of bit-6)

ROLH

-

6 XAUI Rx Lane-3 Comma Not Aligned 0: Aligned1: Not aligned

RO -


ROLH

-


RO -


ROLH

-


RO -


ROLH

-


RO -

MB8AA3020


XAUI Status 2 RegisterXAUI_STS2 (c101h)


15 XAUI Rx Lane-3 Gear Box Not Locked 0: Locked1: Not locked(Latching high version of bit-14)

ROLH

-

14 XAUI Rx Lane-3 Gear Box Not Locked 0: Locked1: Not locked

RO -


ROLH

-


RO -


ROLH

-


RO -


ROLH

-


RO -

7 PHY Tx Lane-3 Gear Box Not Locked 0: Locked1: Not locked(Latching high version of bit-6)

ROLH

-

6 PHY Tx Lane-3 Gear Box Not Locked 0: Locked1: Not locked

RO -


ROLH

-


RO -


ROLH

-


RO -


ROLH

-


RO -



XAUI Status 3 Register


XAUI_STS3 (c102h)


6:4 XAUI Rx Lane Align FSM 0x0: LOSS_OF_ALIGNMENT state0x1: ALIGN_DETECT_1 state0x2: ALIGN_DETECT_2 state0x3: ALIGN_DETECT_3 state0x4: ALIGN_ACQUIRED_1 state0x5: ALIGN_ACQUIRED_2 state0x6: ALIGN_ACQUIRED_3 state0x7: ALIGN_ACQUIRED_4 state

RO -

2:0 XAUI Tx Transmit FSM 0x0: SEND_DATA state0x1: SEND_A state0x2: SEND_K state0x3: SEND_Q state0x4: SEND_RANDOM_A state0x5: SEND_RANDOM_K state0x6: SEND_RANDOM_R state0x7: SEND_RANDOM_Q state

RO -

XAUI_STS4 (c103h)


15:12 XAUI Rx Lane-3 Comma Align FSM (Same bit assignments as bit-3:0) RO -



3:0 XAUI Rx Lane-0 Comma Align FSM 0x0: LOSS_OF_SYNC state0x1: COMMA_DETECT_1 state0x2: COMMA_DETECT_2 state0x3: COMMA_DETECT_3 state0x4: SYNC_ACQUIRED_1 state0x5: SYNC_ACQUIRED_2 state0x6: SYNC_ACQUIRED_3 state0x7: SYNC_ACQUIRED_4 state0x8: SYNC_ACQUIRED_2A state0x9: SYNC_ACQUIRED_3A state0xa: SYNC_ACQUIRED_4A state0xb~f: (Not used)

RO -

MB8AA3020




XAUI Gear Box Control Register

XAUI Test Pattern Generator Control Register

XAUI_STS5 (c104h)


15:12 XAUI Rx Lane-3 Comma Align Shift Amount 0x0~9: Shift amount0xa~f: (Not used)

RO -


RO -


RO -


RO -

XAUI_STS6 (c105h)


14:12 XAUI Rx Lane-3 Lane Align Shift Amount 0x0~4: Shift amount0x5~7: (Not used)

RO -


RO -


RO -


RO -

XAUI_GBOX_CTL (c106h)


5 XAUI Rx Gear Box Lock Reset 0: No action1: Reset lock and re-start process of obtaining lock.

R/W 0

4 XAUI Rx Gear Box Lock Hold 0: Automatically re-start process of obtaining lock when lock is lost.1: Hold lock once locked. Re-start process of obtaining lock only when bit-5 is set.

R/W 0

1 XAUI Tx Gear Box Lock Reset 0: No action1: Reset lock and re-start process of obtaining lock.

R/W 0

0 XAUI Tx Gear Box Lock Hold 0: Automatically re-start process of obtaining lock when lock is lost.1: Hold lock once locked. Re-start process of obtaining lock only when bit-1 is set.

R/W 0

XAUI_PGEN_CTL (c107h)


15:12 XAUI Tx Lane-3 Test Pattern Generator Select (Same bit assignments as bit-3:0) R/W 0000




XAUI Test Pattern Checker Control Register

XAUI Test Pattern Checker Lane-0 Cycle Counter 0 Register


3:0 XAUI Tx Lane-0 Test Pattern Generator Select 0x0: Disable0x1: RRBS7 pattern0x2: PRBS23 pattern0x3: PRBS31 pattern0x4: Static-0 pattern0x5: Static-1 pattern0x6: Square wave pattern (n=2, 1.5625GHz)0x7: Square wave pattern (n=4, 781.25MHz)0x8: Square wave pattern (n=8, 390.625MHz)0x9: Square wave pattern (n=16, 195.3125MHz)0xa: Square wave pattern (n=32, 97.65625MHz)0xb: Square wave pattern (n=64, 48.828125MHz)0xc: Square wave pattern (n=128, 24.4140625MHz)0xd: Square wave pattern (n=256, 12.20703125MHz)0xe: Low frequency pattern (K28.7)0xf: Mixed frequency pattern (K28.5)

R/W 0000

XAUI_PCHK_CTL (c108h)


3 XAUI Rx Test Pattern Checker Counter Clear 0: No Action1: Clear(In order to make this bit work, bit-2 needs to be 1.)

R/W SC 0

2 XAUI Rx Test Pattern Checker Enable 0: Disable1: Enable(When changing this bit from 1 to 0, the value of bit-1:0 should not be changed to avoid incorrect error counts caused by signal glitch.)

R/W 0

1:0 XAUI Rx Test Pattern Checker Select 0x0: (Reserved)0x1: PRBS70x2: PRBS230x3: PRBS31

R/W 00

XAUI_PCHK0_CYC0 (c110h)


15:0 XAUI Rx Test Pattern Checker Lane-0 Cycle Counter 0 Bit-15:0 portion of cycle counter bit-31:0 RO NR -

XAUI_PGEN_CTL (c107h)


MB8AA3020



XAUI Test Pattern Checker Lane-0 Error Counter 0 Register








15:0 XAUI Rx Test Pattern Checker Lane-0 Cycle Counter 1 Bit-31:16 portion of cycle counter bit-31:0 RONR

-

XAUI_PCHK0_ERR0 (c112h)


15:0 XAUI Rx Test Pattern Checker Lane-0 Error Counter 0 Bit-15:0 portion of error counter bit-31:0 R/O NR -

XAUI_PCHK0_ERR1 (c113h)


15:0 XAUI Rx Test Pattern Checker Lane-0 Error Counter 1 Bit-31:16 portion of error counter bit-31:0 R/O NR -



15:0 XAUI Rx Test Pattern Checker Lane-1 Cycle Counter 0 Bit-15:0 portion of cycle counter bit-31:0 RO NR -


Bit(s) Field Name Descrip

20-port, 10gbe switch chip pcs register speciﬁcation€¦ · • axel-x initialization flow...

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