20060308 ic design flow - access ic lab (prof. an...

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Digital IC Design FlowDigital IC Design Flow

Lecturer: Chihhao ChaoAdvisor: Prof. An-Yeu Wu

Date: 2006.3.8


pp. 2

OutlineOutlinevIntroductionvIC Design FlowvVerilog HistoryvHDL concept


pp. 3

MooreMoore’’s Law: Driving Technology Advancess Law: Driving Technology Advances

v Logic capacity doubles per IC at regular intervals (1965).v Logic capacity doubles per IC every 18 months (1975).


pp. 4

Process Technology EvolutionProcess Technology Evolution


pp. 5

Chips SizesChips Sizes

Source: IBM and Dataquest


pp. 6

Shrinking Product CyclesShrinking Product Cycles

v Shrinking product cyclesv Shrinking development turnaround timesv Need for productivity increase (remember the “design gap”)

PCS: Personal Communication Services


pp. 7

Design Productivity CrisisDesign Productivity Crisis

v Human factors may limit design more than technology.v Keys to solve the productivity crisis:

v Design techniques: hierarchical design, SoC design (IP reuse, platform-based design), etc.

v CAD: algorithms & methodology


pp. 8

Increasing Processing PowerIncreasing Processing Powerv Very high performance circuits in today’s

technologies.v Gate delays: ~27ps for a 2-input Nand in 0.13um processv Operating frequencies: up to 500MHz for SoC/Asic, over

1GHz for custom designs

v The increase in speed/performance of circuits allowed blocks to be reused without having to be redesigned and tuned for each application

v Enhanced Design Tools and Techniquesv Although not enough to close the “design gap”, tools are

essential for the design of today’s high-performance chips


pp. 9

IPIP--Based Based SoCsSoCsv An Evolutionary Pathv Early daysØ IP/Cores not really designed for reuse (no standard

deliverables)ØMultiple Interfaces, difficult to integrate

v IPs evolved: parameterization, deliverables, verification, synthesizable

v On-Chip bus standards began to appear (e.g, IBM, ARM)

v Reusable IP + Common on-chip bus architecturesv 1998: max number of cores > 30 cores

core content between 50% and 95%


pp. 10

IP / CoresIP / Coresv Soft IP/Corev Delivered as RTL verilog or VHDL source code with

synthesis script (i.e: clock generation logic)v Customers are responsible for synthesis, timing closure, and

all front-end processingv Firm IP/Corev Delivered as a netlist to be included in customer’s netlist

(with don't touch attribute)v Possibly with placement information

v Hard IP/Corev Due to their complexity, they are provided as a blackbox

(GL1/GDSII). Ex. Processors, analog cores, PLLsv Usually very tight timing constraints. Internal views not be

alterable or visible to the customer


pp. 11

Changes in the Nature of IC DesignChanges in the Nature of IC Design

(IEEE Spectrum Nov,1996)


pp. 12

Chasing the Design GapChasing the Design Gap


pp. 13

Evolution of Silicon DesignEvolution of Silicon Design

Source: “Surviving the SoC revolution – A Guide to Platform-based Design,”Henry Chang et al, Kluwer Academic Publishers, 1999


pp. 14

Methodology Methodology –– Analysis and Verification Analysis and Verification


pp. 15

IC Design and ImplementationIC Design and ImplementationIdea

Design


pp. 16

Design FlowDesign Flow

Design Specification

Design Partition

Design Entry-VerilogBehavioral Modeling

Simulation/FunctionalVerification

Design Integration &Verification

Pre-SynthesisSign-Off

Synthesize and MapGate-Level Netlist

Post-Synthesis Design Validation

Post-SynthesisTiming Verification

Test Generation &Fault Simulation

Cell Placement, ScanChain & Clock Tree

Insertion, Cell Routing

Verify Physical &Electrical Design Rules

Extract Parasitics

Post-LayoutTiming Verification

Production-ReadyMasks

Production-ReadyMasks

Front End

Design Sign-Off

Back End


pp. 17

System SpecificationSystem Specification

From CIC


pp. 18

Algorithm MappingAlgorithm Mapping

RTL Level

System Level

From CIC


pp. 19

Gate and Circuit Level DesignGate and Circuit Level Design

From CIC


pp. 20

Physical DesignPhysical Design

From CIC


pp. 21

Behavioral ModelBehavioral Model

Transistor Level

Gate Level

Register Transfer Level

Architecture

Algorithm

Systemconcept

Increasingbehavioralabstraction

Increasingdetailed

realization &complexity


pp. 22

Design DomainDesign Domain

Behaviorallevel of

abstraction

Design Model Domain

Abstract PhysicalStructural

System

Algorithm

RTL

Gate

Switch

ArchitectureDesign

StructuralDesign

LogicDesign

LayoutDesign

Verification

Verification

Verification

ArchitectureSynthesis

RTL levelSynthesis

Logic levelSynthesis


pp. 23

Introduction to HDLIntroduction to HDLvHDL – Hardware Description Language

vWhy use an HDL ?vHardware is becoming very difficult to design

directlyvHDL is easier and cheaper to explore different

design optionsvReduce time and cost


pp. 24

VerilogVerilog HDLHDLvBrief history of Verilog HDLv1985: Verilog language and related simulator

Verilog-XL were developed by Gateway Automationv1989: Cadence Design System purchased

Gateway Automationv1990: Cadence released Verilog HDL to public

domainv1990: Open Verilog International (OVI) formedv1995: IEEE standard 1364 adopted


pp. 25

VerilogVerilog HDLHDLvFeaturevHDL has high-level programming language

constructs and constructs to describe the connectivity of your circuit.vAbility to mix different levels of abstraction freelyvOne language for all aspects of design, test, and

verificationvFunctionality as well as timingvConcurrency performvSupport timing simulation


pp. 26

Compared to VHDLCompared to VHDLv Verilog and VHDL are comparable languagesv VHDL has a slightly wider scopev System-level modelingv Exposes even more discrete-event machinery

v VHDL is better-behavedv Fewer sources of non-determinism

(e.g., no shared variables ???)v VHDL is harder to simulate quicklyv VHDL has fewer built-in facilities for hardware

modelingv VHDL is a much more verbose languagevMost examples don’t fit on slides


pp. 27

The Verilog LanguageThe Verilog Languagev Originally a modeling language

for a very efficient event-driven digital logic simulatorv Later pushed into use as a specification language

for logic synthesisv Now, one of the two most commonly-used languages

in digital hardware design (VHDL is the other)v Combines structural and behavioral modeling styles


pp. 28

Different Levels of AbstractionDifferent Levels of Abstractionv Architectural / Algorithmicv A model that implements a design algorithm in high-level

language constructsv Register Transfer Logic (RTL)v A model that describes the flow of data between registers

and how a design process these data.v Gatev A model that describe the logic gates and the

interconnections between them.v Switchv A model that describes the transistors and the

interconnections between them.


pp. 29

VerilogVerilog HDL Behavior LanguageHDL Behavior Languagev Structural and procedural like the C programming

languagev Used to describe algorithm level and RTL level

Verilog modelsv Key featuresv Procedural constructs for conditional, if-else, case, and

looping operations.v Arithmetic, logical, bit-wise, and reduction operations for

expressions.v Timing control.


pp. 30

VerilogVerilog HDL Structural LanguageHDL Structural LanguagevUsed to describe gate-level and switch-level

circuits.vKey featuresvA complete set set of combinational primitivesvSupport primitive gate delay specificationvSupport primitive gate output strength

specification


pp. 31

Language ConventionsLanguage Conventionsv Case-sensitivityvVerilog is case-sensitive.vSome simulators are case-insensitivevAdvice: - Don’t use case-sensitive feature!vKeywords are lower case

v Different names must be used for different items within the same scope

v Identifier alphabet:vUpper and lower case alphabeticals: a~z A~ZvDecimal digits: 0~9vUnderscore: _


pp. 32

Language Conventions (contLanguage Conventions (cont’’d)d)vMaximum of 1024 characters in identifierv First character not a digitv Statement terminated by ;v Free format within statement except for within quotesv Comments:vAll characters after // in a line are treated as a

commentvMulti-line comments begin with /* and end with */

v Compiler directives begin with // synopsys XXXv Built-in system tasks or functions begin with $v Strings enclosed in double quotes and must be on a

single line “Strings”


pp. 33

Design EncapsulationDesign Encapsulationv Encapsulate structural and functional details in a module

v Encapsulation makes the model available for instantiation in other modules

module my_design (ports_list);

... // Declarations of ports go here

... // Structural and functional details go here

endmodule


pp. 34

Port DeclarationPort DeclarationvThree port typesvInput portØ input a;

vOutput portØoutput b;

vBi-direction portØ inout c;

net

net

netnet

input output

inoutreg or net reg or net

module

Port list

Port Declaration

module full_add (S, CO, A, B, CI) ;

output S, CO ;input A, B, CI ;

--- function description ---

endmodule


pp. 35

Two Main Data TypesTwo Main Data Typesv Nets represent connections between thingsv Do not hold their valuev Take their value from a driver such as a gate or

other modulev Cannot be assigned in an initial or always block

v Regs represent data storagev Behave exactly like memory in a computerv Hold their value until explicitly assigned

in an initial or always blockv Never connected to somethingv Can be used to model latches, flip-flops, etc.,

but do not correspond exactlyv Shared variables with all their attendant problems


pp. 36

Primitive CellsPrimitive Cellsv Primitives are simple modulesv Verilog build-in primitive gatev not, buf:Ø Variable outputs, single input (last port)

v and, or, buf, xor, nand, nor, xnor:Ø Single outputs (first port), variable inputs

module full_add (S, CO, A, B, CI) ;

--- port Declaration ---

wire net1, net2, net3;xor U0(S,A,B,CI);and U1(net1, A, B);and U2(net2, B, CI);and U3(net3, CI, A);or U4(CO, net1, net2, net3);

endmodule


pp. 37

How Are Simulators Used?How Are Simulators Used?v Testbench generates stimulus and checks responsev Coupled to model of the systemv Pair is run simultaneously

Testbench System Model

Stimulus

ResponseResult checker


pp. 38

Example: Example: TestbenchTestbenchmodule t_full_add();wire sum, c_out;reg a, b, cin; // Storage containers for stimulus waveformsfull_add M1 (sum, c_out, a, b, cin); //UUTinitial begin // Time Out#200 $finish; // Stopwatchendinitial begin // Stimulus patterns#10 a = 0; b = 0; cin = 0; // Statements execute in sequence#10 a = 0; b = 1; cin = 0; #10 a = 1; b = 0; cin = 0; #10 a = 1; b = 1; cin = 0; #10 a = 0; b = 0; cin = 1; #10 a = 0; b = 1; cin = 1; #10 a = 1; b = 0; cin = 1; #10 a = 1; b = 1; cin = 1;endendmodule


pp. 39

VerilogVerilog SimulatorSimulator


pp. 40

EventEvent--Driven SimulationDriven Simulationv A change in the value of a signal (variable) during simulation is

referred to as an event v Spice-like analog simulation is impractical for VLSI circuits v Event-driven simulators update logic values only when signals

change


pp. 41

StylesStylesvStructural - instantiation of primitives and

modulesvRTL/Dataflow - continuous assignmentsvBehavioral - procedural assignments


pp. 42

Structural ModelingStructural ModelingvWhen Verilog was first developed (1984)

most logic simulators operated on netlistsvNetlist: list of gates and how they’re

connectedvA natural representation of a digital logic

circuitvNot the most convenient way to express test

benches


pp. 43

Behavioral ModelingBehavioral ModelingvA much easier way to write testbenchesvAlso good for more abstract models of circuitsvEasier to writevSimulates faster

vMore flexiblevProvides sequencing

vVerilog succeeded in part because it allowed both the model and the testbench to be described together


pp. 44

Style Example Style Example -- StructuralStructuralmodule full_add (S, CO, A, B, CI) ;


wire N1, N2, N3;

half_add HA1 (N1, N2, A, B),HA2 (S, N3, N1, CI);

or P1 (CO, N3, N2);

endmodule

module half_add (S, C, X, Y);

output S, C ;input X, Y ;

xor (S, X, Y) ;and (C, X, Y) ;

endmodule


pp. 45

Style Example Style Example –– Dataflow/RTLDataflow/RTLmodule fa_rtl (S, CO, A, B, CI) ;


assign S = A ^ B ^ CI; //continuous assignmentassign CO = A & B | A & CI | B & CI; //continuous assignment

endmodule


pp. 46

Style Example Style Example –– BehavioralBehavioralmodule fa_bhv (S, CO, A, B, CI) ;


reg S, CO; // required to “hold” values between events.

always@(A or B or CI) //; begin

S <= A ^ B ^ CI; // procedural assignmentCO <= A & B | A & CI | B & CI; // procedural assignment

end endmodule


pp. 47

How Verilog Is UsedHow Verilog Is Usedv Virtually every ASIC is designed using either Verilog

or VHDL (a similar language)v Behavioral modeling with some structural elementsv “Synthesis subset”v Can be translated using Synopsys’ Design Compiler or

others into a netlist

v Design written in Verilogv Simulated to death to check functionalityv Synthesized (netlist generated)v Static timing analysis to check timing

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