2010 ieee/acm international conference on computer-aided … · 2011-01-28 ·...
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2010 IEEE/ACM International
Conference on Computer-AidedDesign
(ICCAD 2010)
San Jose, California, USA7-11 November 2010
AlCCC IEEE Catalog Number:CFP10CAD-PRT
IflCCC ISBN: 978-1-4244-8193-4
TABLE OF CONTENTS
Session 1-A Fast and Accurate System Estimation, Evaluation, and OptimizationModerators: Hao Yu — Nanyang Technological Univ.
Sung Kyu Lim - Georgia Institute of Technology
1-A.l Fidelity Metrics for Estimation Models 1
Maris Jayaid, Aleksander Ignjatovic, Sri Parameswaran
1-A.2 Fast Performance Evaluation of Fixed-Point Systems with Un-Smooth Operators 9
Karthick Parashar, Daniel Menard, Romuald Rocher, Olivier Sentieys,David Novo, Francky Catthoor
1-A.3 Variation-Aware Layout-Driven Scheduling for Performance Yield Optimization 17
Gregoiy Lucas, Deming Chen
Session 1-B Manufacturing-Aware DesignModerator: Azadeh Davoodi - Univ. of Wisconsin
1-B.l Analysis and Optimization of SRAM Robustness for Double Patterning Lithography 25
Vivek Joshi, KanakAgarwal, DavidBlaauw, Dennis Sylvester
1-B.2 WISDOM: W ire Spreading Enhanced Decomposition of Masks in
Double Patterning Lithography 32
Kun Yuan, David Pan
1-B.3 Maximum-Information Storage System: Concept, Implementation and Application 39
Xin Li
1-B.4 Multi-Wafer Virtual Probe: Minimum-Cost Variation Characterization byExploring Wafer-to-Wafer Correlation 47
Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob Rutenbar
Session 1-C Analog and Mixed Signal Verification and OptimizationModerator: L. Miguel Silveira - Cadence Research Labs, INESC-ID/IST - TU Lisbon
1-C.l On Behavioral Model Equivalence Checking for Large Analog/Mixed Signal Systems 55
Amandeep Singh, Peng Li
1-C.2 An Algorithm for Exploiting Modeling Error Statistics to
Enable Robust Analog Optimization 62
Ashish Kumar Singh, Mario Lok, Kareem Ragab, Constantine Caramanis, Michael Orshansky
1-C.3 A Simple Implementation of Determinant Decision Diagram 70
Guoyong Shi
Tutorial 1 Designing for Uncertainty: Addressing Process Variations and
Aging Issues in Digital SystemsModerator: Diana Marculescu - Carnegie Mellon Univ.
1-T.l Aging Analysis at Gate and Macro Cell Level 77
UlfSchlichtmann, Dominik Lorenz, Martin Barke
1-T.2 Resilient Microprocessor Design for Improving Performance and Energy Efficiency 85
Keith Bowman, James Tscham
1-T," Process Variation Aware Performance Modeling and Dynamic Power
Management for Multicore Systems 89
Siddharth Garg, Diana Marculescu, Sebastian Herbert
Session 2-A Design-Aware ManufacturingModerator: Minsik Cho - IBM Corp.
2-A.I Design-Aware Mask Inspection 93
AbdeAli Kagalwalla, Pimeet Gupta, Chris Progler, Steve McDonald
2-A.2 SMATO: Simultaneous Mask and Target Optimization lor
Improving Lithographic Process Window 100
Shayak Banerjee, Kanak Agarwal, Michael Orshansky
2-A.3 Template-Mask Design Methodology for Double Patterning Technology 107
Chin-Hsiung Hsu, Yao-Wen Chang, SaniNassif
2-A.4 Fast and Lossless Graph Division Method for Layout Decomposition Using SPQR-Tree 112
Wai-Shing Luk, Huiping Huang
2-A.5 Design Dependent Process Monitoring for Back-End Manufacturing Cost Reduction 116
Tuck-Boon Chan, Aashish Pant, Lerong Cheng, Puneet Gupta
Session 2-B Advances in Embedded Systems and FPGA SynthesisModerator: Swamy Muddu - AdvancedMicro Devices, Inc.
2-B.l SETS: Stochastic Execution Time Scheduling for Multicore Systems byJoint State Space and Monte Carlo 123
Nabeel Iqbal, Jorg Henkel
2-B.2 Combining Optimistic and Pessimistic DVS Scheduling: An Adaptive Scheme and Analysis 131
Simon Perathoner, Jian-Jia Chen, Kai Lampka, Nikolay Stoimenov, Lothar Thiele
2-B.3 Unified Theory of Real-Time Task Scheduling and Dynamic Voltage/FrequencyScaling on MPSoCs \ .'. 139
Hessam Kooti, Eli Bozorgzadeh
2-B.4 In-Place Decomposition for Robustness in FPGA 143
Ju-Yueh Lee, Zhe Feng, Lei He
Session 2-C Enhancing Test for Delays and Opens under Power-Sensitive Conditions
Moderator: Suriyaprakash Natarajan - Intel Corp.
2-C.I MVP: Capture-Power Reduction with Minimum-Violations Partitioning for Delay Testing 149
Zhen Chen, Krishnendu Chakrabarty, Dong Xiang
2-C.2 Testing Methods for Detecting Stuck-Open Power Switches in
Coarse-Grain MTCMOS Designs 155
Szn-Pang Mu, Willy Wang, Hao-Yu Yang, Mango Chao, Shi-Hao Chen,
Chih-Mou Tseng, Tsung-Ying Tsai
2-C.3 A Scalable Quantitative Measure of IR-Drop Effects for Scan Pattern Generation 162
Meng-Fan Wu, Kim-Han Tsai, Wit-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Aitgusli Kifli
2-C.4 Trace Selection for Improving Timing and Logic Visibility for Post-Silicon Validation 168
HamidShojaei, Azadeh Davoodi
Tutorial 2 Reliability Analysis and Optimization at System Level:
A Straddle between Complexity and AccuracyModerator: Jiirgen Teich — Univ. ofErlangen-Nuremberg
2-T. l System-Level Impact of Chip-Level Failure Mechanisms and Screens 173
Anne Gattiker
2-1.2 Cross-Layer Error Resilience for Robust Systems 177
Larkhoon Leem, Hyungmin Cho, Hsiao-Heng Lee, Young Moon Kim, Yanjing Li, Subhasish Mitra
2-T.3 Reliability, Thermal, and Power Modeling and Optimization 181
Robert Dick
2-T.4 Symbolic System Level Reliability Analysis 185
Michael Glass, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jiirgen Teich
Session 3-A Advanced Scheduling for Memory SystemsModerators: Denting Chen - Univ. ofIllinois at Urbana-Champaign
Sung Kyu Lint — Georgia Institute of Technology
3-A.l Hierarchical Memory Scheduling for Multimedia MPSoCs 190
Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang
3-A.2 Credit Borrow and Repay: Sharing DRAM with Minimum Latency and
Bandwidth Guarantees 197
Zefu Dai, Mark Jarvin, Jianwen Zhu
3-A.3 Scheduling of Synchronous Data Flow Specifications on
Scratchpad Memory based Embedded Processors 205
Weijia Che, Karam S. Chatha
Session 3-B Making Critical Decision on Power in Physical SynthesisModerators: Lars Hagen - Cadence Design Systems, Inc.
Gi-Joon Nam - IBM Corp.
3-B.l The Fast Optimal Voltage Partitioning Algorithm for Peak Power Density Minimization 213
Jia Wang, Shiyan Hu
3-B.2 Post-Placement Power Optimization with Multi-Bit Flip-Flops 218
Yao-Tsung Chang, Chih-Cheng Hsu, Mark Po-Hung Lin, Yu-Wen Tsai, Sheng-Fong Chen
3-B.3 On Power and Fault-Tolerant Optimization in FPGA Physical Synthesis 224
Manu Jose, Yu Hu, Rupak Majumdar
Session 3-C Advances in Yield and Quality AnalysisModerator: Haluk Konuk - Broadcom Corp.
3-C.l Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing Across Dies 230
Li Jiang, Rong Ye, QiangXu
3-C.2 Mathematical Yield Estimation for Two-Dimensional-Redundaney Memory Arrays 235
Mango Chao, Ching-Yv Chin, Chen-Wei Lin
3-C.3 Analog Test Metrics Estimates with PPM Accuracy 241
Haralampos-G. Stratigopoulos, Salvador Mir
Tutorial 3 Analog Challenges in Nanometer CMOS and Digitalization of Analog FunctionalityModerator: Stephan Henzler - Infineon Technologies A G
3-T.l Design Automation Towards Reliable Analog Integrated Circuits 248
Georges Gielen, Elie Maricau, PieterDe Wit
3-T.2 Energy-Efficient 60GHz Wireless Transceiver Design n/a
EladAlon
3-T.3 Digitalization of Mixed-Signal in Nanometer Technologies 252
Stephan Henzler
Session 4-A Design Optimization for Power-Efficient Synchronous and Asynchronous SystemsModerator: Sung Kyu Lim - Georgia Institute of Technology
4-A.l Efficient Trace-Driven Metaheuristics for Optimization ofNetworks-on-Chip Configurations 256
Andrew B. Kahng, BillLin, Kambiz Samadi, Rohit Sunkam Ramanujam
4-A.2 A Self-Evolving Design Methodology for Power Efficient Multi-Core Systems 264
Jin Sun, Rui Zheng, Jyothi Velamala, Yit Cao, Roman Lysecky, Karthik Shankar, Janet Roveda
4-A.3 An Energy and Power-Aware Approach to High-Levcl Synthesis of Asynchronous Systems 269
John Hansen, Montek Singh
4-A.4 Clustering-Based Simultaneous Task and Voltage Scheduling for NOC Systems 277
Yifang Liu, Yu Yang, Jiang Hu
Session 4-B Improving Simulation Performance
Moderators: Ting Mei - Sandia National Labs
L. MiguelSilveira - Cadence Research Labs, INESC-ID/IST - TVLisbon
4-B.l Generalized Nonlinear Timing/Phase Macromodeling:Theory, Numerical Methods and Applications 284
Chenjie Gu, Jaijeet Roychowdhury
4-B.2 Phase Equations for Quasi-Periodic Oscillators 292
Alper Demir, Chenjie Gu, Jaijeet Roychowdhury
4-B.3 On-thc-Fly Runtime Adaptation for Efficient Execution of Parallel
Multi-Algorithm Circuit Simulation 298
Xiaoji Ye, Peng Li
Session 4-C Advances in Global RoutingModerators: Mustafa Ozdal - Intel Corp.
Patrick Groeneveld - Magma Design Automation, Inc.
4-C.l An Auction based Pre-Processing Technique to Determine Detour in Global Routing 305
YueXu, Chris Chit
4-C.2 Simultaneous Antenna Avoidance and via Optimization in
Layer Assignment of Multi-Layer Global Routing 312
Tsung-Hsien Lee, Ting-Chi Wang
4-C.3 GLADE: A Modern Global Router Considering Layer Directives 319
Yen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang
Tutorial 4 System Level Design - An Industrial PerspectiveModerator: Guido Stehr - Infineon Technologies AG
4-T.l Transaction Level Modeling in Practice: Motivation and Introduction 324
Guido Stehr, JosefEckmueller
4-T.2 Standards for System Level Design 332
Laurent Maillet-Contoz
4-T.3 Design Space Exploration and Performance Evaluation at Electronic
System Level for NoC-Based MPSoC 336
Soeren Sonntag, Francisco Gilahert
4-T.4 ESL Solutions for Low Power Design 340
Sylvian Kaiser, llija Materic, Rabih Saade
4-T.5 HW/SW Co-Design of Parallel Systems 344
Enno Wein
4-T.6 Application Specific Processor Design 349
Achim Nohl, Frank Schirrmeisler, Drew Taussig
Session 5-A System-Level Static and Dynamic Low Power DesignModerators: Sri Parameswaran - Univ. ofNew South Wales
Karam Chatha - Arizona State Univ.
5-A.l Selective Instruction Set Muting for Energy-Aware Adaptive Processors 353
Muhammad Shafique, Lars Bauer, Jotg Henkel
5-A.2 Optimal Algorithm for Profile-Based Power Gating: A Compiler Technique for
Reducing Leakage on Execution Units in Microprocessors 361
Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim
5-A.3 Memory Access Aware On-Line Voltage Control for Performance and Energy Optimization 365
Xi Chen, Chi Xu, Robert Dick
Session 5-B Leveraging Logics, Wire and 3D for Physical SynthesisModerators: Shiyan Hu - Michigan Technological Univ.
Gi-Joon Nam - IBM Corp.
5-B.l SPIRE: A Retiming-Based Physical-Synthesis Transformation System 373
David Papa, Smita Krishnaswamy, Igor Markov
5-B.2 Rcdundant-Wircs-Aware ECO Timing and Mask-Cost Optimization 381
Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang
5-B.3 Through Silicon via Management during 3D Physical Design: When to Add and How Many? 387
Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Kyu Lim
Tutorial 5 Beyond-Die Designs: Solutions and ChallengesModerator: Yao-Wen Chang - National Taiwan Univ.
5-T.l Beyond Die Design: Board Driven I/O Planning and Optimization 395John Park
5-T.2 Recent Research Development in PCB Layout 398
Tan Yan, Martin D.F. Wong
5-T.3 Recent Research Development in Flip-Chip Routing 404
Hsu-Chieh Lee, Yao-Wen Chang, Po-Wei Lee
5-T.4 Modeling and Design for Beyond-the-Die Power Integrity 411
Yiyu Shi, Lei He
Session 6-A Advances in Biological and Post-CMOS SystemsModerators: Radii Zlatanovici - Cadence Design Systems, Inc.
Nishant Patil - Stanford Univ.
6-A.l A Synthesis Flow for Digital Signal Processing with Biomolecular Reactions 417
Hua Jiang, Aleksandra Kharam, Marc Riedel, Keshab Parhi
6-A.2 A Network-Flow based Pin-Count Aware Routing Algorithm for
Broadcast Electrode-Addressing EWOD Chips 425
Tsung-Wei Huang, Shih-Yuan Ych, Tsung-YiHo
6-A.3 Variation Tolerant Sensing Scheme of Spin-Transfer Torque Memory for Yield Improvement 432
Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang
Session 6-B Pushing Clock Distribution Performance
Moderators: Chris Chu - Iowa State Univ.
Dwight Hill - Synopsys, Inc.
6-B.l Novel Binary Linear Programming for High Performance Clock Mesh Synthesis 438
Minsik Cho, David Z. Pan, Ruchir Puri
6-B.2 Low-Power Clock Trees for CPUs 444
Dong-Jin Lee, Myung-Chul Kim, Igor Markov
6-B.3 High Variation-Tolerant Obstacle-Avoiding Clock Mesh Synthesis with
Symmetrical Driving Trees 452
Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang
6-B.4 Local Clock Skew Minimization Using Blockage-Aware Mixed Tree-Mesh Clock Network 458
LinfuXiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian,
Evangeline F.Y. Young
Session 6-C 3D-ICs and Detection of Faults and Hardware TrojansModerators: Jinfeng Liu - Synopsys, Inc.
Zhenyu Qi - Broadcom Corp.
6-C.l 3D-ICE: Fast Compact Transient Thermal Modeling for 3D ICs with
Inter-Tier Liquid Cooling 463
Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, Thomas Brunschwiler, DavidAtienza
6-C.2 Cost-Effective Integration of Three-Dimensional (3D) ICs Emphasizing Testing Cost Analysis 471
Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty
6-C.3 Evaluation of Using Induclive/Capacitrve-Coupling Vertical Interconnects in
3D Nerwork-on-Chip 477
Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie
6-C.4 Scalable Segmentation-Based Malicious Circuitry Detection and Diagnosis 483
Sheng Wei, Miodrag Potkonjak
6-C.5 Application-Aware Diagnosis of Runtime Hardware Faults 487
Andrea Pellegrini, Valeria Bertacco
Tutorial 6 Organic Electronics
Moderator: Hagen Klauk - Max Planck Institutefor Solid State Research
6-T.l Materials and Manufacturing of Organic Transistors 493
Hagen Klauk, Ute Zschieschang
6-T.2 Design and Manufacturing of Organic RFID Circuits 496
Jan Genoe, Kris Myny, Soeren Steudel, Paul Heremans
6-T.3 Design of Large Area Electronics with Organic Transistors 500
Makoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai
6-T.4 Design of Analog Circuits Using Organic Field-Effect Transistors 504
Boris Murmann, Wei Xiong
Session 7-A Advances in Timing AnalysisModerators: Yaping Zhan - Advanced Micro Devices, Inc.
Igor Keller - Cadence Design Systems, Inc.
7-A.I Active Learning Framework lor Post-Silicon Variation Extraction and Test Cost Reduction 508
Cheng Zhuo, Kanak Agarwal DavidBlaauw, Dennis Sylvester
7-A.2 Analysis of Circuit Dynamic Behavior with Timed Ternary Decision Diagram 516
Lu Wan, Deming Chen
7-A.3 Fast Statistical Timing Analysis of Latch-Controlled Circuits for Arbitrary Clock Periods 524
Bing Li, Ning Chen, UlfSchlichtmcmn
7-A.4 On Timing-Independent False Path Identification 532
Feng Yuan, QiangXu
Session 7-B Parallel Methods for Power Grid and Interconnect AnalysisModerators: Eric Keiter - Sandia National Labs
Heidi Thornquist - Sandia National Labs
7-B.l 3POr - Parallel Projection based Parameterized Order Reduction for
Multi-Dimensional Linear Models 536
Jorge Fernandez Villena, L. Miguel Siheira
7-B.2 A Hierarchical Matrix Inversion Algorithm for Vectorless Power Grid Verification 543
Xuanxing Xiong, Jia Wang
7-B.3 Fast Thermal Analysis on GPU for 3D-ICs with Integrated MicroChannel Cooling 551
Zhuo Feng, Peng Li
Session 7-C Physical Design for Manufacturability and VariabilityModerators: Yongseok Cheon - Synopsys, Inc.
Yufeng Luo - Mentor Graphics Corp.
7-C.l Native-Conflict-Aware Wire Perturbation for Double Patterning Technology 556
Szu-Yu Chen, Yao-Wen Chang
7-C.2 A Lower Bound Computation Method for Evaluation of Statistical Design Techniques 562
.
Vineeth Veetil, Dennis Sylvester, David Blaauw
7-C.3 Timing Yield Optimization via Discrete Gate-Sizing using Globally-Informed Delay PDFs 570
Shantanu Dutt, Huan Ren
Tutorial 7 Digital Microfluidic Biochips: A Vision for
Functional Diversity and More than Moore
Moderator: Krishnendu Chakrabarty - Duke Univ.
7-T.l Digital Microfluidic Biochips: A Vision lor Functional Diversity and More than Moore 578
Tsung-Yi Ho, Jun Zeng, Krishnendu Chakrabarty
Session 8-A Advances in Core Logic SynthesisModerators: Thomas Shiple - Synopsys, Inc.
Philip Brisk - Univ. of California, Riverside
8-A.l Bi-Decomposition of Large Boolean Functions using Blocking Edge Graphs 586
Mihir Choudhwy, Kartik Mohanram
8-A.2 Peak Current Reduction by Simultaneous State Replication and Re-Encoding 592
Junjun Gu, Lin Yuan, Gang Qu, Qiang Zhou
8-4.3 Boolean Matching of Function Vectors with Strengthened Learning 596
Chih-Fan Lai, Jie-Hong RolandJiang, Kuo-Hua Wang
8-A.4 Reduction of Interpoiants for Logic Synthesis 602
John Baches, Marc Riedel
Session 8-B Routing - Theory and Practice
Moderators: Cheng-Kok Koh - Purdue Univ.
Ting-Chi Wang - National Tsing-Hua Univ.
8-B.l Obstacle-Avoiding Rectilinear Steiner Minimum Tree Construction: An Optimal Approach 610
Tao Huang, Evangeline F. Y. Young
8-B.2 On the Escape Routing of Differential Pairs 614
Tan Yan, Pei-Ci Wu, Qiang Ma, Martin D. F. Wong
8-B.3 New Placement Prediction and Mitigation Techniques for Local Routing Congestion 621
Taraneh Taghavi, Charles Alpert, Andrew Huber, Zhuo Li, Gi-Joon Nam, Shyam Ramji,Lakshmi Reddy, Jarrod Roy, Gustavo Tellez, Paul Villarrubia, Natarajan Viswanathan
Session 8-C Power Optimization from Systems to Circuits
Moderators: Jiong Luo - Synopsys, Inc.
Muhammad Shafique - Karlsruhe Institute of Technology
8-C.l Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems 625
Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi,
Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai
8-C.2 Stretching the Limit of Microarchitectural Level Leakage Control with
Adaptive Light-Weight Vth Hopping 632
Hao Xu, Wen-Ben Jone, Ranga Vemuri
8-C.3 Current Shaping and Multi-Thread Activation for Fast and Reliable Power Mode
Transition in Multicore Designs 637
HaoXu, Ranga Vemuri, Wen-Ben Jone
Tutorial 8 Manufacturing, CAD and Thermal-Aware Architectures for 3-D MPSoCs
Moderator: DavidAtienza - Ecole Polytechnique Federate de Lausanne
8-T.I Fuzzy Control for Enforcing Energy Efficiency in High Performance 3-D Systems 642
Mohamed Sabry, Ayse Coskun, David Atienza
Session 9-A Algorithms for Placement: Full House
Moderators: Yegna Parasuram - Mentor Graphics Corp.BillHatpin - Synopsys, Inc.
9-A.l SimPL: An Effective Placement Algorithm 649
Myung-Chul Kim, Dong-Jin Lee, Igor Markov
9-A.2 Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs 657
Meng-Kai Hsu, Yao- Wen Chang
9-A.3 Design-Hierarchy Aware Mixed-Size Placement for Routability Optimization 663
Yi-Lin Chuang, Gi-Joon Nam, Charles Alpert, Yao-Wen Chang, JarrodRoy,Natarajan Viswanaihan
9-A.4 Stress-Driven 3D-1C Placement with TSV Keep-Out Zone and Regularity Study 669
Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Pan, Sung Kyu Lim
9-A.5 Practical Placement and Routing Techniques for Analog Circuit Designs 675
Linfu Xiao, Evangeline F. Y. Young, Xiaoyong He, K.P. Pun
Session 9-B Analysis and Algorithms for Design and Test in 3D and Many-Core SystemsModerators: Arijit Raychowdhury - Intel Corp.
Saibal Mukhopadhyay - Georgia Institute of Technology
9-B.l Characterizing the Lifetime Reliability of Manycore Processors with Core-Level Redundancy 680
Lin Huang, QiangXu
9-B.2 Electrical Characterization of RF TSV for 3D Multi-Core and Heterogeneous ICs 686
Le Yu, Haigang Yang, Tom T, Jing, Min Xu, Robert Geer, Wei Wang
9-B.3 Design Method and Test Structure to Characterize and Repair TSV Defect
Induced Signal Degradation in 3D System 694
Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay
9-B.4 Fast Poisson Solvers for Thermal Analysis 698
Haifeng Qian, Sachin Sapatnekar
Session 9-C Advanced Analysis of Circuit/Device ReliabilityModerators: Eric Keiter - Sandia National Labs
Bruce McGaughy - ProPlus Design Solutions, Inc.
9-C.l Sequential Importance Sampling for Low-Probability and
High-Dimensional SRAM Yield Analysis 703
Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
9-C.2 Simulation of Random Telegraph Noise with 2-Stage Equivalent Circuit 709
Yun Ye, Chi-Chao Wang, Yu Cao
9-C.3 Work-Function Variation Induced Fluctuation in Bias-Temperature-InstabilityCharacteristics of Emerging Metal-Gate Devices and Implications for Digital Design 714
Seid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee
9-C.4 Structured Analog Circuit Design and MOS Transistor Decomposition for
High Accuracy ApplicationsBo Yang, Qing Dong, Jing Lin, Shigetoshi Nakatake
721
Session 10-A Advanced Applications of Logic SynthesisModerators: Vigyan Singhal - Oski Technology, Inc.
Naehyuck Chang - Seoul National Univ.
10-A.l A Robust Functional ECO Engine by SAT Proof Minimization and
Interpolation Techniques 729
Bo-Han Wu, Chun-Ju Yang, Chung-Yang (Ric) Huang, Jie-Hong Roland Jiang
10-A.2 Efficient Arithmetic Sum-of-Product (SOP) based Multiple Constant
Multiplication (MCM) for FFT 735
Vinay Karkala, Joseph Wanstrath, Travis Lacour, Sunil Khatri
10-A.3 Analysis of Precision for Scaling the Intermediate Variables in
Fixed-Point Arithmetic Circuits 739
OmidSarbishei, Katarzyna Radecka
10-A.4 Synthesis of an Efficient Controlling Structure for the Post-Silicon Clock Skew Minimization 746
Mac Y. C Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang
10-A.5 Engineering a Scalable Boolean Matching based on EDA SaaS 2.0 750
Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong
10-A.6 Polynomial Datapath Optimization using Constraint Solving and Formal Modelling 756
Firm Haedicke, Bijan Alizadeh, Goerschwin Fey, Masahiro Fujita, RolfDrechsler
Session 10-B Advances in Verification
Moderators: Anubhav Gupta - Synopsys, Inc.
Sanjit Seshia - Univ. ofCalifornia, Berkeley
10-B.l Online Selection of Effective Functional Test Programs based on Novelty Detection 762
Po-Hsien Chang, Dragoljub Gagi Dramanac, Li.-C Wang
10-B.2 Flexible Interpolation with Local Proof Transformations 770
Roberto Bi~uttomesso, Simone Fulvio Rollini, Natasha Sharygina, Aliaksei Tsitovich
10-B.3 Symbolic Performance Analysis of Elastic Systems 778
Marc Galceran-Oms, Jordi Cortadella, Michael Kishinevsky
10-B.4 Efficient State Space Exploration: Interleaving Stateless and State-Based Model Checking 786
Malay Ganai, Chao Wang, Weihong Li
10-B.5 Formal Deadlock Checking on High-Level SystemC Designs 794
Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao, Chung-Yang (Ric) Huang
Session 10-C Recent Advances in Power Grid and Interconnect AnalysisModerators: Marek Patyra - Intel Corp.
Nagib Hakim - Intel Corp.
10-C.l PEDS: Passivity Enforcement for Descriptor Systems via
Hamiltonian-Symplectic Matrix Pencil Perturbation 800
Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Grantham K.H. Pang, Ngai Wong
10-C.2 Power Grid Correction Using Sensitivity Analysis 808
Meric Aydonai, FaridN. hlajm
10-C.3 Early P/G Grid Voltage Integrity Verification 816
Mehmet Avci, FaridN. Najm
10-C.4 Characterization of the Worst-Case Current Waveform Excitations in
General RLC-Model Power Grid Analysis 824
Nestor Evmorfopoulos, Maria-Aikatehni Rammou, George Statnoulis, John Moondanos