2013 mazumdar patent us8570203

US008570203B2

(12) United States Patent Mazumdar et a].

US 8,570,203 B2 Oct. 29, 2013

(10) Patent N0.: (45) Date of Patent:

(54) METHOD AND APPARATUS FOR DIRECT DIGITAL SYNTHESIS OF SIGNALS USING TAYLOR SERIES EXPANSION

(75) Inventors: Dipayan Mazumdar, Bangalore (IN); Govind RangasWamy Kadambi, Bangalore (IN)

(73) MS. Ramaiah School of Advanced Studies, Banaglore Karnataka (IN)

Assignee:

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 23 days.

(21) Appl. N0.: 13/389,562

(22) PCT Filed: Oct. 19, 2010

(86) PCT N0.:

§ 371 (0X1)’ (2), (4) Date:

PCT/IB2010/054721

Feb. 8, 2012

PCT Pub. No.: WO2012/025796

PCT Pub. Date: Mar. 1, 2012

(87)

(65) Prior Publication Data

US 2012/0223847 A1 Sep. 6,2012

(30) Foreign Application Priority Data

Aug. 27, 2010 (IN) ......................... .. 2489/CHE/2010

(51) Int. Cl. H03M 1/66 US. Cl. USPC ......................................... .. 341/147; 341/100

Field of Classi?cation Search USPC .......... .. 341/147, 101, 100; 600/310; 356/372 See application ?le for complete search history.

(2006.01) (52)

(58)

(56) References Cited

U.S. PATENT DOCUMENTS

3,551,826 A 12/1970 Sepe 3,582,810 A 6/1971 Gillette 3,654,450 A 4/1972 Webb 3,735,269 A 5/1973 Jackson 4,752,902 A 6/1988 Goldberg 4,905,177 A 2/1990 Weaver, Jr. et a1. 4,951,004 A 8/1990 Sheffer et al. 4,958,310 A 9/1990 Goldberg

(Continued)

FOREIGN PATENT DOCUMENTS

EP 0443242 8/1991 EP 1646142 A1 4/2006

OTHER PUBLICATIONS

Jridi, et a1, “Direct Digital Synthesizer with CORDIC Algorithm and Taylor Series Approximation for Digital Receivers”, European Jour nal ofScienti?c Research, ISSN 145-212X, vol. 30, No. 4 (2009), pp. 542-5 53.

(Continued)

Primary Examiner * Brian Young (74) Attorney, Agent, or Firm * Brundidge & Stanger, PC.

(57) ABSTRACT A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modi?ed phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single adder. Values stored in the ROMs may produce one compo nent of a sinusoid signal, and each of the ROMs may be of a different siZe, such as a coarse, intermediate, and ?ne ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs When combined can form a digital output signal in the form of a Taylor series expansion of a sinusoid function.

20 Claims, 17 Drawing Sheets

. . . Output Analog Output

Frequency Signal (00s) \4 if“) 228 200 DAG 2_0_§

Register m

Register E

Adder 224

\i/ 1 Register Register m m

1 Reg isler

2.2.2.

ROM m

[sin (% u)] ROM 1L1 ROM 23

(u) (u) (P-u) (u) M) ‘(P-u) (u)

K Phase to Phase Accumulator

m Clock Frequency (fin)

Converter 204

US 8,570,203 B2

(56) References Cited

U.S. PATENT DOCUMENTS

6,587,862 B1 7/2003 Henderson 6,732,128 B2 5/2004 Kelly 7,580,007 B2* 8/2009 Brown et al. ................. .. 345/15 7,599,977 B2 10/2009 Ammar 7,701,260 B1* 4/2010 Old ............................. .. 327/106

2005/0262175 A1* 11/2005 Iino et al. .................... .. 708/276 2008/0016141 A1 1/2008 Bushman etal.

OTHER PUBLICATIONS

Bellaouar, et al., “Low-Power Direct Digital Frequency Synthesis for Wireless Communications”, IEEE Journal of SolidState Circuits, vol. 35, No. 3, Mar. 2000, pp. 385-390. Vankka, “Direct Digital Synthesizers: Theory, Design and Applica tions”, Thesis, Helsinki University of Technology, Department of Electrical and Communications Engineering, Electronic Circuit Design Laboratory, Nov. 2000. Torosyan, “Direct Digital Frequency Synthesizers: Complete Analy sis and Design Guidelines”, Thesis, University of California, 2003. Radhakrishnan, “Low Power CMOS Pass Logic 4-2 Compressor for High-Speed Multiplication”, Proc. 43rd IEEE Midwest Symp. on Circuits and Systems, Lansing MI, Aug. 8-11, 2000. Brandon, “Direct Digital Synthesizers are Known for Their Highly Accurate Digital Tuning, Low Noise Figure, and Phase-Continuous

Frequency-Hopping Capabilities, which Make Them More Attrac tive than Alternative Analog Frequency-Synthesis Solutions”, DDS Design, www.edn.com, May 13, 2004, pp. 71-84. Pothuri, “Design of Pulse Output Direct Digital Synthesizer with an Analog Filter Bank”, Thesis, B. Tech., Jawaharlal Nehru Technologi cal University, 2005. A Technical Tutorial on Digital Signal Synthesis, Analog Devices, Inc, 1999. Love, Janine Sullivan, RF Front-End World Class Designs, “Chapter 9 RF/IF Circuits”, copyright 2009, ISBN: 978-1-85617-622-4, pp. 259-267. Cleveland, “First-Order-Hold Interpolation Digital-to-Analog Con verter with Application to Aircraft Simulation”, Nasa Technical Note, NASA TN D-8331, Nov. 1976. The free encyclopedia from Wikipedia, “Direct Digital Synthesizer,” http://en.wikipedia.org/wiki/Directidigitalisynthesis, printed on Feb. 8, 2012. The free encyclopedia from Wikipedia, “Cognitive Radio,” http://en. wikipedia.org/wiki/Congnitiveiradio, printed on Feb. 8, 2012. International Search Report and Written Opinion prepared by the Australian Patent Of?ce for PCT/ IB20 10/ 054721 completed Dec. 13, 2010. Vankka, J ., et al., “A direct digital synthesizer with an on-chip D/A converter,” IEEE Journal of Solid State Circuits, vol. 33, No. 2, pp. 218-227 (1998).

* cited by examiner

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US. Patent US 8,570,203 B2 Oct. 29, 2013 Sheet 15 0f 17

Analog Output Signal

1146

1142 1144

Serial to Serial to Serial to Serial to Parallel Parallel Parallel Parallel

Conversion Conversion Conversion Conversion

Differential Differential Differential Differential to single to single to single to single ended ended ended ended

conversion conversion conversion conversion

Shift Register Shift Register Shift Register Shift Register Serial to Parallel Serial to Parallel Serial to Parallel Serial to Parallel

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To Serial To Serial To Serial To Serial differential differential differential differential

1110 1132 1134 1136

XnI X2 I 1X1 k

Register 1108

ll

ROM 1106

YnI Y2 I Y1

Register 1126

AL

ROM 1120

znI Z2 Z1 1

ROM 1122

Figure 118

W311 W2 W1 1

Register 1130 A

ROM 1124

US. Patent

1200

Oct. 29, 2013 Sheet 16 0f 17

@

US 8,570,203 B2

Receive a phase angle value of a sinusoid, where the phase angle value is in a binary form

1 202

l Receive a number of most significant bits and least

significant bits of the binary form phase angle value as inputs at one or more memory elements 1204

1, Using the most significant bits and the Eeast significant

bits as memory address locations 1206

Retrieve from a first memory element values of a first component in the Taylor series expansion )

1208

l Retrieve from a second memory element values that when

combined with values retrieved from a third memory element represent a second component in the Taylor

series expansion 1210

i Retrieve from a fourth memory element values of a third

component in the Taylor series expansion

V

Convert outputs of the one or more memory elements to serial bitstreams for transmission

l

1212

1214

Convert the serial bitstreems into parallel bitstreams for processing

1216

i Combine the parallel bitstreams in a manner to generate the first, second, and third of the Taylor series expansion 1218

Convert the first component, the second component, and the third component of the Taylor series expansion to an

analog output signal

i @

Figure 12

1220

US 8,570,203 B2 1

METHOD AND APPARATUS FOR DIRECT DIGITAL SYNTHESIS OF SIGNALS USING

TAYLOR SERIES EXPANSION

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to a corresponding patent application ?led in India and having application num ber 2489/CHE/20l0, ?led on Aug. 27, 2010, the entire con tents of Which are herein incorporated by reference. The present application is a US. National Phase Application pur suant to 35 U.S.C. 371 of International Application No. PCT/ IB2010/ 054721, ?led on Oct. 19, 2010, the entire contents of Which are herein incorporated by reference.

BACKGROUND

Many communications and radar systems require radio frequency (RF) synthesiZer performance, Which often can be dif?cult to implement using direct frequency multiplication, phase-locked-loop (PLL), or direct digital synthesiZer (DDS) techniques. To achieve characteristics of a desired frequency range, a high frequency output, a ?ne tuning resolution, a fast settling time, and a loW phase noise, system designers often combine PLL and DDS technologies. The strengths of one technology join With strengths of the other technology to extend a possible range of performance. As one example, a PLL, also knoWn as Indirect synthesis,

is a negative feedback loop structure that locks a phase of an output signal after division to a reference clock. Thus, the output signal of the PLL has a phase related to a phase of the input reference signal. For example, the PLL compares a phase of an input signal With a phase signal derived from its output oscillator signal and adjusts a frequency of its oscilla tor to keep the phases matched. A PLL may include a variable counter (divider) to alloW generation of many frequencies by changing a division ratio. As another example, DDS is a technique for using digital

data processing blocks to generate a frequency and phase tunable output signal referenced to a ?xed-frequency clock source. The reference clock frequency is divided doWn in a DDS architecture by a scaling factor set forth in a program mable binary tuning Word. The tuning Word is typically 24-48 bits long Which enables a DDS implementation to provide high output frequency tuning resolution. DDS technologies may be used to achieve fast sWitching

(typically less than a micro second), Which can be important in spread-spectrum or frequency-hopping systems including radar and communication systems. Additional advantages of DDS technologies include ?ne tuning steps, loW phase noise, transient-free (phase continuous) frequency changes, ?ex ibility as a modulator, and small siZe, among others.

HoWever, DDS systems may have an operating range that is limited by the Shannon, Nyquist sampling theory. For example, an output is typically limited to about 45% of a maximum clock rate at Which the DDS can be operated. Another limitation of DDS systems may include spectral purity, Which is governed by a density/complexity of the DDS circuitry that is attainable at a desired operating speed.

SUMMARY

In one aspect, an example system for outputting a sinusoid signal formed by using a Taylor series expansion is provided. The system comprises one or more memory elements. A ?rst memory element stores values of a ?rst component in the

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2 Taylor series expansion, a second memory element stores values that When combined With values stored in a third memory element represent a second component in the Taylor series expansion, and a fourth memory element stores values of a third component in the Taylor series expansion. The system also comprises a plurality of parallel to serial convert ers. One parallel to serial converter is coupled to each of the one or more memory elements, and the parallel to serial converters convert outputs of the memory elements to serial bitstreams for transmission. The system also comprises a plurality of serial to parallel converters receiving the serial bitstreams and converting the serial bitstreams into parallel bitstreams. The system also comprises an adder receiving the outputs of the ?rst memory element, the second memory element, the third memory element, and the fourth memory element as parallel bitstreams from the plurality of serial to parallel converters, and adding the outputs in a manner to generate the ?rst component, the second component and the third component of the Taylor series expansion and combin ing the ?rst component, the second component and the third component to form a signal output. The system further com prises a digital-to-analog converter (DAC) receiving the sig nal output from the adder and converting the signal output to an analog output signal, and a loW pass ?lter receiving the analog output signal from the DAC and providing a ?ltered analog output signal.

In another aspect, an example method of generating a Tay lor series expansion of a sinusoid signal is provided. The method comprises receiving a phase angle value of a sinusoid that is in a binary form, and receiving a number of most signi?cant bits and least signi?cant bits of the binary form phase angle value as inputs at one or more memory elements. The method also comprises using the most signi?cant bits and the least signi?cant bits as memory address locations to retrieve (i) from a ?rst memory element a value of a ?rst component in the Taylor series expansion, (ii) from a second memory element a value that When combined With a value retrieved from a third memory element represent a second component in the Taylor series expansion, and (iii) from a fourth memory element a value of a third component in the Taylor series expansion. The method further comprises con verting outputs of the one or more memory elements to serial bitstreams for transmission, and converting the serial bit streams into parallel bitstreams for processing. The method also comprises combining the parallel bitstreams in a manner to generate the ?rst component, the second component and the third component of the Taylor series expansion, and con verting the ?rst component, the second component and the third component of the Taylor series expansion to an analog output signal.

In another aspect, an example computer readable medium having stored therein instructions executable by a computing device to cause the computing device to perform functions is provided. The functions comprise receiving a phase angle value of a sinusoid that is in a binary form. The functions also comprise using a number of most signi?cant bits and least signi?cant bits of the binary form phase angle value as memory address locations to retrieve (i) from a ?rst memory element a value of a ?rst component in the Taylor series expansion, (ii) from a second memory element a value that When combined With a value retrieved from a third memory element represent a second component in the Taylor series expansion, and (iii) from a fourth memory element a value of a third component in the Taylor series expansion. The func tions also comprise converting outputs of the one or more memory elements to serial bitstreams for transmission, and converting the serial bitstreams into parallel bitstreams for

2013 mazumdar patent us8570203

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