2013 IEEE Projects @ s3technoloiges Contact: 0452- 4373398, 9789339435

S.N. IEEE 2013-2014 TITLESVLSI

Language

1. Pipelined Radix-   Feedforward FFT Architectures VHDL/verilog

2. A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks

VHDL/verilog

3. STBC-OFDM Downlink Baseband Receiver for Mobile WMAN

VHDL/verilog

4. Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip

VHDL/verilog

5. Application Space Exploration of a Heterogeneous un-Time Configurable Digital Signal Processor

VHDL/verilog

6. Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor

VHDL/verilog

7. CORDIC Designs for Fixed Angle of Rotation VHDL/verilog

8. A Unified Graphics and Vision Processor With a 89   W/fps Pose Estimation Engine for Augmented Reality

VHDL/verilog

9. A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

VHDL/verilog

10. Low Latency Systolic Montgomery Multiplier for Finite Field   Based on Pentanomials

VHDL/verilog

11. Architecture and Design Flow for a Highly Efficient Structured ASIC

VHDL/verilog

12. Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform

VHDL/verilog

13. Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform

VHDL/verilog

14. A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

VHDL/verilog

43, North Masi Street, Opp of Krishnan Kovil, Simmakkal, Madurai

2013 IEEE Projects @ s3technoloiges Contact: 0452- 4373398, 9789339435

15. Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

VHDL/verilog

16. 135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

VHDL/verilog

17.Reconfigurable Accelerator for the Word-Matching Stage of BLASTN

VHDL/verilog

18. Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems

VHDL/verilog

19. MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems

VHDL/verilog

20. Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems

VHDL/verilog

21. Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs

VHDL/verilog

22. Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping

VHDL/verilog

23. Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping

VHDL/verilog

24. Architecture for Real-Time Nonparametric Probability Density Function Estimation

VHDL/verilog

25. Combined Architecture/Algorithm Approach to Fast FPGA Routing

VHDL/verilog

26. Asynchronous Fine-Grain Power-Gated Logic VHDL/verilog

27. All-Digital Fast-Locking Pulsewidth-Control Circuit With VHDL/verilog

43, North Masi Street, Opp of Krishnan Kovil, Simmakkal, Madurai

2013 IEEE Projects @ s3technoloiges Contact: 0452- 4373398, 9789339435

Programmable Duty Cycle28. Energy-Efficient Digital Signal Processing via Voltage-

Overscaling-Based Residue Number SystemVHDL/verilog

29. Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design

VHDL/verilog

30. Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications

VHDL/verilog

31. Enhanced Secure Architecture for Joint Action Test Group Systems

VHDL/verilog

32. Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications

VHDL/verilog

33. An efficient FPGA implementation of the Advanced Encryption Standard algorithm

VHDL/verilog

34. Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT

VHDL/verilog

35. Separable Reversible Data Hiding in Encrypted Image VHDL/verilog

36. Low-Power Low-Cost Design of Primary Synchronization Signal Detection

VHDL/verilog

37. A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

VHDL/verilog

38. An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy

VHDL/verilog

39. A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor

VHDL/verilog

40. Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure

VHDL/verilog

41. Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip

VHDL/verilog

42. A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy

VHDL/verilog

43. Low Latency and Energy Efficient Scalable Architecture for VHDL/verilog

43, North Masi Street, Opp of Krishnan Kovil, Simmakkal, Madurai

2013 IEEE Projects @ s3technoloiges Contact: 0452- 4373398, 9789339435

Massive NoCs Using Generalized de Bruijn Graph44. A Low-Power Low-Cost Design of Primary Synchronization

Signal DetectionVHDL/verilog

45. Low-Power and Area-Efficient Carry Select Adder VHDL/verilog

46. Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain

VHDL/verilog

47. Physical-Defect Modeling and Optimization for Fault-Insertion Test

VHDL/verilog

48. Reconfigurable Routers for Low Power and High Performance

VHDL/verilog

49.A Reliable Routing Architecture and Algorithm for NoCs

VHDL/verilog

50. Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays

VHDL/verilog

51. Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

VHDL/verilog

52. Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction

VHDL/verilog

43, North Masi Street, Opp of Krishnan Kovil, Simmakkal, Madurai