2016 IEEE International Electron Devices MeetingDecember 3rd—7th, 2016

Hilton San Francisco Union Square, San Francisco, California

IEDM 2016 HighlightsPlenary Presentations

Memory Scaling – Challenges and Opportunities, Seok-Hee Lee, Hynix Brain-Inspired Computing, Dharmendra S. Mohda, IBM Differentiating Technologies and Novel Opportunities for the Future Internet of Everything: The Quest for Power Efficiency, Marie-Noëlle Semeria, CEA-Leti

Special Focus Sessions System-Level Impact of Power Devices Wearable Electronics and Internet of Things Ultra High Speed Electronics Quantum Computing

Evening Panel Discussions How Will the Semiconductor Industry Change to Enable 50 Billion Connected Devices? Challenges and Opportunities for Neuromorphic and Machine Learning

Entrepreneur Luncheon Speaker(Sponsored by IEEE Women in Engineering)

Vamsee Pamula, Founder of Baebies

IEDM Luncheon SpeakerProf. Roberto Cingolani, Istituto Italiano di Tecnologia

Translating Evolution into Technology: From Biochemical Robots to Autonomous Anthropomorphic Machines

Professional Development

The Struggle to Keep Scaling BEOL, and What We Can Do Next

Physical Characterization of Advanced Devices

Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications

Electronic Circuits and Architectures for Neuromorphic Computing Platforms

Present and Future of FEOL Reliability - From Dielectric Trap Properties to Reliable Circuit Operation

Technologies for IoT and Wearable Applications Including Advances in Cost-Effective and Reliable Embedded Non-Volatile Memories

IEDM’s program consists of more than 200 papers from the world’s leading experts from industry, government & academia, covering the following topics:Circuit and Device Interaction Characterization, Reliability and Yield Compound Semiconductor and High Speed Devices Memory Technology Modeling and Simulation

Nano Device Technology Optoelectronics, Displays, and Imagers Power Devices Process and Manufacturing Technology Sensors, MEMS, and BioMEMS

Technology Options at the5 Nanometer Node

Nano Patterning Challenges at the 5nm Node Novel Channel Materials for High-Performance and Low-Power CMOS Transistor Options & Challenges for 5nm Technology Low Resistance Contacts to Enable 5nm Node Technology: Patterning, Etch, Clean, Metallization and Device Performance Parasitic R and C Mitigation Options for BEOL and MOL in N5 Technology Metrology Challenges for 5nm Technology

Design/Technology Enablers for Computing Applications

The Rise of Massively Parallel Processing: Why the Demands of Big Data and Power Efficiency Are Changing the Computing Landscape Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: A Design and Technology Perspective Power Management with Integrated Power Device…and How GaN Changes the Story Interconnect Challenges for Future Computing Advanced Packaging Technologies for System Integration

Tutorials Saturday, December 3

Short Courses Sunday, December 4

IEDM Online: ieee-iedm.orgSocial Networks: ieee-iedm.org/social-media