ELECTRONICSDIGITAL CIRCUITS

DIGITAL SIGNALS

• Digital electronics uses signals which can take logical values – one of two

discrete states:

• ‚0’, LOW

• ‚1’, HIGH

• In fact these two correspond to analog voltages:

• Most commonly:

• 0V

• VCC/VDD (5V, 3.3V, 2.5V, 1.2V, 1.1V … )

• Or other strictly defined (i.g. -5V/+5V)

LOGIC LEVELS

• Digital circuit has voltage levels defined, corresponding to logical values:

• Input voltage range (VIL i VIH - Input Low/High), for which the continous voltage

level is interpreted as a particular logical value

• Output voltage range (VOL, VOH - Output Low/High), that the circuit outputs, for a

given logical value

• CMOS technology circuit

voltages (VDD = 5V):

• Output for ‚1’ – (4.7V, 5V)

• Output for ‚0’ – (0V, 0.2V)

• Input for ‚1’ – (2V, 5V)

• Input for ‚0’ – (0V, 0.8V)

LOGIC LEVELS

• Connection of digital circuits must ensure, that input and output logical levels

between the circuits match to each other (worst case must be considered):

• Circuits made with the same technology can be connected together

e.g. TTL<->TTL, or CMOS<->CMOS

• For different technologies the voltage levels must be compared. E.g. circuits of the

given technologies can be

connected together –

CMOSv->TTL, but not the

other way - TTL->CMOSv

(TTL out 3.3V < CMOSv in 3.7V

– worst case not satisfied)

• Independently of the technology

each digital circuit precisely

specifies its voltage levels

LOGIC LEVELS

• Example NAND gate, depending on the supply voltage level:

7400 SERIES

• 7400 series assigns numbers to particular logical circuits

• They are made with different technologies, but the same numbers e.g.

SN74LS08N, 74HCT08DB (circuit consisting of four two-input AND gates)

BOOLEAN ALGEBRA & OPERATORS

• Boolean algebra consists of:

• B set consisting of elements { 0, 1 }

• One-argument operator:

• Negation (inversion, NOT)

• 𝑥

• ~𝑥

• Two-argument operators:

• Disjunction (sum, OR)

• 𝑥 + 𝑦

• 𝑥 ∨ 𝑦

• Conjunction (product, AND)

• 𝑥 ⋅ 𝑦

• 𝑥 ∧ 𝑦

x y 𝑥 + 𝑦 𝑥 ⋅ 𝑦

0 0 0 0

0 1 1 0

1 0 1 0

1 1 1 1

x ~𝑥

0 1

1 0

PROPERTIES

• Associativity + commutativity

• Distributivity of AND over OR

• De Morgan laws

• Others

OPERATORS 2

• Additiona operators can be defined:

• Implication

• Equivalence

• Exlusive OR (XOR)

• 𝑥⨁𝑦

• Inverted OR (NOR)

• ~(𝑥 + 𝑦)

• 𝑥 ∨ 𝑦

• Inverted AND (NAND)

• ~(𝑥 ⋅ 𝑦)

• 𝑥 ∧ 𝑦

x y ~(𝑥 + 𝑦) ~(𝑥 ⋅ 𝑦)

0 0 1 1

0 1 0 1

1 0 0 1

1 1 0 0

x y 𝑥 → 𝑦 𝑥 ⟺ 𝑦 𝑥⨁𝑦

0 0 1 1 0

0 1 1 0 1

1 0 0 0 1

1 1 1 1 0

LOGIC GATES

• Electronic components realizing logical

operation are called logical gates:

• Identity (buffer)

𝑞 = 𝑥

• Negation (NOT)

𝑞 = ~𝑥

• Conjunction (AND)

𝑞 = 𝑎 ⋅ 𝑏

• Disjunction (OR)

𝑞 = 𝑎 + 𝑏

• Inverted AND (NAND)

𝑞 = ~(𝑎 ⋅ 𝑏)

• Inverted OR (NOR)

𝑞 = ~(𝑎 + 𝑏)

• Exlusive OR (XOR)

𝑞 = 𝑎⨁𝑏

• Inverted exlusive OR (XNOR)

𝑞 = ~(𝑎⨁𝑏)

IMPLEMENTATION

• NAND gate implementation in TTL and CMOS technologies:

FUNCTIONAL COMPLETENESS

• A set of functional complete gates – a set of logic gates that allows to

implement any boolean function with it.

• The following gate sets are functionally complete:

• AND, NOT

• OR, NOT

• NAND

• NOR

• Using only one type of logic gates simplifies physical complexity of a circuit

(e.g. only NAND gates are used)

FUNCTIONAL COMPLETE SET - NAND

• Realization of other gates using only NAND gate

• NOT:

• y = nand(x, x) = ~(x ⋅ x) = ~x

• y = nand(x, 1) = ~(x ⋅ 1) = ~x

• AND:

• y = nand(nand(x, y), nand(x, y)) = and(x, y)

y = ~((~(a ⋅ b)) ⋅ ~(a ⋅ b)) = ~(~(a ⋅ b)) = a ⋅ b

• OR:

• y = nand(nand(a, a), nand(b, b)) = or(a, b)

• ~((~(a * a)) * (~(b * b))) = ~(~a * ~b) = a + b (De Morgan law)

• Buffer:

• y = nand(nand(x, x), nand(x, x)) = y

FUNCTIONAL COMPLETE SET - NAND

• OR:

• OR aimilar to previous example (De Morgan law) + inversion

• y = nand(or(a, b), or(a, b)) = nor(a, b)

• ~((a + b) * (a + b)) = ~(a + b)

• XOR:

• y = (a ⋅ ~b) + (~a ⋅ b)

• XNOR: additional inversion on the output

DIGITAL CIRCUITS

• Digital circuits can be represented as a „black box”, having inputs and outputs.

• An „input vector” is passed to the input, and an „output vector” is given at the

output.

• Digital circuits are divided into:

• Combination – output state at the given moment is dependent on the input state at

the same moment.

• Sequential – output state at a given moment is dependent on the input state at the

same moment and at previous moments. Such a circuit has its internal state.

Sequential circuits are divided into:

• Synchronous, where output and internal vector state changes are synchronized

with the external clock signal.

• Asynchronous, where there is no external clock signal and vector state

changes occur „immediately” when the input changes.

COMBINATIONAL DIGITAL CIRCUITS

• A combinational digital circuit can be described in variuos ways:

• By boolean equation

• y = a + (b ⋅ c)

• With a Truth table – all the possible input vectors are listed and have an output

value assigned

• With a Karnaugh Mapabc y

000 0

001 0

010 0

011 1

100 1

101 1

110 1

111 1

ab\c 0 1

00 0 0

01 0 1

11 1 1

10 1 1

CODES

• Decimal system

• For a decimal number n, consisting of decimal digit sequence dkdk-1dk-2...d1d0, the

value of n is equal to:

𝑛 =

𝑖=0

𝑘

10𝑖 ⋅ 𝑑𝑖

• Binary system

• Analogous. Base of the system is the value of 2, instead the value of 10.

• For a binary number n, consisting of bit sequence bkbk-1bk-2... b1b0, the value of n is

equal to:

𝑛 =

𝑖=0

𝑘

2𝑖 ⋅ 𝑏𝑖

• Example: 11012 = 23 ⋅ 1 + 22 ⋅ 1 + 21 ⋅ 0 + 20 ⋅ 1 = 8 + 4 +1 = 1310

CODES – GRAY CODE

• Gray code is a binary code for which the cosecutive words differ in only one

bit between each other.

• Gray code:

• Two-bit: 00, 01, 11, 10

• Three-bit: 000, 001, 011, 010, 110, 111, 101, 100

• Four-bit code can be made by adding a leading zero to all three-bit code words,

and then adding a leading one to all three-bit code words, but in reverse order

KARNAUGH MAP

• A combinational circuit can be described by a set of boolean equations, truth

table, which consists of output values for all the possible inputs, or by a

Karnaugh Map.

• Karnaugh Map is a table, the cells of which contain the output vector values.

• Cell position determines the input vector given for this particular cell.

• Rows/columns define the input vector parts.

• The consecutive rows/columns are numbered by using Gray code.

KARNAUGH MAP

• A function given with a Truth Table and a

Karnaugh Map.

x3x2\x1x0 00 01 11 10

00 0 0 0 0

01 0 1 0 1

11 1 1 0 1

10 1 1 0 0

x3x2x1x0 y

0000 0

0001 0

0010 0

0011 0

0100 0

0101 1

0110 1

0111 0

1000 1

1001 1

1010 0

1011 0

1100 1

1101 1

1110 1

1111 0

KARNAUGH MAP

• Problem: How to implement a circuit, given with a Karnaugh Map, with the

minimum possible number of logic gates ?

1. Group all the neighbouring 1`s int groups of size being a power of 2 (2^N = 1,

2, 4, 8..) Groups should be as big as possible. Grouping through the table edges

is allowed.

• Ones can occur in multiple groups

at the same time

• All the ones must be covered

• No zeros can be covered by the groups

2. For each group a product of input variables

must be assigned.

3. The resulting function is a sum of the products.

x3x2\x1x0 00 01 11 10

00 0 0 0 0

01 0 1 0 0

11 1 1 0 1

10 1 1 0 0

KARNAUGH MAP – EXAMPLE 1

1. Group of four ones - 𝑥3 ⋅ (~𝑥1)

2. Group of two ones - 𝑥2 ⋅ ~𝑥1 ⋅ 𝑥0

3. Group of two ones - 𝑥3 ⋅ 𝑥2 ⋅ (~𝑥0)

(through an edge)

4. Resulting function:

y = 𝑥3 ⋅ ~𝑥1 + 𝑥2 ⋅ ~𝑥1 ⋅ 𝑥0+ 𝑥3 ⋅ 𝑥2 ⋅ (~𝑥0)

5. Implementation using (only) NAND gates:

x3x2\x1x0 00 01 11 10

00 0 0 0 0

01 0 1 0 0

11 1 1 0 1

10 1 1 0 0

KARNAUGH MAP – EXAMPLE 2

• Function of four variables, given with Karnaugh Map.

• Groups of ones:

• ~𝑥1 ⋅ ~𝑥0

• ~𝑥3 ⋅ ~𝑥0

• 𝑥3 ⋅ ~𝑥2 ⋅ 𝑥1 ⋅ 𝑥0

• Resulting function:

y = ~𝑥1 ⋅ ~𝑥0 + ~𝑥3 ⋅ ~𝑥0 + 𝑥3 ⋅ ~𝑥2 ⋅ 𝑥1 ⋅ 𝑥0

• Implementation with AND and OR gates, and with NAND gates (NOT gates

omitted):

x3x2\x1x0 00 01 11 10

00 1 0 0 1

01 1 0 0 1

11 1 0 0 0

10 1 0 1 0

SEQUENTIAL DIGITAL CIRCUITS

• Sequential digital circuit is a circuit, which output state at a given moment is

dependent on the input state at the same moment and at previous moments.

• This implies a requirement for the circuit to have a „memory” to remember the

information regarding previous input vectors.

• Sequential circuits are divided into:

• Synchronous – where input and output vector states change only at the moments

determined by an external clock (the circuit is synchronized with the external clock).

• Asynchronous – where there is no external clock signal and vector state changes

occur „immediately” when the input changes.

SEQUENTIAL DIGITAL CIRCUITS – RS FLIP-FLOP

• The „memory” elements are flip-flops. Flip-flop „remembers” one bit of

information.

• Asynchronous RS flip-flop

• Inputs:

• Set (S)

• Reset (R)

• Active low level

(in neutral state it has a value of ‚1’)

• Activating both inputs is forbidden

• Outputs:

• Output (Q)

• Inverted output (~Q)

• RS flip-flop symbol:

SEQUENTIAL DIGITAL CIRCUITS – RS FLIP-FLOP

• Initial state (inputs not active ~S = 1, ~R=1, remembered Q = 0)

1

1

0

1

SEQUENTIAL DIGITAL CIRCUITS – RS FLIP-FLOP

• Setting value (inputs ~S = 0, ~R = 1, setting Q = 1)

0

1

1

0

1

1

0

1

SEQUENTIAL DIGITAL CIRCUITS – RS FLIP-FLOP

0

1

1

0

1

1

0

1

1

1

1

0

• Stable state (inputs inactive ~S = 1, ~R=1, remembered Q = 1)

SEQUENTIAL DIGITAL CIRCUITS – RS FLIP-FLOP

• Resetting value (inputs ~S = 1, ~R = 0, resetting Q = 0)

0

1

1

0

1

1

0

1

1

0

0

1

1

1

1

0

SEQUENTIAL DIGITAL CIRCUITS – D FLIP-FLOP

• D flip-flop

• Is synchronized with an external clock

• Triggering occurs at positive clock edge

• At each trigger, the flip-flop remembers

the input value D

• Regardles of the changing input in between – the

data is remembered only at clock edges

SEQUENTIAL DIGITAL CIRCUITS – D FLIP-FLOP

• Truth table of an example D-type flip-flop

• Real circuit SN74HCS74 consisting of a common hybrid solution (2 in 1):

• D-type flip-flop with CLK and D inputs

• RS-type flip-flop with ~PRE (~S - set) and ~CLR (~R - reset) inputs

• X w tabeli oznacza dowolną wartość (nie ma znaczenia, tzw. „don`t care”)

SEQUENTIAL DIGITAL CIRCUITS – D FLIP-FLOP

• Frequency divider implemented with a D-type flip-flop

• Square rectangular siglan is given at the CLK input of the flip-flop

• The inverted output (~Q) is fed

back to the input D

• The output signal (Q) changes

its state at every positive clock

edge

• The output frequency is one half

of the input frequency

SEQUENTIAL DIGITAL CIRCUITS – T FLIP-FLOP

• T flip-flop

• Is synchronized with an external clock

• Triggering occurs at positive clock edge

• At each trigger, the flip-flop changes its internal state if the input value is ‚1’

• An analogous frequency divider realized with T-type flip-flop:

SEQUENTIAL DIGITAL CIRCUITS – JK FLIP-FLOP

• JK flip-flop

• Is synchronized with an external clock

• Triggering occurs at positive clock edge

• The remembered value changes according

to the given truth table

• Real circuit SN74HC109 consisting of a common hybrid solution (2 in 1):

• JK-type flip-flop with CLK, J and K inputs

• RS-type flip-flop with ~PRE (~S - set)

and ~CLR (~R - reset) inputs

BINARY COUNTER

• Two bit counter, with overflow:

• 00

• 01

• 10

• 11

• Internal state represented by two D-type flip-flops

• Input signals:

• Stop (s) – counter stalls, if signal is active

• Up – counts up, when active, down, when inactive.

• Circuit output is its internal state

STATE DIAGRAM

• Next internal state table, dependent on present state and input signals

00 01

11 10

~su

~su

~su

~su ~s~u~s~u

~s~u

~s~u

s s

s s

q1q0\su 00 01 11 10

00 11 01 00 00

01 00 10 01 01

11 10 00 11 11

10 01 11 10 10

d1d0:

TRANSFER FUNCTIONS

• Flip-flop input functions

q1q0\su 00 01 11 10

00 1 0 0 0

01 0 1 0 0

11 1 0 1 1

10 0 1 1 1

q1q0\su 00 01 11 10

00 1 1 0 0

01 0 0 1 1

11 0 0 1 1

10 1 1 0 0

d1(s, u, q1, q0)d1 q1

clk

d0(s, u, q1, q0)d0 q0

clk

s

u

clk

d1: d0:

TRANSFER FUNCTIONS

q1q0\su 00 01 11 10

00 1 0 0 0

01 0 1 0 0

11 1 0 1 1

10 0 1 1 1

q1q0\su 00 01 11 10

00 1 1 0 0

01 0 0 1 1

11 0 0 1 1

10 1 1 0 0

d1: d0:

• d1 = q1s + q1~q0u + q1q0~u + ~q1q0~su + ~q1~q0~s~u

• d0 = q0s + ~q0~s