24aa256/24lc256/24fc256 - microchip...

24AA256/24LC256/24FC256256K I2C™ CMOS Serial EEPROM

Device Selection Table

Features:• Single Supply with Operation Down to 1.7V for

24AA256 and 24FC256 Devices, 2.5V for 24LC256 Devices

• Low-Power CMOS Technology:- Active current 400 uA, typical- Standby current 100 nA, typical

• 2-Wire Serial Interface, I2C™ Compatible• Cascadable up to Eight Devices • Schmitt Trigger Inputs for Noise Suppression• Output Slope Control to Eliminate Ground Bounce• 100 kHz and 400 kHz Clock Compatibility• Page Write Time 5 ms max.• Self-Timed Erase/Write Cycle• 64-Byte Page Write Buffer• Hardware Write-Protect• ESD Protection >4000V• More than 1 Million Erase/Write Cycles• Data Retention >200 years• Factory Programming Available• Packages Include 8-lead PDIP, SOIC, DFN,

TSSOP and MSOP • Pb-Free and RoHS Compliant

• Temperature Ranges:

Description:The Microchip Technology Inc. 24AA256/24LC256/24FC256 (24XX256*) is a 32K x 8 (256 Kbit) SerialElectrically Erasable PROM, capable of operationacross a broad voltage range (1.7V to 5.5V). It hasbeen developed for advanced, low-power applicationssuch as personal communications or data acquisition.This device also has a page write capability of up to 64bytes of data. This device is capable of both randomand sequential reads up to the 256K boundary.Functional address lines allow up to eight devices onthe same bus, for up to 2 Mbit address space. Thisdevice is available in the standard 8-pin plastic DIP,SOIC, TSSOP, MSOP and DFN packages.

Block Diagram

Package Types

*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.

Part Number

VCC Range

Max. ClockFrequency

Temp. Ranges

24AA256 1.7-5.5V 400 kHz(1) I24LC256 2.5-5.5V 400 kHz I, E24FC256 1.7-5.5V 1 MHz(2) I

Note 1: 100 kHz for VCC < 2.5V.2: 400 kHz for VCC < 2.5V.

- Industrial (I): -40°C to +85°C- Automotive (E): -40°C to +125°C

HV Generator

EEPROM Array

Page Latches

YDEC

XDEC

Sense Amp.R/W Control

MemoryControlLogic

I/OControl

Logic

I/O

A0 A1A2

SDA

SCL

VCC

VSS

WP

A0

A1

A2

VSS

VCC

WP

SCL

SDA

1

2

3

4

8

7

6

5

24XX

256

PDIP/SOIC TSSOP/MSOP*

A0

A1

A2

VSS

1

2

3

4

8

7

6

5

VCC

WP

SCL

SDA

24XX

256

DFN

A0

A1

A2

VSS

WP

SCL

SDA24XX

256

5

6

7

8

4

3

2

1 VCC

Note: * Pins A0 and A1 are no connects for the MSOP package only.

© 2007 Microchip Technology Inc. DS21203P-page 1

24AA256/24LC256/24FC256

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at these or any other conditions above thoseindicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Ratingconditions for extended periods may affect device reliability.

DC CHARACTERISTICSElectrical Characteristics:Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°CAutomotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C

Param.No. Sym. Characteristic Min. Max. Units Conditions

D1 — A0, A1, A2, SCL, SDA and WP pins:

— — — —

D2 VIH High-level input voltage 0.7 VCC — V —D3 VIL Low-level input voltage — 0.3 VCC

0.2 VCCVV

VCC ≥ 2.5VVCC < 2.5V

D4 VHYS Hysteresis of Schmitt Trigger inputs(SDA, SCL pins)

0.05 VCC — V VCC ≥ 2.5V (Note)

D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 ma @ VCC = 4.5VIOL = 2.1 ma @ VCC = 2.5V

D6 ILI Input leakage current — ±1 μA VIN = VSS or VCC, WP = VSSVIN = VSS or VCC, WP = VCC

D7 ILO Output leakage current — ±1 μA VOUT = VSS or VCC

D8 CIN, COUT

Pin capacitance (all inputs/outputs)

— 10 pF VCC = 5.0V (Note)TA = 25°C, FCLK = 1 MHz

D9 ICC Read Operating current — 400 μA VCC = 5.5V, SCL = 400 kHzICC Write — 3 mA VCC = 5.5V

D10 ICCS Standby current — 1 μA TA = -40°C to +85°CSCL = SDA = VCC = 5.5VA0, A1, A2, WP = VSS

— 5 μA TA = -40°C to +125°CSCL = SDA = VCC = 5.5VA0, A1, A2, WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

DS21203P-page 2 © 2007 Microchip Technology Inc.

24AA256/24LC256/24FC256
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICSElectrical Characteristics:Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°CAutomotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C


1 FCLK Clock frequency ————

100400400

1000

kHz 1.7V ≤ VCC < 2.5V2.5V ≤ VCC ≤ 5.5V1.7V ≤ VCC < 2.5V 24FC2562.5V ≤ VCC ≤ 5.5V 24FC256

2 THIGH Clock high time 4000600600500

————

ns 1.7V ≤ VCC < 2.5V2.5V ≤ VCC ≤ 5.5V1.7V ≤ VCC < 2.5V 24FC2562.5V ≤ VCC ≤ 5.5V 24FC256

3 TLOW Clock low time 470013001300500

————


4 TR SDA and SCL rise time (Note 1)

———

1000300300

ns 1.7V ≤ VCC < 2.5V2.5V ≤ VCC ≤ 5.5V1.7V ≤ VCC ≤ 5.5V 24FC256

5 TF SDA and SCL fall time (Note 1)

——

300100

ns All except, 24FC2561.7V ≤ VCC ≤ 5.5V 24FC256

6 THD:STA Start condition hold time 4000600600250

————


7 TSU:STA Start condition setup time 4700600600250

————


8 THD:DAT Data input hold time 0 — ns (Note 2)9 TSU:DAT Data input setup time 250

100100

———


10 TSU:STO Stop condition setup time 4000600600250

————


11 TSU:WP WP setup time 4000600600

———


12 THD:WP WP hold time 470013001300

———


Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com.


24AA256/24LC256/24FC256

FIGURE 1-1: BUS TIMING DATA

13 TAA Output valid from clock (Note 2)

————

3500900900400

ns 1.7 V ≤ VCC < 2.5V2.5 V ≤ VCC ≤ 5.5V1.7V ≤ VCC < 2.5V 24FC2562.5 V ≤ VCC ≤ 5.5V 24FC256

14 TBUF Bus free time: Time the bus must be free before a new transmission can start

470013001300500

————


15 TOF Output fall time from VIHminimum to VIL maximumCB ≤ 100 pF

10 + 0.1CB 250250

ns All except, 24FC256 (Note 1)

16 TSP Input filter spike suppression(SDA and SCL pins)

— 50 ns All except, 24FC256 (Notes 1 and 3)

17 TWC Write cycle time (byte or page)

— 5 ms —

18 — Endurance 1,000,000 — cycles 25°C (Note 4)

AC CHARACTERISTICS (Continued)Electrical Characteristics:Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°CAutomotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C


Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com.

(unprotected)(protected)

SCL

SDAIN

SDAOUT

WP

5

7

6

16

3

2

8 9

13

D4 4

10

11 12

14


24AA256/24LC256/24FC256

2.0 PIN DESCRIPTIONSThe descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

2.1 A0, A1, A2 Chip Address InputsThe A0, A1 and A2 inputs are used by the 24XX256 formultiple device operations. The levels on these inputsare compared with the corresponding bits in the slaveaddress. The chip is selected if the compare is true.

For the MSOP package only, pins A0 and A1 are notconnected.

Up to eight devices (two for the MSOP package) maybe connected to the same bus by using different ChipSelect bit combinations. These inputs must beconnected to either VCC or VSS.

In most applications, the chip address inputs A0, A1and A2 are hard-wired to logic ‘0’ or logic ‘1’. Forapplications in which these pins are controlled by amicrocontroller or other programmable device, the chipaddress pins must be driven to logic ‘0’ or logic ‘1’before normal device operation can proceed.

2.2 Serial Data (SDA)This is a bidirectional pin used to transfer addressesand data into and out of the device. It is an open drainterminal. Therefore, the SDA bus requires a pull-upresistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for400 kHz and 1 MHz).

For normal data transfer, SDA is allowed to changeonly during SCL low. Changes during SCL high arereserved for indicating the Start and Stop conditions.

2.3 Serial Clock (SCL)This input is used to synchronize the data transfer toand from the device.

2.4 Write-Protect (WP)This pin must be connected to either VSS or VCC. If tiedto VSS, write operations are enabled. If tied to VCC,write operations are inhibited but read operations arenot affected.

3.0 FUNCTIONAL DESCRIPTIONThe 24XX256 supports a bidirectional 2-wire bus anddata transmission protocol. A device that sends dataonto the bus is defined as a transmitter and a devicereceiving data as a receiver. The bus must becontrolled by a master device which generates theSerial Clock (SCL), controls the bus access, andgenerates the Start and Stop conditions while the24XX256 works as a slave. Both master and slave canoperate as a transmitter or receiver, but the masterdevice determines which mode is activated.

Name 8-pinPDIP

8-pinSOIC

8-pinTSSOP

8-pinMSOP

8-pinDFN Function

A0 1 1 1 — 1 User Configurable Chip SelectA1 2 2 2 — 2 User Configurable Chip Select(NC) — — — 1, 2 — Not ConnectedA2 3 3 3 3 3 User Configurable Chip SelectVSS 4 4 4 4 4 GroundSDA 5 5 5 5 5 Serial DataSCL 6 6 6 6 6 Serial Clock(NC) — — — — — Not ConnectedWP 7 7 7 7 7 Write-Protect InputVCC 8 8 8 8 8 +1.7V to 5.5V (24AA256)

+2.5V to 5.5V (24LC256)+1.7V to 5.5V (24FC256)


24AA256/24LC256/24FC256

4.0 BUS CHARACTERISTICSThe following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have beendefined (Figure 4-1).

4.1 Bus Not Busy (A)Both data and clock lines remain high.

4.2 Start Data Transfer (B)A high-to-low transition of the SDA line while the clock(SCL) is high, determines a Start condition. Allcommands must be preceded by a Start condition.

4.3 Stop Data Transfer (C)A low-to-high transition of the SDA line, while the clock(SCL) is high, determines a Stop condition. Alloperations must end with a Stop condition.

4.4 Data Valid (D)The state of the data line represents valid data when,after a Start condition, the data line is stable for theduration of the high period of the clock signal.

The data on the line must be changed during the lowperiod of the clock signal. There is one bit of data perclock pulse.

Each data transfer is initiated with a Start condition andterminated with a Stop condition. The number of thedata bytes transferred between the Start and Stopconditions is determined by the master device.

4.5 AcknowledgeEach receiving device, when addressed, is obliged togenerate an Acknowledge signal after the reception ofeach byte. The master device must generate an extraclock pulse which is associated with this Acknowledgebit.

A device that acknowledges must pull down the SDAline during the acknowledge clock pulse in such a waythat the SDA line is stable low during the high period ofthe acknowledge related clock pulse. Of course, setupand hold times must be taken into account. Duringreads, a master must signal an end of data to the slaveby NOT generating an Acknowledge bit on the last bytethat has been clocked out of the slave. In this case, theslave (24XX256) will leave the data line high to enablethe master to generate the Stop condition.

Note: The 24XX256 does not generate anyAcknowledge bits if an internalprogramming cycle is in progress.


24AA256/24LC256/24FC256
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2: ACKNOWLEDGE TIMING

Address orAcknowledge

Valid

DataAllowed

to Change

StopCondition

StartCondition

SCL

SDA

(A) (B) (D) (D) (C) (A)

SCL 987654321 1 2 3

Transmitter must release the SDA line at this point,allowing the Receiver to pull the SDA line low toacknowledge the previous eight bits of data.

Receiver must release the SDA lineat this point so the Transmitter cancontinue sending data.

Data from transmitterSDA

AcknowledgeBit

Data from transmitter


24AA256/24LC256/24FC256

5.0 DEVICE ADDRESSINGA control byte is the first byte received following theStart condition from the master device (Figure 5-1).The control byte consists of a 4-bit control code. For the24XX256, this is set as ‘1010’ binary for read andwrite operations. The next three bits of the control byteare the Chip Select bits (A2, A1, A0). The Chip Selectbits allow the use of up to eight 24XX256 devices onthe same bus and are used to select which device isaccessed. The Chip Select bits in the control byte mustcorrespond to the logic levels on the corresponding A2,A1 and A0 pins for the device to respond. These bitsare, in effect, the three Most Significant bits of the wordaddress.

For the MSOP package, the A0 and A1 pins are notconnected. During device addressing, the A0 and A1Chip Select bits (Figures 5-1 and 5-2) should be set to‘0’. Only two 24XX256 MSOP packages can beconnected to the same bus.

The last bit of the control byte defines the operation tobe performed. When set to a one, a read operation isselected. When set to a zero, a write operation isselected. The next two bytes received define theaddress of the first data byte (Figure 5-2). Becauseonly A14…A0 are used, the upper address bits are a“don’t care.” The upper address bits are transferredfirst, followed by the Less Significant bits.

Following the Start condition, the 24XX256 monitorsthe SDA bus checking the device type identifier beingtransmitted. Upon receiving a ‘1010’ code andappropriate device select bits, the slave device outputsan Acknowledge signal on the SDA line. Depending onthe state of the R/W bit, the 24XX256 will select a reador write operation.

FIGURE 5-1: CONTROL BYTE FORMAT

5.1 Contiguous Addressing Across Multiple Devices

The Chip Select bits A2, A1 and A0 can be used toexpand the contiguous address space for up to 2 Mbitby adding up to eight 24XX256 devices on the samebus. In this case, software can use A0 of the controlbyte as address bit A15; A1 as address bit A16; and A2as address bit A17. It is not possible to sequentiallyread across device boundaries.

For the MSOP package, up to two 24XX256 devicescan be added for up to 512 Kbit of address space. Inthis case, software can use A2 of the control byte asaddress bit A17. Bits A0 (A15) and A1 (A16) of thecontrol byte must always be set to a logic ‘0’ for theMSOP.

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

1 0 1 0 A2 A1 A0S ACKR/W

Control CodeChip Select

Bits

Slave Address

Acknowledge BitStart Bit

Read/Write Bit

1 0 1 0 A2

A1

A0 R/W x A

11A10

A9

A7

A0

A8 • • • • • •A

12

Control Byte Address High Byte Address Low Byte

ControlCode

ChipSelect

Bits

x = “don’t care” bit

A13

A14


24AA256/24LC256/24FC256

6.0 WRITE OPERATIONS

6.1 Byte WriteFollowing the Start condition from the master, thecontrol code (four bits), the Chip Select (three bits) andthe R/W bit (which is a logic low) are clocked onto thebus by the master transmitter. This indicates to theaddressed slave receiver that the address high byte willfollow after it has generated an Acknowledge bit duringthe ninth clock cycle. Therefore, the next bytetransmitted by the master is the high-order byte of theword address and will be written into the AddressPointer of the 24XX256. The next byte is the LeastSignificant Address Byte. After receiving anotherAcknowledge signal from the 24XX256, the masterdevice will transmit the data word to be written into theaddressed memory location. The 24XX256 acknowl-edges again and the master generates a Stopcondition. This initiates the internal write cycle andduring this time, the 24XX256 will not generateAcknowledge signals (Figure 6-1). If an attempt ismade to write to the array with the WP pin held high, thedevice will acknowledge the command but no writecycle will occur, no data will be written, and the devicewill immediately accept a new command. After a byteWrite command, the internal address counter will pointto the address location following the one that was justwritten.

6.2 Page WriteThe write control byte, word address and the first databyte are transmitted to the 24XX256 in much the sameway as in a byte write. The exception is that instead ofgenerating a Stop condition, the master transmits up to63 additional bytes, which are temporarily stored in theon-chip page buffer, and will be written into memoryonce the master has transmitted a Stop condition.

Upon receipt of each word, the six lower AddressPointer bits are internally incremented by one. If themaster should transmit more than 64 bytes prior togenerating the Stop condition, the address counter willroll over and the previously received data will be over-written. As with the byte write operation, once the Stopcondition is received, an internal write cycle will begin(Figure 6-2). If an attempt is made to write to the arraywith the WP pin held high, the device will acknowledgethe command, but no write cycle will occur, no data willbe written and the device will immediately accept a newcommand.

6.3 Write-ProtectionThe WP pin allows the user to write-protect the entirearray (0000-7FFF) when the pin is tied to VCC. If tied toVSS the write protection is disabled. The WP pin issampled at the Stop bit for every Write command(Figure 1-1). Toggling the WP pin after the Stop bit willhave no effect on the execution of the write cycle.

FIGURE 6-1: BYTE WRITE

FIGURE 6-2: PAGE WRITE

Note: Page write operations are limited to writingbytes within a single physical page,regardless of the number of bytes actuallybeing written. Physical page boundariesstart at addresses that are integermultiples of the page buffer size (or ‘pagesize’) and end at addresses that areinteger multiples of [page size – 1]. If aPage Write command attempts to writeacross a physical page boundary, theresult is that the data wraps around to thebeginning of the current page (overwritingdata previously stored there), instead ofbeing written to the next page, as might beexpected. It is, therefore, necessary for theapplication software to prevent page writeoperations that would attempt to cross apage boundary.

x

Bus ActivityMaster

SDA Line

Bus Activity

START

ControlByte

AddressHigh Byte

AddressLow Byte Data

STOP

ACK

ACK

ACK

ACK


S 1 0 1 0 0A2

A1

A0 P

x

Bus ActivityMaster

SDA Line

Bus Activity

START

ControlByte

AddressHigh Byte

AddressLow Byte Data Byte 0

STOP

ACK

ACK

ACK

ACK

Data Byte 63

ACKx = “don’t care” bit

S 1 0 1 0 0A2

A1

A0 P


24AA256/24LC256/24FC256

7.0 ACKNOWLEDGE POLLINGSince the device will not acknowledge during a writecycle, this can be used to determine when the cycle iscomplete (This feature can be used to maximize busthroughput). Once the Stop condition for a Writecommand has been issued from the master, the deviceinitiates the internally timed write cycle. ACK pollingcan be initiated immediately. This involves the mastersending a Start condition, followed by the control bytefor a Write command (R/W = 0). If the device is stillbusy with the write cycle, then no ACK will be returned.If no ACK is returned, the Start bit and control byte mustbe resent. If the cycle is complete, then the device willreturn the ACK and the master can then proceed withthe next Read or Write command. See Figure 7-1 forflow diagram.

FIGURE 7-1: ACKNOWLEDGE POLLING FLOW

SendWrite Command

Send StopCondition to

Initiate Write Cycle

Send Start

Send Control Bytewith R/W = 0

Did DeviceAcknowledge

(ACK = 0)?

NextOperation

NO

YES


24AA256/24LC256/24FC256

8.0 READ OPERATIONRead operations are initiated in much the same way aswrite operations, with the exception that the R/W bit ofthe control byte is set to ‘1’. There are three basic typesof read operations: current address read, random readand sequential read.

8.1 Current Address ReadThe 24XX256 contains an address counter that main-tains the address of the last word accessed, internallyincremented by ‘1’. Therefore, if the previous readaccess was to address ‘n’ (n is any legal address), thenext current address read operation would access datafrom address n + 1.

Upon receipt of the control byte with R/W bit set to ‘1’,the 24XX256 issues an acknowledge and transmits the8-bit data word. The master will not acknowledge thetransfer, but does generate a Stop condition and the24XX256 discontinues transmission (Figure 8-1).

FIGURE 8-1: CURRENT ADDRESS READ

8.2 Random ReadRandom read operations allow the master to accessany memory location in a random manner. To performthis type of read operation, the word address must firstbe set. This is done by sending the word address to the24XX256 as part of a write operation (R/W bit set to‘0’). Once the word address is sent, the master gener-ates a Start condition following the acknowledge. Thisterminates the write operation, but not before theinternal Address Pointer is set. The master then issuesthe control byte again, but with the R/W bit set to a one.The 24XX256 will then issue an acknowledge andtransmit the 8-bit data word. The master will notacknowledge the transfer, though it does generate aStop condition, which causes the 24XX256 to discon-tinue transmission (Figure 8-2). After a random Readcommand, the internal address counter will point to theaddress location following the one that was just read.

8.3 Sequential ReadSequential reads are initiated in the same way as arandom read except that after the 24XX256 transmitsthe first data byte, the master issues an acknowledgeas opposed to the Stop condition used in a randomread. This acknowledge directs the 24XX256 totransmit the next sequentially addressed 8-bit word(Figure 8-3). Following the final byte transmitted to themaster, the master will NOT generate an acknowledge,but will generate a Stop condition. To provide sequen-tial reads, the 24XX256 contains an internal AddressPointer which is incremented by one at the completionof each operation. This Address Pointer allows theentire memory contents to be serially read during oneoperation. The internal Address Pointer willautomatically roll over from address 7FFF to address0000 if the master acknowledges the byte receivedfrom the array address 7FFF.

FIGURE 8-2: RANDOM READ

FIGURE 8-3: SEQUENTIAL READ

Bus ActivityMaster

SDA Line

Bus Activity

PS

STOP

ControlByte

START

Data

ACK

NOACK

1 10 0 A A A 1

Byte

2 1 0

x

Bus Activity Master

SDA Line

Bus ActivityACK

NOACK

ACK

ACK

ACK

STOP

START

ControlByte

AddressHigh Byte

AddressLow Byte

ControlByte

DataByte

START


S 1 0 1 0 A A A 02 1 0 S 1 0 1 0 A A A 12 1 0 P

Bus ActivityMaster

SDA Line

Bus Activity

ControlByte Data (n) Data (n + 1) Data (n + 2) Data (n + x)

NOACK

ACK

ACK

ACK

ACK

STOP

P


24AA256/24LC256/24FC256

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXXT/XXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (150 mil) Example:

XXXXXXXTXXXXYYWW

NNN

8-Lead SOIC (208 mil) Example:

24LC256

0510017I/SM

24AA256I/P 017

0510

XXXXXXXX

YYWWNNNT/XXXXXX

24LC256ISN 0510

017

3e

3e

3e

*Standard device marking consists of Microchip part number, year code, week code, and traceability code. Fordevice marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.

Legend: XX...X Part number or part number codeT Temperature (I, E)Y Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator , the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e


24AA256/24LC256/24FC256
Package Marking Information (Continued)
8-Lead MSOP Example:

XXXXXTYWWNNN

4L256I510017

8-Lead DFN-S Example:

XXXXXXXT/XXXXXYYWW

24LC256I/MF

0510017NNN

First Line Marking CodesPart No. TSSOP Package Codes MSOP Package Codes

24AA256 4AD 4A256T24LC256 4LD 4L256T24FC256 4FD 4F256T

8-Lead TSSOP Example:

XXXXTYWWNNN

4LDI510017

3e


24AA256/24LC256/24FC256

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APPENDIX A: REVISION HISTORY

Revision LCorrections to Section 1.0, Electrical Characteristics.

Revision MAdded 1.8V 400 kHz option for 24FC256.

Revision NRevised Sections 2.1 and 2.4. Removed 14-LeadTSSOP Package.

Revision PRevised Features; Changed 1.8V voltage to 1.7V;Replaced Package Drawings; Revised markings (8-leadSOIC); Revised Product ID System.


24AA256/24LC256/24FC256


24AA256/24LC256/24FC256

THE MICROCHIP WEB SITEMicrochip provides online support via our WWW site atwww.microchip.com. This web site is used as a meansto make files and information easily available tocustomers. Accessible by using your favorite Internetbrowser, the web site contains the followinginformation:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICEMicrochip’s customer notification service helps keepcustomers current on Microchip products. Subscriberswill receive e-mail notification whenever there arechanges, updates, revisions or errata related to aspecified product family or development tool of interest.

To register, access the Microchip web site atwww.microchip.com, click on Customer ChangeNotification and follow the registration instructions.

CUSTOMER SUPPORTUsers of Microchip products can receive assistancethrough several channels:

• Distributor or Representative• Local Sales Office• Field Application Engineer (FAE)• Technical Support• Development Systems Information Line

Customers should contact their distributor,representative or field application engineer (FAE) forsupport. Local sales offices are also available to helpcustomers. A listing of sales offices and locations isincluded in the back of this document.

Technical support is available through the web siteat: http://support.microchip.com


24AA256/24LC256/24FC256

READER RESPONSEIt is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentationcan better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader ResponseTotal Pages Sent ________

From: Name

CompanyAddressCity / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21203P24AA256/24LC256/24FC256

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?


24AA256/24LC256/24FC256

PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX

PackageTemperatureRange

Device

Device: 24AA256: 256 Kbit 1.8V I2C Serial EEPROM

24AA256T: 256 Kbit 1.8V I2C Serial EEPROM Tape and Reel)

24LC256: 256 Kbit 2.5V I2C Serial EEPROM

24LC256T: 256 Kbit 2.5V I2C Serial EEPROM Tape and Reel)

24FC256: 256 Kbit High Speed I2C Serial EEPROM

24FC256T: 256 Kbit High Speed I2C Serial EEPROM Tape and Reel)

Temperature Range:

I = -40°C to +85°CE = -40°C to +125°C

Package: P = Plastic DIP (300 mil body), 8-leadSN = Plastic SOIC (3.90 mm body), 8-leadSM = Plastic SOIJ (5.28 mm body), 8-leadST = Plastic TSSOP (4.4 mm), 8-leadMF = Dual, Flat, No Lead (DFN)(6x5 mm

body), 8-leadMS = Plastic Micro Small Outline (MSOP),

8-lead

Examples:a) 24AA256-I/P: Industrial Temp.,

1.7V, PDIP package.b) 24AA256T-I/SN: Tape and Reel,

Industrial Temp., 1.7V, SOIC package.

c) 24AA256-I/ST: Industrial Temp., 1.7V, TSSOP package.

d) 24AA256-I/MS: Industrial Temp., 1.7V, MSOP package.

e) 24LC256-E/P: Extended Temp., 2.5V, PDIP package.

f) 24LC256-I/SN: Industrial Temp., 2.5V, SOIC package.

g) 24LC256T-I/SN: Tape and Reel, Industrial Temp., 2.5V, SOIC package.

h) 24LC256-I/MS: Industrial Temp, 2.5V, MSOP package.

i) 24FC256-I/P: Industrial Temp, 1.7V, High Speed, PDIP package.

j) 24FC256-I/SN: Industrial Temp, 1.7V, High Speed, SOIC package.

k) 24FC256T-I/SN: Tape and Reel, Industrial Temp, 1.7V, High Speed, SOIC package


24AA256/24LC256/24FC256
NOTES:

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

© 2007 Microchip Technology Inc.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

DS21203P-page 25

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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