2.7-16.modeling and simulation on subthreshold …orar.upit.ro/docmanagerpub/file/buletin nr9...

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ISSN – 1453 – 1119

MODELING AND SIMULATION ON SUBTHRESHOLD CONDUCTION OF THE MOS-FET

Emil SOFRON

University of Pitesti, Department of Electronics and Computers [email protected]

Keywords: subthreshold conduction, modeling and simulation, MOS capacitor, SPICE models.

Abstract. For the MOS-FET devices, in the subthreshold conduction, the drain current is obtained only by diffusion the carriers of charge. The subthreshold conduction for the MOS-FET devices to refers at the operation in current domain about units of pA÷nA. The results obtained by modeling and by simulation of the subthreshold conduction to illustrate a exponential form for transfer characteristics of the MOS-FET devices.

1. Introduction

In this paper to presents analysis and

simulation of the subthreshold conduction for the MOS-FET devices (fig. 1 a and b). Technology for the MOS-FET with the subthreshold conduction has been recognized as most suitable for implementation of intelligent electronic structures and dynamic circuits [1, 2, 3] which offers: low power dissipation; useful parasitic bipolar devices and high integration density. In this analysis, a basic assumption is that weak inversion layer charge exists below the threshold

voltage and the subthreshold current is not zero [4, 5, 6].

From Gauss law for a MOS capacitor, with oxoxox xC /ε= - specifically capacity of oxide (/unity of surface) under the gate,

( )[ ]thBSdepinv V2CC /exp Φ−Φ⋅≅ - the specifically

capacity of inversion layer (/unity of surface, where ( )

Siinvs QEsthinv EVx ε// == is width of the

inversion-layer under the oxide), ( ) oxinvoxinvoxeffox CCCCCC ≈+⋅= /, - effective

oxide capacity under the gate and

Fig. 1 – a/ The structure for a MOS capacitor in MOS-FET (S – source, D – drain, G – gate

and B – background or substrate). b/ The model of equivalent circuit for a MOS capacitor with Cinv >> Cdep.

8 UNIVERSITY OF PITESTI – ELECTRONICS AND COMPUTERS SCIENCE, SCIENTIFIC BULLETIN, No. 9, Vol.2, 2009

ISSN – 1453 – 1119

( ) ( ) invSDASidep C2NqC <<Φ⋅⋅= /ε - the

specifically capacity of depletion layer (/unity of surface) in the semiconductor substrate which form a capacitive divider, the voltage GSV and the variation of gate voltage GV∆ to calculate with the relations:

≅∆ →+Φ+= ∆≈∆G

VV

ox

invSFBGS V

C

QVV GGS

+∆Φ≅

ox

deps C

C1 where FBV is the flat-band

voltage,

( ) ( ) ≈Φ⋅Φ⋅⋅⋅⋅= thSSDASiinv VNqQ /exp2 ε

( ) SDASi Nq Φ⋅⋅⋅⋅≈ ε2 for thS V<<Φ - the

specifically charge by inversion layer, oxx -

oxide thickness (SiO2), 0V

FBGSS k

VV Φ−−≈Φ - the

surface potential of used semiconductor,

+≅

∆Φ∆≈

Φ=

ox

dep

s

G

s

GSV C

C1

V

d

dVk - the subthreshold

voltage swing coefficient for BS 2Φ≅Φ at strong-inversion, ( )( )iDAthB nNV /ln⋅=Φ - the

volume potential at a MOS capacitor and

≈Φ →+

Φ≈Φ Φ≅Φ0

20

BS

depox

depS CC

C

depox

depB CC

C

+Φ≈ 2 - one potential obtained by

capacitive division with . oxC and depC .

For a good operation of the CMOS circuits at room temperature, the subthreshold conduction ( ( ) ( )LWQDI invpnsubthD /, ⋅⋅= ), where

( )pnD is the diffusion constant for used

semiconductor (with the AN or DN concentrations on substrate), W - the depth of

the conduction channel and L - length of conduction channel) is the most important limiting at low-voltage or at low-power.

2. Modeling on subthreshold

conduction of the MOS-FET

For MOS-FET devices with induced-channel and with a strong-inversion region, the threshold voltage (TV ) to calculate such:

−−Φ+Φ+= BSSSFBT VKVV 1

DSBSS VVK ⋅−−Φ− η2 where 1K is body-

effect coefficient, 2K - non-uniform channel doping coefficient and η - drain-induced barrier-lowering coefficient.

At modeling of the MOS-FET devices with induced-channel to assumption the following physics process: subthreshold conduction [7], channel length modulation, non-uniform channel doping, drain-induced barrier lowering, carrier velocity saturation, mobility reduction due to the vertical electric field, source/drain charge sharing, source/drain parasitic resistance, hot-electron-induced output resistance reduction, inversion-layer capacitance.

In the subthreshold conduction at MOS-FET (for TGS VV < ), dominated only by the diffusion of electrons (in the case at n-channel MOS-FET) or of holes (in the case at p-channel MOS-FET) in the region with weak-inversion under gate ( BS 2Φ<Φ ), where there is a barrier between the source and the drain, the subthreshold drain current (in a long-channel MOS-FET with 0VDS ≥ for n-MOS-FET and with 0VDS ≤ for p-MOS-FET) to calculate such:

( ) ( )( )( ) ( ) ( )

( )( )( ) ( )( )

( )( )( ) ( )( )

( )( )

( )( )

( )

( )( )

( )( )

444444444444 3444444444444 214444 34444 21

thVDSVB2x

0nthV

B2x

0n

dS

thVDSVB2x

0pthV

B2x

0peff

invcB

thpnthpnpn

epLpep0p

x

x1xenLnen0nLL

eff

pnpnpnc

eff

pnpnpnc

xZAq

TkVVDp

nC

pnpncsubth

diffD L

LC0CDAq

L

0CLCDAqyCDAqI

−Φ−ΦΦ−Φ

−Φ−ΦΦ−Φ

⋅=⋅=

−Φ=Φ⋅=⋅=⋅=

⋅=⋅=⋅==

−⋅⋅=

−⋅⋅−=∇⋅⋅−=

,

,,,

,,,

,

λ

µ

EMIL SOFRON Modeling and Simulation on Subthreshold Conduction of The MOS-FET 9

ISSN – 1453 – 1119

( ) ( ) ( )

( ) ( ) ( )

−−

−⋅⋅⋅⋅⋅

Φ⋅⋅⋅⋅⋅⋅⋅⋅=−⋅⋅

−−

−⋅⋅⋅⋅⋅

Φ⋅⋅⋅⋅⋅⋅⋅⋅=−⋅⋅

=−

Φ−Φ

−Φ−Φ

FETMOSpfore1eL

p

q

Tk

Nq2q

TkZq

L

Lp0pDAq

FETMOSnfore1eL

n

q

Tk

Nq2q

TkZq

L

Ln0nDAq

th

DS

th

B

th

DS

th

B

V

V

V

2x

eff

0np

B

SDSi

SiB

effpc

V

V

V

2x

eff

0pn

B

SASi

SiB

effnc

µεε

µε

ε

where ( )pnD is diffusion constant for electrons

(/holes), ( )pnµ - mobility for electrons (/holes),

( )pnC - the concentration of electrons or of

holes in the conduction-channel, thV - the thermal voltage, Bk - the Boltzmann constant, q - of electron charge, T - ambient temperature, Z - depth of conduction channel,

cA - the area cross-section of conduction channel, effL - effective length of conduction

channel, ( )DAN - acceptors (/donors) atoms

concentration in the semiconductor substrate,

( )( )DASSid Nq2x ⋅Φ⋅⋅= /ε - depletion depth in

the semiconductor substrate, Siε - the permittivity for Si, in - intrinsic concentration of carriers in the semiconductor substrate,

( )0yn = or ( )0yp = and ( )Lyn = or ( )Lyp = - the concentration of electrons or of holes in inversion-layer at the source (S: y=0) and at the drain (D: y=L) respectively.

To see that the subthreshold current contains two main components:

=≈+⋅

≅ explimexp

limexpI

II

III subth

D

−⋅⋅=

−⋅⋅ ∗

th

DS

th

BS

thV

GS

V

V

V

V

Vk

V

eeeI 10η

where:

−⋅⋅≈

−⋅⋅ ∗

th

DS

th

BS

thV

GS

V

V

V

V

Vk

V

0 e1eeII ηexp is the

current in subthreshold region, 2

II 0=lim - the

current used to limit subthDI in the strong-

inversion region, 0I - the subthreshold current in absence the voltages of bias,

0GS10 V ηηηη ≈⋅+=∗ - the substrate voltage swing coefficient (with 01 ≈η by ignoring the

dependence of η on GSV ), To see that the subthreshold current depends heavily on the surface potential ss ∆Φ±Φ . For the TV voltage offset in the subthreshold region ( DSDoffsetBSBoffset0offsetoffset VVVVVV ⋅+⋅+= ,,, ), the

subthreshold current to calculate with the relation:

−⋅=

−⋅+−

th

DS

thV

offsetTGS

V

V

Vk

VVV

0subth

offsetD e1eII ,

where 0offsetV , is value of offsetV extracted at

0VBS = and 0VDS = , BoffsetV , - sensitivity of

offsetV to BSV and DoffsetV , - sensitivity of offsetV

to DSV . The main SPICE n(p)-MOS-FET model parameters [8, 9] to illustrate in Table 1, at which to addition the SPICE n(p)-MOS-FET model parameters for parasitic elements (resistances and capacitances – in Table 2) and the SPICE MOS-FET model parameters for geometric elements (in Table 3).

3. Results obtained by simulation on subthreshold conduction of the MOS-FET In this section to illustrate the subthreshold conduction (by ( )

BSDS VVGSD VI , characteristics)

at n(p)-MOS-FET devices by simulation, using the following SPICE MOS-FET models: mod1 (with the parameters marked by * - in Table 1,2,3) for one NMOS transistor (Fig. 2); mod2 (with the parameters marked by * - in Table 1,2,3) for one PMOS transistor (Fig. 3); modn1 (with the parameters marked by * and by ** - in Table 1,2,3) for one NMOS transistor (Fig. 4); modp1 (with the parameters marked by * and by ** - in Table 1,2,3) for one PMOS transistor (Fig. 5).


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Table 1 – Main SPICE MOS-FET model parameters.

Parameter Name Symbol SPICE Name Units Default Value SPICE Model Index * - LEVEL - 1 Zero-Bias Threshold Voltage * VT0 VT0 V 0 Transconductance Parameter * k’ KP A/V2 2e-5 Body-Bias Parameter * γ GAMMA V 1/2 0 Channel Modulation * λ=0.1/L LAMBDA 1/V 0 Surface Inversion Potential * 2ΦF PHI V 0.6 Emission Coefficient ** - N - 1 Substrate Doping ** N A(D) NSUB cm-3 0 Type of Gate Material ** - TPG - 1 Transit time ** Tt TT s 0 Surface Mobility * µ0 U0 cm2/V .s 600 Maximum Drift Velocity ** vmax VMAX m/s 0 Bulk Junction Grading Ceofficient * m MJ - 0.5 Bulk Junction Leakage Current * Is IS A 0 Bulk Junction Leakage Current Density ** Js JS A/m2 1.0e-8 Bulk Junction Potential * Φ0 PB V 0.8 Side-Wall Grading Coefficient ** msw MJSW - 0.3 Cofficient for FBD Capacitance ** Fc FC - 0.5 Output Feedback Parameter ** ∆ DELTA 1/(A.V) 0 Mobility Reduction Coefficient ** θ THETA 1/V 0 Body Bias Coefficient in Subthreshold Region (η0) ** η(η0,ηB) ETA (-, 1/V) (0.08, -0.07) Coefficient for Electric Field in Saturation Mode * k KAPPA 0.2 Note. FBD (Forward-Bias Depletion). ηB- Body Bias Coefficient in Subthreshold Region. Table 2 – SPICE MOS-FET model parameters for parasitic elements (resistances and capacitances).

Parameter Name Symbol SPICE Name Units Default Value Parasitic Source Resistance * RS RS Ω 0 Parasitic Drain Resistance * RD RD Ω 0 Sheet Resistance (Source/Drain) ** R RSH Ω / 0 Zero-Bias Bulk Junction Capacitance Cj0 CJ F/m2 0 Zero-Bias Side-Wall Junction Capacitance Cjsw0 CJSW F/m 0 Gate-Bulk Overlap Capacitance Cgb0 CGB0 F/m 0 Gate-Source Overlap Capacitance * Cgs0 CGS0 F/m 0 Gate-Drain Overlap Capacitance * Cgd0 CGD0 F/m 0 Bulk -Drain Capacitance * Cbd CBD F 0 Table 3 – SPICE MOS-FET model parameters for geometric elements.

Parameter Name Symbol SPICE Name Units Default Value Drawn Length * L L m - Effective Width * W W m - Source Perimeter * Perim PS m 0 Drain Perimeter * Perim PD m 0 Bulk-Side-Wall Perimeter * Perim PBSW m 0 Oxide Thickness * tox TOX m 1.0e-7 Lateral Diffusion ** xd LD m 0 Metallurgical Junction Depth * xj XJ m 0 Channel Width Reduction on One Side ** ∆W DW m 0


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Fig. 2 – The SPICE model mod1 parameters for one NMOS transistor.

Fig. 3 – The SPICE model mod2 parameters for one PMOS transistor.

Fig. 4 – The SPICE model modn1 parameters for other NMOS transistor.

Fig. 5 – The SPICE model modp1 parameters for other PMOS transistor.

The simulated subthreshold ( )BSVGSD VI

characteristics of n(p)-MOS-FET devices are shown in Fig. 6 (for mod1 with tox=100n, W=5u and L=5u), Fig. 7 (for mod1 with tox=100n, W=5u and L=10u), Fig. 8 (for mod1 with tox=100n, W=1u and L=5u), Fig. 9 (for modn1 with tox=100n, W=5u and L=5u), Fig. 10 (for modn1 with tox=1n, W=5u and

L=5u), Fig. 11 (for mod2 with tox=100n, W=5u and L=5u), Fig. 12 (for mod2 with tox=100n, W=5u and L=10u), Fig. 13 (for mod2 with tox=100n, W=1u and L=5u), Fig. 14 (for modp1 with tox=100n, W=5u and L=5u), Fig. 15 (for modp1 with tox=1n, W=5u and L=5u).

model mod1 NMOS(Level=3 Gamma=3.1 Kappa=0.7 Xj=0.1 Tox=10n Uo=15 Phi=.75 Rs=.1207 Kp=21.35u W=1u L=1u Vto=0.5 Rd=64.68m Cbd=1.273n Pb=.1 Pbsw=.1 Mj=.46 Fc=.5 Cgso=729.7p Cgdo=310.4p Rg=5.839 Is=50f N=1 Tt=370n Lambda=3.9u)

model mod2 PMOS(Level=3 Gamma=3.1 Kappa=0.7 Xj=0.1 Tox=100n Uo=15 Phi=.75 Rs=.1207 Kp=21.35u W=1u L=5u Vto=-0.5 Rd=64.68m Cbd=1.273n Pb=.7 Pbsw=.1 Mj=.46 Fc=.5 Cgso=729.7p Cgdo=310.4p Rg=5.839 Is=50f N=1 Tt=370n Lambda=3.9u tpg=-1)

model modn1 NMOS(Level=3 Gamma=3.1 Kappa=0.8 Vmax=2.5e+05 ld=2.2e-07 dw=-1.2e-07 tpg=1 js=2.5e-03 Xj=2.6e-07 nsub=1.4e+16 rsh=171 mjsw=0.28 delta=1.6 eta=2.1e-02 theta=4.5e-02 nfs=5.4e+11 Tox=1n Uo=526 Phi=.75 Kp=21.35u W=5u L=5u Vto=0.67 Cbd=1.273n Pb=.7 Pbsw=.1 Mj=.35 Fc=.5 Cgso=2.9e-10 Cgdo=2.9e-10 Is=5f N=1 Tt=370n Lambda=3.9u tpg=1)

model modp1 PMOS(Level=3 Gamma=3.1 Kappa=0.8 Vmax=2.5e+05 ld=2.2e-07 dw=-1.2e-07 tpg=-1 js=2.5e-03 Xj=2.6e-07 nsub=1.4e+16 rsh=171 mjsw=0.28 delta=1.6 eta=2.1e-02 theta=4.5e-02 nfs=5.4e+11 Tox=1n Uo=200 Phi=.75 Kp=21.35u W=5u L=5u Vto=-0.67 Cbd=1.273n Pb=.7 Pbsw=.1 Mj=.35 Fc=.5 Cgso=2.9e-10 Cgdo=2.9e-10 Is=5f N=1 Tt=370n Lambda=3.9u tpg=-1)


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Fig. 6 - The simulated n-channel MOS-FET subthreshold ( ) 0VVGSD BSDS

VI <, characteristics for

W/L= 5 µm/5 µm, tox = 100 nm and the associated low signal model (mod1). The background-source voltage VBS is a parameter ranging from 0 to -0.2 V in steps of -0.05 V.








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W/L= 5 µm/5 µm, tox = 100 nm and other the associated low signal model (modn1). The background-source voltage VBS is a parameter ranging from 0 to -0.2 V in steps of -0.05 V.



W/L= 5 µm/5 µm, tox = 1 nm and other the associated low signal model (modn1). The background-source voltage VBS is a parameter ranging from 0 to -0.2 V in steps of -0.05 V.

Fig. 11 - The simulated p-channel MOS-FET subthreshold ( ) 0VVGSD BSDS

VI >, characteristics for

W/L= 5 µm/5 µm, tox = 100 nm and the associated low signal model (mod2). The background-source voltage VBS is a parameter ranging from 0 to 0.2 V in steps of 0.05 V.


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W/L= 5 µm/5 µm, tox = 100 nm and other the associated low signal model (modp1). The background-source voltage VBS is a parameter ranging from 0 to 0.2 V in steps of 0.05 V.


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Fig. 15 - The simulated p-channel MOS-FET subthreshold ( ) 0VVGSD BSDSVI >,

characteristics for

W/L= 5 µm/5 µm, tox = 1 nm and other the associated low signal model (modp1). The background-source voltage VBS is a parameter ranging from 0 to 0.2 V in steps of 0.05 V.

4. Conclusions

For a MOS-FET device in the subthreshold conduction (that is in the weak inversion and in depletion regions), the SΦ potential is linearly proportional with TGS VV < .

The short channel effect to illustrate by drain-induced barrier lowering, by threshold voltage shift and by increasing the inverse of the slope (named the S-parameter) associated the ( )

BSDS VVGSD VI,

lg

characteristics. From the simulated

( )BSDS VVGSD VI

,characteristics, for the

subthreshold conduction, we see that used models are strong-sensitive at the variation of values for tox, W, L and VBS.

With used models, between the subthreshold region and the strong-inversion region to obtain a transition region in which to alter the form for

( )BSDS VVGSD VI

, characteristics.

References [1]. TH. F. BOGART, JR. Electronic Devices

and Circuits, Second Edition. Merrill Publishing Company, A Bell & Howell Information Company, Columbus, Ohio, London, Toronto, Melbourne, 1990.

[2]. N. WESTE, K. ESHRAGIAN. Principles of CMOS VLSI Design - A System Perspective, Addison-Wesley Publishing Company, 1993.

[3]. N. G. Tarr, D. J. Walkey, M. B. Rowlandson, S. B. Hewitt and T. W. MacElwee. Short-channel effects on MOSFET subthreshold swing. Solid-State Electronics, vol. 38, no. 3, March 1995, pp. 697-701.

[4]. W. QIAN, X. ZHOU, Y. WANG AND K.Y. LIM. A Velocity-Overshoot Subthreshold Current Model for Deep-Submicrometer MOSFET Devices,Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems. Nanyang Technological University, Singapore, pp. 396 – 399.

[5]. P. R. GRAY, P. J. HURST, ST. H. LEVLS, R. G. MEYER. Analysis and Design of Analog Integrated Circuits, Fourth Edition, John Wiley & Sons Inc., New York, Chichester, Weinheim, Brisbane, Singapore, Toronto, 2001.


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[6]. KIM JAE-JOON, K. ROY. Double gate-MOSFET subthreshold circuit for ultralow power applications, IEEE Trans. Electron Devices, vol. 51, no. 9, September 2004, pp 1468-1474.

[7]. A. MIZUMURA, T. OHISHI, N. YOKOYAMA, M. NONAKA, S. TANAKA, H. AMMO. A study of 90 nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure, Semiconductor Technology, Dev. Group, Sony Corp., Kanagawa, Japan, Microelectronic Test Structures, ICMTS 2005, Proceedings of the 2005 International Conference, 4-7 April 2005, pp. 39-42.

[8]. MOHAMMAD MAHDI KHAFAJI, MAHMOUD KAMAREI AND BEHJAT FOROUZANDEH. Modified analytical model for subthreshold current in short channel MOSFET's, IEICE Electronics Express, vol. 4 (2007), no. 3, pp.114-120.

[9]. RISHU CHAUJAR, RAVNEET KAUR, MANOJ SAXENA, MRIDULA GUPTA, R S GUPTA. Two-dimensional analytical sub-threshold model of multi-layered gate dielectric recessed channel (MLaG-RC) nanoscale MOSFET. University of Delhi, Karampura, New Delhi, India. Semicond. Sci. Technol. vol. 23, 2008.

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