27 memory controllers
TRANSCRIPT
Memory Controllers 1
Memory Controllers
Memory Controllers 2
Motivation• Many memory controllers have as features:
– Multiple ports– Single port memory devices– SRAM, DRAM, or SDRAM or technology
• Have seen failures in multiple flight systems– Circuit design errors– Risky, complex architectural decisions
Memory Controllers 3
SRAM Technology Overview
Background
Memory Controllers 4
Some SDRAM Features
• Synchronous Timing– Signal generation much simpler than DRAM
• Complex devices with state machines, pipelines, refresh modes, power states, etc.
• Like DRAM, startup sequence required
Memory Controllers 5
Block DiagramMicron, 64 Mbit
4 Banks
Control SignalsSampled
Synchronously
ModeRegister
Memory Controllers 6
Block DiagramMicron, 64 MbitControl Signals
SampledSynchronously
ModeRegister
CKECLK
CS*WE*CAS*RAS*
Memory Controllers 7
Control Signal Interpretation
Function CS* RAS* CAS* WE*
COMMAND INHIBIT H X X XNOP H X X X
LOAD MODE REGISTER L L L LAUTO/SELF REFRESH L L L HPRECHARGE L L H LACTIVE (SEL BANK/ROW) L L H HWRITE L H L LREAD L H L HBURST TERMINATE L H H L
Memory Controllers 8
Example Read w/ Auto PrechargeCAS Latency=2; Burst Length=4
Memory Controllers 9
Load Mode Register CommandAddress Used As Operation Code
A2:A0 Burst Length
A3 Burst Type {Sequential, Interleaved}
A6:A4 CAS Latency
A8:A7 Operation Mode
A9 Write Burst Mode
A11:A10 Reserved
Memory Controllers 10
Load Mode Register CommandExamination of Some Fields - Burst Length
BURST LENGTHA2 A1 A0 M3=0 M3=1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 RESERVED RESERVED 1 0 1 RESERVED RESERVED 1 1 0 RESERVED RESERVED 1 1 1 FULL PAGE RESERVED
Memory Controllers 11
Load Mode Register CommandExamination of Some Fields - CAS Latency
A6 A5 A4 CAS LATENCY 0 0 0 RESERVED 0 0 1 RESERVED 0 1 0 2 0 1 1 3 1 0 0 RESERVED 1 0 1 RESERVED 1 1 0 RESERVED 1 1 1 RESERVED
Memory Controllers 12
Load Mode Register CommandExamination of Some Fields - Op Mode
A8 A7 Operation Mode
0 0 Standard Operation 0 1 RESERVED 1 0 RESERVED 1 1 RESERVED
Memory Controllers 13
State Diagram, Simplified [3]Hitachi 256M SDRAM
PowerOn
Pre-charge
LoadModeReg
Idle
SelfRefresh
AutoRefresh
IdlePowerDownRead/
Write
Lockup states?
Memory Controllers 14
Mode Register and Device StateSpecial Considerations
• Mode Register likely SEU Soft– Test data supports this
• RESERVED states in Mode Register– May be able to load invalid state– May require power cycle– May result in damage to device
• Toggling N/C Pins– May require power cycle to recover– May result in damage to device
• Poor Signal Integrity or Power/Ground Noise– May upset Mode Register: put into a RESERVED state
Memory Controllers 15
What Happens with Heavy Ions?
Memory Controllers 16
Heavy Ion SEUs, 128 Mbit Samsung [2]
KM44S32030B
LET (MeV-cm2/mg)
Cro
ss-s
ectio
n (c
m2 /d
evic
e)
SEE Event SEL
Memory Controllers 17
Heavy Ion SEUs, 256 Mbit [2]
• Samsung– Multiple bit upsets seen– LETTH is around 1 MeV-cm2/mg
• Hitachi– Multiple bit upsets seen– LETTH is around 1 MeV-cm2/mg
Memory Controllers 18
Heavy Ion: Stuck Bits• Reference [1] reports 30 stuck bits on one
128 Mb device, after exposure to a large fluence. Fewer stuck bits observed after being annealed at room temperature, unbiased for one week.
• Reference [2] reports stuck bits for the 256M Samsung devices. The small number of stuck bits annealed within a few weeks in an unbiased condition.
Memory Controllers 19
Loss of Functionalityand other
Unusual Events
RadiationSignal Integrity
Memory Controllers 20
“Large Event” - Samsung [1]
Most or all bits “wrong” were seen a few times for the 128 Mbit Samsung device; it was not seen for the 64 Mbit Samsung SDRAM.
Memory Controllers 21
Loss of Functionality - Early Data• 256M Samsung [2]
– “Often, ‘reset’ (power cycle) is needed to recover from SEFI conditions.” [2]
– Large multiple bit errors (> 100 bits) making an oval patch in the memory
– Multiple-bit errors over many consecutive address locations– Events above may have an increase of about 10 mA in
supply current.• 256 Hitachi [2]
– Also seen. – Anomalous Currents– Ranged from 0.5 to 145 mA [3]
Memory Controllers 22
Loss of Functionality [3]Hyundai 256M (Auto Refresh Operation)
LET (MeV-cm2/mg)
Cro
ss-s
ectio
n (c
m2 /d
evic
e)
10-3
10-4
10-5
10-6
10-7
Memory Controllers 23
Loss of FunctionalityAdditional Issues
• Refreshing MODE Register– Will restore functionality in some cases– But not all!
• Different ways of operating SDRAM can result in different affects from radiation. See Reference [3] for details.
Memory Controllers 24
Loss of Functionality - A SampleSee Ref. 3 for Detailed Data
Self-Refresh Operation: Power Cycle Required
LET HIT256M HYND256M SAM128M SAM256M
4.1 - N/A - N/A12 X N/A X X28 X X X X
- No problemN/A Data Not AvailableX Power Cycle Required
Memory Controllers 25
Design FSM Controllers
Memory Controllers 26
Data Flow
SDRAM
ProducerProcess
ConsumerProcess
Memory Controllers 27
One Flight Hardware ApproachControl Signals Shown
SDRAM
ProducerFSM
ConsumerFSM
Arbitration
OR Gate
FPGA
Arbitration between the FSMs complex, a small error was made, resulting in putting the SDRAM in an illegal state, potentially damaging it, and locking up the entire system.
Memory Controllers 28
Another Flight Hardware DesignControl Signals Shown
SRAM
ProducerFSM
ConsumerFSM
Arbitration
Tri-State Mux
Arbitration between the FSMs complex, a small error was made, resulting in putting glitches into the SRAM, destroying the contents, and locking up the entire system.
Memory Controllers 29
A Reliable Flight Hardware TopologyControl Signals Shown
xRAM
Producer Consumer
Arbiter
ControllerFSM
Timer to refresh
xRAM state
Memory Controllers 30
Some Recommendations for Memory Data Path
• Stuck Bits– These are common place and can weaken EDAC
• Stronger EDAC• Map pages
– May anneal over times• Multiple Bit Errors
– Use EDAC as appropriate
Memory Controllers 31
Some Recommendations for Memory Controllers
• Control Register– Illegal configuration can lockup SDRAM
• May be cleared by reloading; provide either automatic or commandable reload.
• May require power cycling. Support power cycling at either the subsystem or circuit level
– Illegal configuration can damage SDRAM– SDRAM control registers can not be read
• Bummer.
Memory Controllers 32
Some Recommendations for Memory Controllers (cont'd)
• Design a robust, correct arbiter• Design a robust, correct, memory controller• Do not mix the above two logic blocks