2.7-w constant output power class-d audio power amplifier ... · v dd sw in! in+ agnd pgnd vout+...

VDD SW

IN–

IN+

AGND PGND

VOUT+

VOUT–

V OUTCC V INCC

10 Fm

22 Fm

1 Fm

To Battery

DifferentialInput

CIN

CIN

V FBCC

SDb

SDd

ShutDown Boost

ShutDown ClassD

GAINGain (V /Float/GND)CC

2.2 to 6.2 Hm

GPIO

1 Fm

R150 kΩ

R2500 kΩ

TPA2013D1

Product

Folder

Sample &Buy

Technical

Documents

Tools &

Software

Support &Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPA2013D1SLOS520A –AUGUST 2007–REVISED MARCH 2016

TPA2013D1 2.7-W Constant Output Power Class-D Audio Amplifier With Integrated BoostConverter

1

1 Features1• High Efficiency Integrated Boost Converter (Over

90% Efficiency)• 2.2-W into an 8-Ω Load from a 3.6-V Supply• 2.7-W into an 4-Ω Load from a 3.6-V Supply• Operates from 1.8 V to 5.5 V• Efficient Class-D Prolongs Battery Life• Independent Shutdown for Boost Converter and

Class-D Amplifier• Differential Inputs Reduce RF Common Noise• Built-In INPUT Low-Pass Filter Decreases RF and

Out-of-Band Noise Sensitivity• Synchronized Boost and Class-D Eliminates Beat

Frequencies• Thermal and Short-Circuit Protection• Available in 2.275-mm × 2.275-mm 16-ball WCSP

and 4-mm × 4-mm 20-Lead QFN Packages• 3 Selectable Gain Settings of 2 V/V, 6 V/V, and

10 V/V

2 Applications• Cell Phones• PDA• GPS• Portable Electronics

3 DescriptionThe TPA2013D1 device is a high efficiency Class-Daudio power amplifier with an integrated boostconverter. It drives up to 2.7 W (10% THD+N) into a4-Ω speaker. With 85% typical efficiency, theTPA2013D1 helps extend battery life when playingaudio.

The built-in boost converter generates the voltage railfor the Class-D amplifier. This provides a louderaudio output than a stand-alone amplifier connecteddirectly to the battery. It also maintains a consistentloudness, regardless of battery voltage. Additionally,the boost converter can be used to supply externaldevices.

The TPA2013D1 has an integrated low pass filter toimprove RF rejection and reduce out-of-band noise,increasing the signal-to-noise ratio (SNR). A built-inPLL synchronizes the boost converter and Class-Dswitching frequencies, thus eliminating beatfrequencies and improving audio quality. All outputsare fully protected against shorts to ground, powersupply, and output-to-output shorts.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPA2013D1VQFN (20) 4.00 mm × 4.00 mmDSBGA (16) 2.275 mm × 2.275 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Simplified Application Schematic

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TPA2013D1SLOS520A –AUGUST 2007–REVISED MARCH 2016 www.ti.com

Product Folder Links: TPA2013D1

Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated

Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Device Comparison Table ..................................... 36 Pin Configuration and Functions ......................... 37 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 47.2 ESD Ratings.............................................................. 47.3 Recommended Operating Conditions....................... 47.4 Thermal Information .................................................. 47.5 DC Characteristics .................................................... 57.6 Boost Converter DC Characteristics ......................... 57.7 Class D Amplifier DC Characteristics ....................... 67.8 AC Characteristics .................................................... 67.9 Class D Amplifier AC Characteristics........................ 77.10 Dissipation Ratings ................................................. 77.11 Typical Characteristics ............................................ 8

8 Parameter Measurement Information ................ 139 Detailed Description ............................................ 14

9.1 Overview ................................................................. 149.2 Functional Block Diagram ....................................... 149.3 Feature Description................................................. 149.4 Device Functional Modes........................................ 16

10 Application and Implementation........................ 1810.1 Application Information.......................................... 1810.2 Typical Applications .............................................. 18

11 Power Supply Recommendations ..................... 2511.1 Power Supply Decoupling Capacitors................... 25

12 Layout................................................................... 2512.1 Layout Guidelines ................................................. 2512.2 Layout Examples................................................... 2712.3 Efficiency and Thermal Considerations ................ 28

13 Device and Documentation Support ................. 3013.1 Device Support .................................................... 3013.2 Community Resources.......................................... 3013.3 Trademarks ........................................................... 3013.4 Electrostatic Discharge Caution............................ 3013.5 Glossary ................................................................ 30

14 Mechanical, Packaging, and OrderableInformation ........................................................... 31

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (August 2007) to Revision A Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementationsection, Power Supply Recommendations section, Layout section, Device and Documentation Support section, andMechanical, Packaging, and Orderable Information section. ................................................................................................. 1


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VCC

FB

SW

SW

VC

CO

UT

VC

CIN

SD

b

IN+

IN–

PG

ND

PG

ND

SDd

VDD

PG

ND

2

5

7 10

11

14

1720

GAIN

AGND VOUT–

VOUT–

VOUT+

VOUT+

VOUT+

1819 16

13

12

15

3

4

1

8 96

VCC

FB

SWVCC

OUTVCC

IN

SDbIN+ IN–PGND

AGNDSDdPGNDVOUT–

VDDGAINVOUT+

PGND

D1 D2 D3 D4

C1 C2 C3 C4

B1 B3 B4B2

A1 A2 A3 A4

3

TPA2013D1www.ti.com SLOS520A –AUGUST 2007–REVISED MARCH 2016


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5 Device Comparison Table

DEVICE NUMBER SPEAKER AMP TYPE SPECIAL FEATURE OUTPUT POWER (W) PSRR (Db)TPA2013D1 Class D Boost Converter 2.7 95TPA2015D1 Class D Adaptive Boost Converter 2 85TPA2025D1 Class D Class G Boost Converter 2 65TPA2080D1 Class D Class G Boost Converter 2.2 62.5

6 Pin Configuration and Functions

RGP Package20-Pin VQFN

Top ViewYZH Package16-Pin DSBGA

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNAME VQFN DSBGA

AGND 4 C4 – Analog ground – connect all GND pins together

GAIN 3 B2 I Gain selection pin

IN+ 8 D2 I Positive audio input

IN– 7 D3 I Negative audio input

PGND 9, 10, 20 D1, C2, A4 – Power ground – connect all GND pins together

SDb 6 D4 I Shutdown terminal for the Boost Converter

SDd 5 C3 I Shutdown terminal for the Class D Amplifier

SW 18, 19 A3 – Boost and rectifying switch input

Thermal Pad Die Pad N/A P Solder the thermal pad on the bottom of the QFN package to the GND plane of the PCB. It isrequired for mechanical stability and enhances thermal performance.

VCCFB 2 B3 I Voltage feedback

VC CIN 16 A1 – Class-D audio power amplifier voltage supply – connect to VCCOUT

VCCOUT 17 A2 – Boost converter output – connect to VCCIN

VDD 1 B4 – Supply voltage

VOUT+ 13, 14, 15 B1 O Positive audio output

VOUT– 11, 12 C1 O Negative audio output


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4




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITVDD Supply voltage –0.3 6 VVI Input voltage, Vi: SDb, SDd, IN+, IN–, VCCFB –0.3 VDD + 0.3 V

Continuous total power dissipation See Dissipation RatingsTA Operating free-air temperature –40 85 °CTJ Operating junction temperature –40 150 °CTstg Storage temperature –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD RatingsVALUE UNIT

V(ESD)Electrostaticdischarge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000V

Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500

7.3 Recommended Operating ConditionsMIN MAX UNIT

VDD Supply voltage 1.8 5.5 VVIH High-level input voltage SDb, SDd 1.3 VVIL Low-level input voltage SDb, SDd 0.35 V| IIH | High-level input current SDb = SDd = 5.8 V, VDD = 5.5 V, VCC = 5.5 V 1 μA| IIL| Low-level input current SDb = SDd = -0.3 V, VDD = 5.5 V, VCC = 5.5 V 20 μATA Operating free-air temperature –40 85 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

7.4 Thermal Information

THERMAL METRIC (1)TPA2013D1

UNITRGP (VQFN) YZH (DSBGA)20 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 34 70.6 °C/WRθJC(top) Junction-to-case (top) thermal resistance 33.4 0.3 °C/WRθJB Junction-to-board thermal resistance 10.5 15 °C/WψJT Junction-to-top characterization parameter 0.4 1.8 °C/WψJB Junction-to-board characterization parameter 10.5 14.2 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 3.1 — °C/W


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5




(1) IDD is calculated using IDD = (ICC× VCC)/(VDD×η), where ICC is the class D amplifier quiescent current; η = 40%, which is the boostconverter efficiency when class D amplifier has no load. To achieve the minimal 40% η, it is recommended to use the suggestedinductors in table 4 and to follow the layout guidelines.

7.5 DC CharacteristicsTA = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCCClass-D audio power amplifiervoltage supply range, VCCIN 3 5.5 V

ISD Shutdown quiescent current

SDd = SDb = 0 V, VDD = 1.8 V, RL = 8 Ω 0.04 1.5

μA

SDd = SDb = 0 V, VDD = 3.6 V, RL = 8 Ω 0.04 1.5SDd = SDb = 0 V, VDD = 4.5 V, RL = 8 Ω 0.02 1.5SDd = SDb = 0.35 V, VDD = 1.8 V, RL = 8 Ω 0.03 1.5SDd = SDb = 0.35 V, VDD = 3.6 V, RL = 8 Ω 0.03 1.5SDd = SDb = 0.35 V, VDD = 4.5 V, RL = 8 Ω 0.02 1.5

IDDBoost converter quiescentcurrent

SDd = 0 V, SDb = 1.3 V, VDD = 3.6 V, VCC = 5.5 V, NoLoad, No Filter 1.3 mA

ICCClass D amplifier quiescentcurrent

VDD = 3.6, Vcc = 5.5 V, No Load, No Filter 4.3 6mA

VDD = 4.5, Vcc = 5.5 V, No Load, No Filter 3.6 6

IDD

Boost converter and audiopower amplifier quiescentcurrent, Class D (1)

SDd = SDb = 1.3 V, VDD = 3.6 V, Vcc = 5.5 V, No Load,No Filter 16.5 23

mASDd = SDb = 1.3V, VDD = 4.5 V, Vcc = 5.5 V, No Load,No Filter 11 18.5

fBoost converter switchingfrequency 500 600 700 kHz

Class D switching frequency 250 300 350 kHzUVLO Under voltage lockout 1.7 V

GAINGain input low level Gain = 2 V/V (6 dB) 0 0.35 VGain input mid level Gain = 6 V/V (15.5 dB) (floating input) 0.7 0.8 1 VGain input high level Gain = 10 V/V (20 dB) 1.35 V

PORDClass D Power on reset ONthreshold 2.8 V

7.6 Boost Converter DC CharacteristicsTA = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITVCC Output voltage range 3 5.5 VVFB Feedback voltage 490 500 510 mVIOL Output current limit, Boost_max 1300 1500 1700 mARON_PB PMOS switch resistance 220 mΩRON_NB NMOS resistance 170 mΩ

Line regulation No Load, 1.8 V < VDD < 5.2V, VCC = 5.5 V 3 mV/V

Load regulation VDD = 3.6 V, 0 < IL < 500 mA,VCC = 5.5 V 30 mV/A

IL Start-up current limit, Boost 0.4×IBoost mA


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6




7.7 Class D Amplifier DC CharacteristicsTA = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CMR Input common mode rangeVin = ±100 mV, VDD = 1.8 V, VCC = 3 V, RL = 8 Ω 0.5 2.2

VVin = ±100 mV, VDD = 2.5 V, VCC = 3.6 V, RL = 8 Ω 0.5 2.8Vin = ±100 mV, VDD = 3.6 V, VCC = 5.5 V, RL = 8 Ω 0.5 4.7

CMRR Input common mode rejection RL = 8 Ω, Vicm = 0.5 and Vicm = VCC – 0.8, differentialinputs shorted –75 dB

VOOOutput offset voltageClass-D

VCC = 3.6 V, Av = 2 V/V, IN+ = IN– = Vref, RL = 8 Ω 1 6

mVVCC= 3.6 V, Av = 6 V/V, IN+ = IN– = Vref, RL = 8 Ω 1 6VCC= 3.6 V, Av = 10 V/V, IN+ = IN– = Vref, RL = 8 Ω 1 6VCC = 5.5 V, Av = 2 V/V, IN+ = IN– = Vref, RL = 8 Ω 1 6

Rin Input ImpedanceGain = 2 V/V (6 dB) 32

kΩGain = 6 V/V (15.5 dB) 15Gain = 10 V/V (20 dB) 9.5

RDS(on)

OUTP High-side FET On-stateseries resistance

IOUTx = –300 mA; VCC = 3.6 V

0.36

Ω

OUTP Low-side FET On-stateseries resistance 0.36

RDS(on)

OUTN High-side FET On-stateseries resistance 0.36

OUTN Low-side FET On-stateseries resistance 0.36

AV

Low Gain GAIN ≤ 0.35 V 1.8 2 2.2 V/VMid Gain GAIN = 0.8 V 5.7 6 6.3 V/VHigh Gain GAIN ≥ 1.35 V 9.5 10 10.5 V/V

7.8 AC CharacteristicsTA = 25°C, VDD = 3.6 V, RL = 8 Ω, L = 4.7 μH (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITtSTART Start up time 1.8 V ≤ VDD ≤ 5.5 V, CIN ≤ 1 μF 7.5 ms

η Efficiency

THD+N = 1%, VCC = 5.5 V, VDD = 3.6 V,RL= 8 Ω, Pout = 1.7 W, Cboost= 47μF 85%

THD+N = 1%, VCC = 5.5 V, VDD = 4.2 V,RL = 8 Ω, Pout = 1.7 W 87.5%

Thermal Shutdown Threshold 150 °C


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7




7.9 Class D Amplifier AC CharacteristicsTA = 25°C, VDD = 3.6V, RL = 8 Ω, L = 4.7μH (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITKSVRClass-D

Output referred power supplyrejection ratio

VDD = 3.6 V, VCC = 5.5V, 200 mVPP ripple,f = 217 Hz –95 dB

THD+NClass-D Total harmonic distortion + noise

f = 1 kHz, Po = 1.7 W, VCC = 5.5 V 1%f = 1 kHz, Po = 1.2 W, VCC = 4.5 V 1%f = 1 kHz, Po = 2.2 W, VCC = 5.5 V 10%f = 1 kHz, Po = 1 W, VCC = 5.5 V 0.1%

VnClass-D

Output integrated noise floor Av = 6 dB (2V/V) 31μVrmsOutput integrated noise floor A-

weighted Av = 6 dB (2V/V) 23

PO Maximum output power

THD+N = 10%, VCC = 5.5 V, VDD = 3.6 V , RL = 8Ω

2.2

W

THD+N = 1%, VCC = 5.5 V, VDD = 3.6 V , RL = 8 Ω 1.7THD+N = 1%, VCC = 4.5 V, VDD = 3.6 V , RL = 8 Ω 1.2THD+N = 10%, VCC = 5.5 V, VDD = 3.6 V , RL = 4Ω

2.7

THD+N = 1%, VCC = 5.5 V, VDD = 3.6 V , RL = 4 Ω 2.2THD+N = 1%, VCC = 4.5 V, VDD = 3.6 V , RL = 4 Ω 1.9

(1) Derating factor measured with JEDEC High K board.

7.10 Dissipation RatingsPACKAGE TA ≤ 25°C DERATING FACTOR (1) TA = 70°C TA = 85°C

16 ball WCSP 1.5 W 12.4 mW/°C 1 W 0.8 W20 pin QFN 2.5 W 20.1 mW/°C 1.6 W 1.3 W


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PO − Output Power − W

0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.5 1.0 1.5

I DD

− S

uppl

y C

urre

nt −

A

G005

VDD = 1.8 V

Gain = 2 V/VRL = 8 Ω + 33 µHVCC = 4.5 V

VDD = 2.5 V

VDD = 4.2 V

VDD = 3.6 V


0.0

0.2

0.4

0.6

0.8

1.0

1.2

0.0 0.5 1.0 1.5 2.0

I DD

− S

uppl

y C

urre

nt −

A

G006

VDD = 1.8 V


VDD = 2.5 V

VDD = 4.2 V

VDD = 3.6 V


0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.0 0.5 1.0 1.5

PD

− P

ower

Dis

sipa

tion

− W

G003

VDD = 3.6 V

VDD = 1.8 V


VDD = 2.5 V

VDD = 4.2 V


0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.0 0.5 1.0 1.5 2.0

PD

− P

ower

Dis

sipa

tion

− W

G004

VDD = 1.8 V


VDD = 2.5 V

VDD = 4.2 V

VDD = 3.6 V


0

20

40

60

80

100

0.0 0.5 1.0 1.5

Effi

cien

cy −

%

G001


VDD = 4.2 VVDD = 3.6 V VDD = 2.5 V

VDD = 1.8 V


0

20

40

60

80

100

0.0 0.5 1.0 1.5 2.0

Effi

cien

cy −

%

G002


VDD = 4.2 VVDD = 3.6 V VDD = 2.5 V

VDD = 1.8 V

8




7.11 Typical Characteristics

Figure 1. Efficiency vs Output Power Figure 2. Efficiency vs Output Power

Figure 3. Power Dissipation vs Output Power Figure 4. Power Dissipation vs Output Power

Figure 5. Supply Current vs Output Power Figure 6. Supply Current vs Output Power


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RL − Load Resistance − Ω

0.0

0.5

1.0

1.5

2.0

2.5

3.0

4 8 12 16 20 24 28 32

PO

− O

utpu

t Pow

er −

W

G011

f = 1 kHzGain = 2 V/VVCC = 4.5 V

THD = 1%

THD = 10%

RL − Load Resistance − Ω

0.0

0.5

1.0

1.5

2.0

2.5

3.0

4 8 12 16 20 24 28 32

PO

− O

utpu

t Pow

er −

W

G012

f = 1 kHzGain = 2 V/VVCC = 5.5 V

THD = 1%

THD = 10%

VDD − Supply Voltage − V

0.0

0.5

1.0

1.5

2.0

2.5

1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6

PO

− O

utpu

t Pow

er −

W

G009

Gain = 2 V/VRL = 8 Ω + 33 µHTHD = 10%VCC = 4.5 V

L = 2.2 µH

L = 3.3 µHL = 6.2 µH

L = 4.7 µH


0.0

0.5

1.0

1.5

2.0

2.5

1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4

PO

− O

utpu

t Pow

er −

W

G010

L = 6.2 µH

L = 4.7 µH

L = 3.3 µH



0.0

0.5

1.0

1.5

2.0

2.5

1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6

PO

− O

utpu

t Pow

er −

W

G007


L = 2.2 µH

L = 3.3 µHL = 6.2 µH

L = 4.7 µH


0.0

0.5

1.0

1.5

2.0

2.5

1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4

PO

− O

utpu

t Pow

er −

W

G008

L = 3.3 µH

L = 6.2 µH

L = 4.7 µH


9




Typical Characteristics (continued)

Figure 7. Output Power vs Supply Voltage Figure 8. Output Power vs Supply Voltage

Figure 9. Output Power vs Supply Voltage Figure 10. Output Power vs Supply Voltage

Figure 11. Output Power vs Load Figure 12. Output Power vs Load


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f − Frequency − Hz

0.1

0.01

0.001

G017

Gain = 2 V/VRL = 8 Ω + 33 µHVCC = 4.5 VVDD = 3.6 V

1

PO = 0.05 W

PO = 1 W

20 100 1k 20k10k

PO = 0.25 W

TH

D+

N −

%

10

20 100 1k 20k10k


0.1

0.01

0.001

G018


1

PO = 0.075 W

PO = 0.025 W

PO = 0.2 W

TH

D+

N −

%

10


0.01 0.1 1 5

1

0.1

0.01

G015

Gain = 2 V/VRL = 4 Ω + 33 µHVCC = 5.5 V10 VDD = 1.8 V

VDD = 2.5 V

VDD = 4.2 V

VDD = 3.6 V

TH

D+

N −

%

100


20 100 1k 20k

0.1

0.01

0.001

G016


1

PO = 0.075 W

PO = 0.2 W

10k

PO = 0.025 W

TH

D+

N −

%

10


0.01 0.1 1 3

100

1

0.1

0.01

G013

Gain = 2 V/VRL = 8 Ω + 33 µHVCC = 4.5 V10

VDD = 1.8 V

VDD = 2.5 V

VDD = 4.2 V

VDD = 3.6 V

TH

D+

N −

%

0.01 0.1 1 3


1

0.1

0.01

G014

Gain = 2 V/VRL = 8 Ω + 33 µHVCC = 5.5 V10

VDD = 1.8 V

VDD = 2.5 V

VDD = 4.2 V

VDD = 3.6 V

TH

D+

N −

%

100

10





Figure 13. Total Harmonic distortion + Noise vs OutputPower

Figure 14. Total Harmonic Distortion + Noise vs OutputPower

Figure 15. Total Harmonic Distortion + Noise vs OutputPower

Figure 16. Total Harmonic Distortion + Noise vs Frequency

Figure 17. Total Harmonic Distortion + Noise vs Frequency Figure 18. Total Harmonic Distortion + Noise vs Frequency


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−120

−100

−80

−60

−40

−20

0


PS

RR

− d

B

G023


20 100 1k 20k10k

VDD = 3.6 V VDD = 2.5 V

VDD = 1.8 V

VDD = 4.2 V

−120

−100

−80

−60

−40

−20

0


CM

RR

− d

B

G024

Gain = 2 V/VRL = 8 ΩVCC = 4.5 V

20 100 1k 20k10k

VDD = 3.6 V

VDD = 2.5 VVDD = 1.8 V

VDD = 4.2 V

20 100 1k 20k10k


0.1

0.01

0.001

G021

Gain = 2 V/VPO = 250 mWRL = 4 Ω + 33 µHVCC = 5.5 V

1

VDD = 1.8 V

VDD = 2.5 V

VDD = 4.2 V

VDD = 3.6 V

TH

D+

N −

%

10

−120

−100

−80

−60

−40

−20

0


PS

RR

− d

B

G022


20 100 1k 20k10k

VDD = 3.6 V

VDD = 4.2 V

VDD = 2.5 V

VDD = 1.8 V

20 100 1k 20k10k


0.1

0.01

0.001

G019


1

PO = 0.05 W

PO = 1 W

PO = 0.25 W

TH

D+

N −

%

10

20 100 1k 20k10k


0.1

0.01

0.001

G020

Gain = 2 V/VPO = 250 mWRL = 4 Ω + 33 µHVCC = 4.5 V

1VDD = 1.8 V

VDD = 2.5 V

VDD = 4.2 V

VDD = 3.6 V

TH

D+

N −

%

10

11





Figure 19. Total Harmonic Distortion + Noise vs Frequency Figure 20. Total Harmonic Distortion + Noise vs Frequency

Figure 21. Total Harmonic Distortion + Noise vs Frequency Figure 22. Power Supply Rejection Ratio vs Frequency

Figure 23. Power Supply Rejection Ratio vs Frequency Figure 24. Common-Mode Rejection Ratio vs Frequency


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VDD − Supply Voltage (Boost) − V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.8 2.2 2.6 3.0 3.4 3.8 4.2

L = 4.7 µH

I OM

− M

ax. C

ontin

uous

Out

put C

urre

nt −

A

VCC = 4.5 V

VCC = 5.5 V

G029t − Time − ms

−2

−1

0

1

2

3

4

5

6

0 2 4 6 8 10 12 14 16 18 20

V −

Vol

tage

− V

VCC

OUT

SDb, SDd

Start Time 7.5 ms

G030

50

55

60

65

70

75

80

85

90

95

100

IO − Output Current − A

0.01 0.1 1

VCC = 5.5 V

VDD = 1.8 V

VDD = 2.5 V

VDD = 3.6 V

VDD = 4.2 V

Boo

st E

ffici

ency

− %

G027 VDD − Supply Voltage − V

50

60

70

80

90

100

1.8 2.2 2.6 3.0 3.4 3.8 4.2

ICC = 250 mAL = 4.7 µH

Boo

st E

ffici

ency

− %

VCC = 4.5 V

VCC = 5.5 V

G028

−90

−80

−70

−60

−50

−40

−30

−20

−10

0


CM

RR

− d

B

G025

Gain = 2 V/VRL = 8 ΩVCC = 5.5 V

20 100 1k 20k10k

VDD = 3.6 V

VDD = 1.8 V

VDD = 2.5 V

VDD = 4.2 V

50

55

60

65

70

75

80

85

90

95

100

IO − Output Current − A

0.01 0.1 1

VCC = 4.5 V

VDD = 1.8 V

VDD = 2.5 V

VDD = 3.6 V

VDD = 4.2 V

Boo

st E

ffici

ency

− %

G026

12





Figure 25. Common-Mode Rejection Ratio vs Frequency Figure 26. Boost Efficiency vs Output Current

Figure 27. Boost Efficiency vs Output Current Figure 28. Boost Efficiency vs Supply Voltage

Figure 29. Maximum Continuous Output Current vs SupplyVoltage (Boost)

Figure 30. Start-Up Time


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TPA2013D1

IN+

IN

OUT+

OUT–

VDD

VDD

GND

CI

CI

MeasurementOutput

+

+

–

–

Load30 kHz

Low-PassFilter

MeasurementInput

+

–

1 Fm

13




8 Parameter Measurement Information

All parameters are measured according to the conditions described in Specifications. Figure 31 shows the setupused for the typical characteristics of the test device.

(1) CI was shorted for any common-mode input voltage measurement. All other measurements were taken with a 1-μF CI(unless otherwise noted).

(2) A 33-μH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.(3) The 30-kHz low-pass filter is required, even if the analyzer has an internal low-pass filter. An RC low-pass filter (100-

Ω, 47-nF) is used on each output for the data sheet graphs.(4) L = 4.7 μH is used for the boost converter unless otherwise noted.

Figure 31. Test Set-Up for Graphs


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PWMand

LevelShifter

H-Bridge

Internal

Oscillator

Biases, Control,and

References

Regulator

Vmax

Control

GateControl

Anti-Ringing

PGND

AGND

BG Control

PGNDAGND

V OUTCC

Vref

AGND

IN+

IN–

SDb

VDD

SW

V OUTCC

V FBCC

V INCC

VOUT+

VOUT–

PGND

SDd

Res.Array

GAIN

14




9 Detailed Description

9.1 OverviewThe TPA2013D1 is a high efficiency Class D audio power amplifier with an integrated boost converter. It drivesup to 2.7 W (10% THD+N) into a 4-Ω speaker. The built-in boost converter generates the voltage rail for theClass-D amplifier. The TPA2013D1 has an integrated low-pass filter to improve RF rejection and reduce out-of-band noise, increasing the signal-to-noise ratio (SNR).

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Fully Differential AmplifierThe TPA2013D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifierconsists of a differential amplifier with common-mode feedback. The differential amplifier ensures that theamplifier outputs a differential voltage on the output that is equal to the differential input times the gain. Thecommon-mode feedback ensures that the common-mode voltage at the output is biased around VCC/2 regardlessof the common-mode voltage at the input. The fully differential TPA2013D1 can still be used with a single-endedinput; however, the TPA2013D1 must be used with differential inputs when in a noisy environment, like awireless handset, to ensure maximum noise rejection.


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15




Feature Description (continued)9.3.1.1 Advantages of Fully Differential Amplifiers• Input-coupling capacitors not required:

– The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. The inputs ofthe TPA2013D1 can be biased anywhere within the common mode input voltage range listed in theRecommended Operating Conditions. If the inputs are biased outside of that range, input-couplingcapacitors are required.

• Midsupply bypass capacitor, C(BYPASS), not required:– The fully differential amplifier does not require a bypass capacitor. Any shift in the midsupply affects both

positive and negative channels equally and cancels at the differential output.• Better RF-immunity:

– GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. Thetransmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signalbetter than the typical audio amplifier.

9.3.2 Class-D AmplifierThe TPA2013D1 is a high efficiency Class-D audio power amplifier with an integrated boost converter able todrive up to 2.7 W (10% THD+N) into a 4-Ω speaker with 85% typical efficiency, the device helps extend batterylife when playing audio. It is available in 2.275-mm × 2.275-mm 16-ball WCSP and 4-mm × 4-mm 20-lead QFNpackages. The device has three selectable gain settings of 2 V/V, 6 V/V and 10 V/V.

9.3.3 Boost ConverterThe TPA2013D1 consists of a boost converter and a Class-D amplifier. The boost converter takes a low supplyvoltage, VDD, and increases it to a higher output voltage, VCC.

The two main passive components necessary for the boost converter are the boost inductor and the boostcapacitor. The boost inductor stores current, and the boost capacitor stores charge. As the Class-D amplifierdepletes the charge in the boost capacitor, the boost inductor charges it back up with the stored current. Thecycle of charge and discharge occurs at a frequency of fboost.

The TPA2013D1 allows a range of VCC voltages, including setting VCC lower than VDD.

9.3.4 Operation With DACs and CODECsWhen using switching amplifiers with CODECs and DACs, sometimes there is an increase in the output noisefloor from the audio amplifier. This occurs when mixing of the output frequencies of the CODEC and DAC withthe switching frequencies of the audio amplifier input stage. The noise increase can be solved by placing a low-pass filter between the CODEC and DAC and audio amplifier. This filters off the high frequencies that cause theproblem and allow proper performance.

The TPA2013D1 has a two pole low-pass filter at the inputs. The cutoff frequency of the filter is set toapproximately 100 kHz. The integrated low-pass filter of the TPA2013D1 eliminates the need for additionalexternal filtering components. A properly designed additional low-pass filter may be added without altering theperformance of the device.

If driving the TPA2013D1 input with 4th-order or higher ΔΣ DACs or CODECs, add an R-C low-pass filter at eachof the audio inputs (IN+ and IN–) of the TPA2013D1 to ensure best performance. The recommended resistorvalue is 100 Ω and the capacitor value of 47 nF.

9.3.5 Filter-Free Operation and Ferrite Bead FiltersA ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and thefrequency sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCCand CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead,choose one with high impedance at high frequencies, and very low impedance at low frequencies. In addition,select a ferrite bead with adequate current rating to prevent distortion of the output signal.

Use an LC output filter if there are low-frequency, (< 1 MHz) EMI-sensitive circuits and/or there are long leadsfrom amplifier to speaker.


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1 nFFerrite

Chip Bead

OUTP

OUTN

1 nF

FerriteChip Bead

16




Feature Description (continued)Figure 32 shows a typical ferrite bead output filters.

Figure 32. Typical Ferrite Chip Bead Filter

Table 1. Suggested Chip Ferrite BeadLOAD VENDOR PART NUMBER SIZE

8 Ω Murata BLM18EG121SN1 06034 Ω TDK MPZ2012S101A 0805

9.3.6 Fixed Gain SettingsThe TPA2013D1 has 3 selectable fixed-gains: 6 dB, 15.5 dB, and 20 dB. Connect the GAIN pin as shown inTable 2.

Table 2. Amplifier Fixed-GainCONNECT GAIN PIN TO AMPLIFIER GAIN

GND 6 dBNo connection (Floating) 15.5 dB

VBAT 20 dB

9.4 Device Functional Modes

9.4.1 Boost Converter ModeThe TPA2013D1 has 4 boost converter operation modes as shown in Table 3.

Table 3. Boost Converter Mode ConditionCASE OUTPUT CURRENT MODE OF OPERATION

VDD < VCC Low Continuous (fixed frequency)VDD < VCC High Continuous (fixed frequency)VDD ≥ VCC Low Discontinuous (variable frequency)VDD ≥ VCC High Discontinuous (variable frequency)

9.4.2 Shutdown ModeThe TPA2013D1 amplifier can be put in shutdown mode when asserting SDd pin to a logic LOW. While inshutdown mode, the device output stage is turned off and the current consumption is very low. The boostconverter can be put in shutdown mode when asserting SDb pin to a logic LOW. While in shutdown Mode, theboost converter is turned off.


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17




Table 4. Device Configuration

SDb SDdBOOST

CONVERTER

CLASS DAMPLIFIER COMMENTS

low low OFF OFF Device is in shutdown mode Iq ≤ 1 μA

low high OFF ON Boost converter is off. Class-D Audio Power Amplifier (APA) can be driven by anexternal pass transistor connected to the battery.

high low ON OFF Class-D APA is off. Boost Converter is on and can be used to drive an external device.

high high ON ONBoost converter and Class-D APA are on. Normal operation. Boost converter can beused to drive an external device in parallel to the Class-D APA within the limits of theboost converter output current.


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VDD SW

IN–

IN+

AGND PGND

VOUT+

VOUT–

V OUTCC V INCC

10 Fm

22 Fm

1 Fm

To Battery

DifferentialInput

CIN

CIN

V FBCC

SDb

SDd

ShutDown Boost

ShutDown ClassD

GAINGain (V /Float/GND)CC

2.2 to 6.2 Hm

GPIO

1 Fm

R150 kΩ

R2500 kΩ

TPA2013D1

18




10 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

10.1 Application InformationThese typical connection diagrams highlight the required external components and system level connections forproper operation of the device. Each of these configurations can be realized using the Evaluation Modules(EVMs) for the device. These flexible modules allow full evaluation of the device in the most common modes ofoperation. Any design variation can be supported by TI through schematic and layout reviews. Visit e2e.ti.com fordesign assistance, and join the audio amplifier discussion forum for additional information.

10.2 Typical Applications

10.2.1 TPA2013D1 With Differential Input Signal

Figure 33. Typical Application Schematic With Differential Input Signals

10.2.1.1 Design RequirementsFor this design example, use the parameters listed in Table 5.

Table 5. Design ParametersDESIGN PARAMETERS EXAMPLE VALUE

Power Supply 3.6 V

Enable InputsHigh > 1.3 VLow < 0.6 V

Speaker 8 Ω


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DD CC DD

L CC

V (V V )L =

I f Vboost

´ -

D ´ ´

CCL CC

DD

VI = I

V 0.8

æ ö´ ç ÷

´è ø

CC0.5 (R1 + R2)

V =R1

´æ öç ÷è ø

19




10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Setting the Boost Voltage

Use Equation 1 to determine the value of R1 for a given VCC. The maximum recommended value for VCC is5.5 V. The typical value of the VCCFB pin is 500 mV. The current through the resistor divider should be about 100times greater than the current into the VCCFB pin, typically 0.01 μA. Based on those two values, therecommended value of R2 is 500 kΩ. VCC must be greater than 3 V and less than or equal to 5.5 V.

(1)

10.2.1.2.2 Inductor Selection

10.2.1.2.2.1 Surface Mount Inductors

Working inductance decreases as inductor current increases. If the drop in working inductance is severe enough,it may cause the boost converter to become unstable, or cause the TPA2013D1 to reach its current limit at alower output power than expected. Inductor vendors specify currents at which inductor values decrease by aspecific percentage. This can vary by 10% to 35%. Inductance is also affected by DC current and temperature.

10.2.1.2.2.2 TPA2013D1 Inductor Equations

Inductor current rating is determined by the requirements of the load. The inductance is determined by twofactors: the minimum value required for stability and the maximum ripple current permitted in the application.

Use Equation 2 to determine the required current rating. Equation 2 shows the approximate relationship betweenthe average inductor current, IL, to the load current, load voltage, and input voltage (ICC, VCC, and VDD,respectively). Insert ICC, VCC, and VDD into Equation 2 to solve for IL. The inductor must maintain at least 90% ofits initial inductance value at this current.

(2)

The minimum working inductance is 2.2 μH. A lower value may cause instability.

Ripple current, ΔIL, is peak-to-peak variation in inductor current. Smaller ripple current reduces core losses in theinductor as well as the potential for EMI. Use Equation 3 to determine the value of the inductor, L. Equation 3shows the relationship between inductance L, VDD, VCC, the switching frequency, fboost, and ΔIL. Insert themaximum acceptable ripple current into Equation 3 to solve for L.

(3)

ΔIL is inversely proportional to L. Minimize ΔIL as much as is necessary for a specific application. Increase theinductance to reduce the ripple current.

NOTEMaking the inductance too large prevents the boost converter from responding to fast loadchanges properly. Typical inductor values for the TPA2013D1 are 4.7 μH to 6.8 μH.

Select an inductor with a small DC resistance, DCR. DCR reduces the output power due to the voltage dropacross the inductor.

10.2.1.2.3 Capacitor Selection

10.2.1.2.3.1 Surface Mount Capacitors

Temperature and applied DC voltage influence the actual capacitance of high-K materials.

Table 6 shows the relationship between the different types of high-K materials and their associated tolerances,temperature coefficients, and temperature ranges. Notice that a capacitor made with X5R material can lose up to15% of its capacitance within its working temperature range.


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( )CC CC DD

boost CC

I V VC =

V f V

´ -

D ´ ´

( )CC CC DD

boost CC

I V VC = 2

V f V

´ -´

D ´ ´

20




High-K material is very sensitive to applied DC voltage. X5R capacitors can have losses ranging from 15 to 45%of their initial capacitance with only half of their DC-rated voltage applied. For example, if 5 Vdc is applied to a10-V, 1-μF X5R capacitor, the measured capacitance at that point may show 0.85 μF, 0.55 μF, or somewhere inbetween. Y5V capacitors have losses that can reach or exceed 50% to 75% of their rated value.

In an application, the working capacitance of components made with high-K materials is generally much lowerthan nominal capacitance. A worst-case result with a typical X5R material might be –10% tolerance, –15%temperature effect, and –45% DC-voltage effect at 50% of the rated voltage. This particular case would result ina working capacitance of 42% (0.9 × 0.85 × 0.55) of the nominal value.

Select high-K ceramic capacitors according to the following rules:1. Use capacitors made of materials with temperature coefficients of X5R, X7R, or better.2. Use capacitors with DC-voltage ratings of at least twice the application voltage. Use minimum 10-V

capacitors for the TPA2013D1.3. Choose a capacitance value at least twice the nominal value calculated for the application. Multiply the

nominal value by a factor of 2 for safety. If a 10-μF capacitor is required, use 20 μF.

The preceding rules and recommendations apply to capacitors used in connection with the TPA2013D1. TheTPA2013D1 cannot meet its performance specifications if the rules and recommendations are not followed.

Table 6. Typical Tolerance and Temperature Coefficient of Capacitance by MaterialMATERIAL COG/NPO X7R X5R

Typical Tolerance ±5% ±10% 80/–20%Temperature Coefficient ±30ppm ±15% 22/–82%Temperature Range, °C –55/125°C –55/125°C –30/85°C

10.2.1.2.3.2 TPA2013D1 Capacitor Equations

The value of the boost capacitor is determined by the minimum value of working capacitance required for stabilityand the maximum voltage ripple allowed on VCC in the application. The minimum value of working capacitance is10 μF. Do not use any component with a working capacitance less than 10 μF.

For X5R or X7R ceramic capacitors, Equation 4 shows the relationship between the boost capacitance, C, toload current, load voltage, ripple voltage, input voltage, and switching frequency (ICC, VCC, ΔV, VDD, fboostrespectively). Insert the maximum allowed ripple voltage into Equation 4 to solve for C. A factor of 2 is includedto implement the rules and specifications listed earlier.

(4)

For aluminum or tantalum capacitors, Equation 5 shows the relationship between the boost capacitance, C, toload current, load voltage, ripple voltage, input voltage, and switching frequency (ICC, VCC, ΔV, VDD, fboostrespectively). Insert the maximum allowed ripple voltage into Equation 5 to solve for C. Solve this equationassuming ESR is zero.

(5)

Capacitance of aluminum and tantalum capacitors is normally not sensitive to applied voltage, so there is nofactor of 2 included in Equation 5. However, the ESR in aluminum and tantalum capacitors can be significant.Choose an aluminum or tantalum capacitor with ESR around 30 mΩ. For best perfornamce using of tantalumcapacitor, use at least a 10-V rating.

NOTETantalum capacitors must generally be used at voltages of half their ratings or less.

10.2.1.2.4 Recommended Inductor and Capacitor Values by Application

Use Table 7 as a guide for determining the proper inductor and capacitor values.


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I)I

1C =

(2 f Rc´ p ´ ´

)I I

1f =c

(2 R C´ p ´

21




(1) All power levels are calculated at 1% THD unless otherwise noted(2) All values listed are for ceramic capacitors. The correction factor of 2 is included in the values.

Table 7. Recommended ValuesCLASS-D

OUTPUT POWER(W) (1)

CLASS-DLOAD

(Ω)

MINIMUMVDD(V)

REQUIREDVCC(V)

MAX IL(A)

L(μH)

INDUCTORVENDOR

PART NUMBERSMAX ΔV(mVpp)

C (2)

(μF)CAPACITOR VENDOR

PART NUMBERS

1 8 3 4.3 0.70

3.3

30

10

Toko DE2812CCoilcraft DO3314

Murata LQH3NPN3R3NG0

Kemet C1206C106K8PACTUMurata GRM32ER61A106KA01BTaiyo Yuden LMK316BJ106ML-T

1.6 8 3 5.5 1.13

4.7

30

22

Murata LQH32PN4R7NN0Toko DE4514C

Coilcraft LPS4018-472

Murata GRM32ER71A226KE20LTaiyo Yuden LMK316BJ226ML-T

2 4 3 4.6 1.533.3

3033

Murata LQH55PN3R3NR0Toko DE4514C TDK C4532X5R1A336M

2.3 4 1.8 5.5 26.2

3047

SumidaCDRH5D28NP-6R2NC

Murata GRM32ER61A476KE20LTaiyo Yuden LMK325BJ476MM-T

10.2.1.2.5 Components Location and Selection

10.2.1.2.5.1 Decoupling Capacitors

The TPA2013D1 is a high-performance Class-D audio amplifier that requires adequate power-supply decouplingto ensure the efficiency is high and total harmonic distortion (THD) is low. Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 μF, as close as possible to the device VDD lead. This choice ofcapacitor and placement helps with higher frequency transients, spikes, or digital hash on the line. Additionally,placing this decoupling capacitor close to the TPA2013D1 is important for the efficiency of the Class-D amplifier,because any resistance or inductance in the trace between the device and the capacitor can cause a loss inefficiency. Place a capacitor of 10 μF or greater between the power supply and the boost inductor. The capacitorfilters out high-frequency noise. More importantly, it acts as a charge reservoir, providing energy more quicklythan the board supply, thus helping to prevent any droop.

10.2.1.2.5.2 Input Capacitors

The TPA2013D1 does not require input coupling capacitors if the design uses a differential source that is biasedwithin the common mode input range. Use input coupling capacitors if the input signal is not biased within therecommended common-mode input range, if high-pass filtering is needed, or if using a single-ended source.

The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined inEquation 6.

(6)

The value of the input capacitor is important to consider as it directly affects the bass (low frequency)performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so thecorner frequency can be set to block low frequencies in this application. Not using input capacitors can increaseoutput offset.

Use Equation 7 to find the required the input coupling capacitance.

(7)

Any mismatch in capacitance between the two inputs causes a mismatch in the corner frequencies. Choosecapacitors with a tolerance of ±10% or better.

10.2.1.3 Application CurvesFor application curves, see the figures listed in table Table 8.


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Toko1098AS-4R7M

Toshiba CRS 06Schottky Diode

VDD SW

IN–

IN+

AGND PGND

VOUT+

VOUT–

V OUTCC V INCC

22 Fm

22 Fm

1 Fm

To Battery

LeftChannel

Input

CIN

CIN

V FBCC

SDb

SDd

GAIN

4.7 Hm

GND = BypassV = Boost ModeDD

1 Fm

R150 kΩ

R2500 kΩ

TPA2013D1

GPIO

22




Table 8. Table of GraphsDESCRIPTION FIGURE NUMBER

Efficiency vs Output Power Figure 1Supply Current vs Output Power Figure 5Output Power vs Supply Voltage Figure 7

Output Power vs Load Figure 11

10.2.2 Bypassing the Boost ConverterBypass the boost converter to drive the Class-D amplifier directly from the battery. Place a Shottky diodebetween the SW pin and the VCCIN pin. Select a diode that has an average forward current rating of at least 1 A,reverse breakdown voltage of 10 V or greater, and a forward voltage as small as possible. See Figure 34 for anexample of a circuit designed to bypass the boost converter.

Do not configure the circuit to bypass the boost converter if VDD is higher than VCC when the boost converter isenabled (SDb ≥ 1.3 V); VDD must be lower than VCC for proper operation. VDD may be set to any voltage withinthe recommended operating range when the boost converter is disabled (SDb ≤ 0.3 V).

Place a logic high on SDb to place the TPA2013D1 in boost mode. Place a logic low on SDb to place theTPA2013D1 in bypass mode.

Figure 34. Bypass Circuit


10.2.2.2 Detailed Design ProcedureFor the design procedure, see Detailed Design Procedure.


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TPA2032D1

VDD

IN–

IN+

GND

VO+

SHUTDOWN

CI

CI

1 Fm

VO–

VDD SW

IN–

IN+

AGND PGND

VOUT+

VOUT–

V OUTCC V INCC

22 Fm

47 Fm

1 Fm

To Battery

LeftChannel

Input

RightChannel

Input

CIN

CIN

V FBCC

SDb

SDd

ShutDown Boost

ShutDown ClassD

GAIN

4.7 Hm

GPIO

1 Fm

R162.5 kΩ

R2500 kΩ

TPA2013D1

23




10.2.2.3 Application CurvesFor application curves, see the figures listed in Table 8.

10.2.3 Stereo Operation ApplicationUse the boost converter of the TPA2013D1 to supply the power for another audio amplifier when stereooperation is required. Ensure the gains of the amplifiers match each other. This prevents one channel fromsounding louder than the other. Use Equation 1 through Equation 5 to determine R1, R2, boost inductor, and theboost capacitor values. Figure 35 is an example schematic. The TPA2032D1 is a good choice for thisapplication; the gain is internally set to 2 V/V, the power supply is compatible with VCCOUT of the TPA2013D1,and the output power of the TPA2032D1 is on par with the TPA2013D1.

Figure 35. TPA2013D1 in Stereo With the TPA2032D1


10.2.3.2 Detailed Design ProcedureFor the design procedure, see Detailed Design Procedure.

10.2.3.3 Application CurvesFor application curves, see the figures listed in Table 8.


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GPIO

LXCL-PWF3

NDS355N

1 W

CKG57NX5R1C107M

VDD SW

IN–

IN+

AGND PGND

VOUT+

VOUT–

V OUTCC V INCC

22 Fm

100 Fm

1 Fm

To Battery

DifferentialInput

CIN

CIN

V FBCC

SDb

SDd

ShutDown Boost

ShutDown ClassD

GAINGain

6.2 Hm

GPIO

1 Fm

R150 kΩ

R2500 kΩ

TPA2013D1

24




10.2.4 LED Driver for Digital Still CamerasUse the boost converter of the TPA2013D1 as a power supply for the flash LED of a digital still camera. Use amicroprocessor or other device or synchronize the flash to shutter sound that typically comes from the speaker ofa digital still camera. Figure 36 shows a typical circuit for this application. LEDs, switches, and other componentsvaries by application.

Figure 36. LED Driver

10.2.5 Design RequirementsFor this design example, use the parameters listed in Table 5.

10.2.6 Detailed Design ProcedureFor the design procedure, see Detailed Design Procedure.

10.2.7 Application CurvesFor application curves, see the figures listed in Table 8.


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25




11 Power Supply RecommendationsThe TPA2013D1 is designed to operate from an input voltage supply range from 1.8 V to 5.5 V. Therefore, theoutput voltage range of the power supply should be within this range. The current capability of upper power mustnot exceed the maximum current limit of the power switch.

11.1 Power Supply Decoupling CapacitorsThe TPA2013D1 requires adequate power-supply decoupling to ensure a high-efficiency operation with low totalharmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF,within 2 mm of the VDD/VCCOUT pin. This choice of capacitor and placement helps with higher-frequencytransients, spikes, or digital hash on the line. In addition to the 0.1-μF ceramic capacitor, TI recommends placinga 2.2-µF to 10-µF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providingenergy faster than the board supply, thus helping to prevent any droop in the supply voltage.

12 Layout

12.1 Layout Guidelines

12.1.1 Component PlacementPlace all the external components close to the TPA2013D1 device. Placing the decoupling capacitors as close tothe device as possible is important for the efficiency of the class-D amplifier. Any resistance or inductance in thetrace between the device and the capacitor can cause a loss in efficiency

12.1.1.1 Trace WidthRecommended trace width at the solder balls is 75 μm to 100 μm to prevent solder wicking onto wider PCBtraces.

For high current pins (SW, PGND, VOUT+, VOUT–, VCCIN, and VCCOUT) of the TPA2013D1, use 100-μm tracewidths at the solder balls and at least 500-μm PCB traces to ensure proper performance and output power forthe device.

For low current pins (IN–, IN+, SDd, SDb, GAIN, VCCFB, VDD) of the TPA2013D1, use 75-μm to 100-μm tracewidths at the solder balls. Run IN– and IN+ traces side-by-side to maximize common-mode noise cancellation.

12.1.2 Pad SideIn making the pad size for the WCSP balls, use nonsolder mask defined (NSMD) land. With this method, thesolder mask opening is made larger than the desired land area, and the opening size is defined by the copperpad width. Figure 37 and Table 9 show the appropriate diameters for a WCSP layout.


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Copper Trace Width

Solder Pad Width

Solder Mask Opening

Copper Trace ThicknessSolder Mask Thickness

26




Layout Guidelines (continued)

Figure 37. Land Pattern Dimensions

Table 9. Land Pattern DimensionsSOLDER PADDEFINITIONS COPPER PAD SOLDER MASK

OPENINGCOPPER

THICKNESSSTENCILOPENING

STENCILTHICKNESS

Nonsolder maskdefined (NSMD)

275 μm(+0.0, –25 μm)

375 μm(+0.0, –25 μm)

1 oz max (32 μm) 275 μm x 275 μm Sq.(rounded corners)

125 μm thick

NOTES:1. Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside

the solder mask opening. Wider trace widths reduce device stand off and impact reliability.2. Recommend solder paste is Type 3 or Type 4.3. Best reliability results are achieved when the PWB laminate glass transition temperature is above the

operating the range of the intended application.4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in

thermal fatigue performance.5. Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.6. Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically

etched stencils results in inferior solder paste volume control.7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional

component movement due to solder wetting forces.


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OUT -

Via to Ground Plane

Top Layer Ground Plane Top Layer Traces

Pad to Top Layer Ground Plane

Decoupling capacitor

placed as close as

possible to the device

Via to Bottom Layer

2.2µH

Bottom Layer Traces

Via to Power Supply Plane

A1

B1

C1

D1

A2

C2

D2

A3

B3

D3

A4

B4

C4

D4

B2

-IN IN +

SDb

SDd

GAIN

10µF

10µF

0.1µF

Input capacitors

placed as close as

possible to the device Differential Routing of

input and output

signals is

recommended

OUT +


placed as close as


TPA2013D1

50KΩ 500KΩ

Resistors placed as close

as possible to the device

C3

27




12.2 Layout Examples

Figure 38. TPA2015BGA Layout


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JA1 1

= = = 80.64 C/WDerating Factor 0.0124

q °

Via to Bottom Ground Plane

Top Layer Ground Plane Top Layer Traces

Pad to Top Layer Ground Plane


placed as close as


Via to Bottom Layer

Bottom Layer Traces

Via to Power Supply Plane

OUT +

TPA2013D1

1

2

3

4

5

15

14

13

12

11

6

20

7 8 9 10

19 18 17 16

OUT +

OUT +

OUT -

OUT -

IN - IN +

1µF1µF

Differential Routing of

input and output

signals is

recommended

GAIN

SDd

SDb

Thermal Pad


placed as close as


Input capacitors

placed as close as


1µF

1µF

10µF

2.2uH

50KΩ

500KΩ

28




Layout Examples (continued)

Figure 39. TPA2015QFN Layout

12.3 Efficiency and Thermal ConsiderationsThe maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factorsfor the YZH and RGP packages are shown in Dissipation Ratings. Apply the same principles to both packages.Using the YZH package, and converting this to θJA:

(8)

Given θJA of 80.64°C/W, the maximum allowable junction temperature of 150°C, and the maximum internaldissipation of 0.317 W (VDD = 3.6 V, PO = 1.7 W), the maximum ambient temperature is calculated withEquation 9:


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A J JA DmaxT Max = T Max P = 150 80.64 (0.317) = 124 C- q - °

29




Efficiency and Thermal Considerations (continued)

(9)

Equation 9 shows that the calculated maximum ambient temperature is 124°C at maximum power dissipationunder the above conditions. The TPA2013D1 is designed with thermal protection that turns the device off whenthe junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more resistive than4-Ω dramatically increases the thermal performance by reducing the output current and increasing the efficiencyof the amplifier.


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30




13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products DisclaimerTI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOTCONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICESOR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHERALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.1.2 Device Nomenclature

13.1.2.1 Boost TermsThe following is a list of terms and definitions used in the boost equations found in this document.

C Minimum boost capacitance required for a given ripple voltage on VCC.L Boost inductorfboost Switching frequency of the boost converter.ICC Current pulled by the Class-D amplifier from the boost converter.IL Average current through the boost inductor.R1 and R2 Resistors used to set the boost voltage.VCC Boost voltage. Generated by the boost converter. Voltage supply for the Class-D

amplifier.VDD Supply voltage to the IC.ΔIL Ripple current through the inductor.ΔV Ripple voltage on VCC due to capacitance.

13.2 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

13.3 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

13.4 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

13.5 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.


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http://www.ti.com/lit/pdf/SLYZ022

31




14 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.


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PACKAGE OPTION ADDENDUM

www.ti.com 1-Feb-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPA2013D1RGPR ACTIVE QFN RGP 20 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 BTI

TPA2013D1YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS& no Sb/Br)

SNAGCU Level-1-260C-UNLIM -40 to 85 BTH

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

http://www.ti.com/product/TPA2013D1?CMP=conv-poasamples#samplebuy

http://www.ti.com/product/TPA2013D1?CMP=conv-poasamples#samplebuy

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PACKAGE OPTION ADDENDUM


Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPA2013D1RGPR QFN RGP 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

TPA2013D1YZHR DSBGA YZH 16 3000 180.0 8.4 2.35 2.35 0.81 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPA2013D1RGPR QFN RGP 20 3000 367.0 367.0 35.0

TPA2013D1YZHR DSBGA YZH 16 3000 182.0 182.0 20.0

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 2

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D: Max =

E: Max =

2.31 mm, Min =

2.31 mm, Min =

2.25 mm

2.25 mm

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