29

MODULAR MISSILE BORNE COMPUTERS

R. Ramseyer, R. Arnold, H. Applewhite and R. BergHoneywell Systems and Research Center

Minneapolis, MinnesotaA

The increasing real time signal and data processing loads on-board

BMD interceptors cannot be met with currently available and flyable

processors. The Modular Missile Borne Computer is being developed

to provide a solution to that problem through the use of a

collection of microprocessors in a distributed processing system.

This paper discusses the Modular Missile Borne Computer's architecture

with emphasis on how that architecture evolved from a careful

analysis of both the physical constraints and the processing require-

ments. The development techniques used .are generally applicable

to real-time data processing systems and have resulted in the

achievement of one of our most significant design goals. This

goal is a modular, flexible, extensible system capable of adapting

to evolving BMD problems as well as others where an ultra-high

performance distributed processor is desirable.

The general objective for the MMBC program is the development of

a data processing system which lends itself readily to system

growth, reconfiguration and changes in application or environment.

Given the constraints and requirements imposed by the .BMD threat,

scenarios and environmental considerations, four driving architectural

considerations result:

• The required processing is real time.

• There is a massive quantity.of data and it is received

at a rapid rate.

• A high degree of modularity, flexibility and potential

for growth is desired in MMBC.

• MMBC must be capable of performing in an extremely hostile

operating environment (e.g. shock, vibration, temperature,

nuclear).

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HIGH LEVEL PROCESSOR STRUCTURE

OBJECTS

SAMPLEDDATA STREAM

TOTAL DP LOAD IS COMPOSED OFMANY SMALL, INDEPENDENT LOADS

tOO IK IOK 100K 1M 10M IOOM 1000Mi I I . . I I I IHSTPERSEC

CURRENTMICROPROCESSORSTATE-OF-ART

231

MODULAR MISSILE-BORNE COMPUTERS

OBJECTIVE: INVESTIGATE ADVANCED PREPROCESSING TECHNOLOGY & THE APPLICATIONOF MODULAR, FLEXIBLE, EXTENDABLE MICROCOMPUTER ARRAYS TO PERFORMTHE REAL TIME DATA PROCESSING NECESSARY ON BOARD A BMD INTERCEPTOR.

IDS/DP

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MOSAICSENSOR

4 ARITHMETICALLYENHANCED GP'S

HARDWIREFOCAL PLANEPROCESSOR

RATIONALE:

PREPROCESSING& BULK FILTERING

PULSE MATCH

TRACKING & DISCRIMINATION

GUIDANCE NAVIGATION & CONTROLADVANCES IN INTERCEPTOR & TECHNOLOGY AS WELL AS INCREASINGCOMPUTATION OF BMD FUNCTIONS ON BOARD IMPOSE REQUIREMENTS ON THEDATA PROCESSOR THAT CANNOT BE MET BY CONVENTIONAL COMPUTER ARCHI-TECTURES. MODULAR, FLEXIBLE, AND EXTENDABLE COMPUTER STRUCTURESARE REQUIRED TO MEET THE NEEDS OF THE FLUID AND RAPIDLY EVOLVINGBMD SYSTEMS.

BENEFITS OF MICROPROCESSORS

ALLOW MAXIMUM USE OF LSIC HARDWARE- MINIMIZES SIZE/WEIGHT/POWER/INTERCONNECTS

SPECIAL PURPOSE OPERATION CAN BE ACHIEVED THROUGH MICROPROGRAMMING

SIMULTANEOUS OPERATION OF MANY REAL TIME HARDWARE UNITS DRASTICALLYREDUCES NEED FOR MULTIPROGRAMMING- REDUCED SOFTWARE COST- REDUCED OVERHEAD TIME

ALLOWS MAXIMUM MODULARITY TO BE ACHIEVED WHICH IMPROVES- FAULT TOLERANCE- FLEXIBILITY/ALTERABILITY

232

APPROXIMATECAPABILITIES AND REQUIREMENTS

PROCESSING SECTION

PREPROCESSING ANDBULK FILTERING

DMX TO PULSE

MATCH

PULSE MATCH

TRACKING AND

DISCRIMINATION

GUIDANCE NAVIGATION

AND CONTROL

PROCESSORCONFIGURATION

14 SIMD

(1 TO 3 MIPS EA)

4GPW/SPECIALARITHMETIC(15 MIPS FOR PULSEMATCH; 1 MIPSOTHERWISE)

3GP

(1 MIPS EACH)

1GP

(500 KIPS)

REQUIREMENT

22 MIPS

43 MIPS

151 KIPS

185 KIPS

CAPABILITY

-40 MIPS*

45 MIPS

3 MIPS

500 KIPS

TOTAL CAPACITY 88.5 MIPS

•HIGH THROUGHOUT REQUIRED TO ABSORB OVERHEAD AND SATISFY REAL-TIME RESPONSE REQUIREMENT.

EACH COMPUTER IN MMBC IS "TUNED" TO PERFORM WELL IN ITS AREA OF APPLICATION.E.G., MULTIPLE DATA STREAM PROCESSORS IN BULK FILTERING; PIPELINED, FASTARITHMETIC UNIT IN PULSE MATCH.

CHARACTERISTICS OF HARDWARE MODULES

GENERAL PROCESSING ELEMENT (16 BITS) 1 MIPS

SIMDPE(3ALUS) 3 MIPS

VOA PROCESSOR 15 MIPS/5 MIPS

LOCAL MEMORY (3 PORT RAM)

READ ACCESS TIME 270 ni

WRITE ACCESS TIME 75ns

COMMON BULK MEMORY

READ 375ns

WRITE 140 ns

CYCLE 425 n$

GLOBAL BUS (3 BUSES)

TRANSFER RATE 1 MWOROS/S

1MWORDS/S

CAN HANDLE 40 K TRACKS/SEC/GLOBAL BUS

UTILIZATION 60%

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EXAMPLE OF HYBRID MMBC SYSTEM

POWERCONVERSION

SYSTEM

14.5"

SIMDJM

SIMP #2

S]MD_#3

SIMP #4

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PROCESSING S]MD_#7

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SIMP #12

SJMD_#13

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COMMON (\ CBMB_OOJ<SO,1<u2]195J<W_gRD_S)

BULK I CBM BOOKS 3. 4. 5 (195K WORDS) | 3"

_CBM §pOJKSj>,7,_8 (195J< WORDS) I i

Nl_ CBM BOOKS 9, 10, 11 (195K WORDS) T 29'

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DISCRIMINATION P.E.

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AND JAfiGElTaACJINJ! CJ. I 4.5

GNC | TRACK FILE MEMORY

_GN& CP.E^

NLJ I/O FUNCTIONS

POWER CONVERTER #1 (1KW DELIVERED POWER)

POWER CONVERTER #2 (1KW)

POWER CONVERTER #3 (1KW)

POWER CONVERTER #4 (1KW)

8.0"

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