2nd korea vietnam joint workshop of solid-state circuits ... · 2nd korea–vietnam joint workshop...
TRANSCRIPT
January 04 - 06, 2017
Meeting Room 2, 6th floor, Main Building, University of Technology and Education,
Ho Chi Minh City, Vietnam
https://isdlute.wordpress.com/home/
Co-organized by Institute of Korean Electrical and Electronics Engineers (IKEEE), Korea
and Department of Electrical and Electronics Engineering. University of
Technology and Education, HCMC, Vietnam (FEEE-HCMUTE)
2nd Korea–Vietnam Joint Workshop of
Solid-State Circuits and Systems
2nd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
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ORGANIZING COMMITTEE
Kyeong-Sik Min (Kookmin University, Seoul, Korea)
Van Hieu Nguyen (University of Science, VNU, HCMC, Vietnam)
Thuyen Van Ngo (University of Technology and Education, HCMC, Vietnam)
Minh Tam Nguyen (University of Technology and Education, HCMC, Vietnam)
Chi Kien Le (University of Technology and Education, HCMC, Vietnam)
An Quoc Hoang (University of Technology and Education, HCMC, Vietnam)
Minh Huan Vo (University of Technology and Education, HCMC, Vietnam)
INVITED SPEAKERS
Minkyu Song (Dongguk University, Seoul, Korea)
Jongsun Kim (Hongik University, Seoul, Korea)
Yong Moon (Soongsil University, Seoul, Korea)
Yongseo Koo (Dankook University, Seoul, Korea)
Kwang-Yeob Lee, Seokyeong University, Seoul, Korea
Kyeong-Sik Min (Kookmin University, Seoul, Korea)
Van Hieu Nguyen (University of Science, VNU, HCMC, Vietnam) Tuan Khanh Nguyen (ICDREC, HCMC, Vietnam)
Bach Thang Phan (University of Science, VNU, HCMC, Vietnam)
Vinh Ai Dao (University of Technology and Education, HCMC, Vietnam)
Minh Huan Vo (University of Technology and Education, HCMC, Vietnam)
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WORKSHOP PROGRAM Wed, January 04, 2017
17:00 - 19:00 PM Reception
Thurs, January 05, 2017
Visiting ICDREC
09:30 - 09:45 AM Introducing the attendees and networking
09:45 - 10:05 AM IKEEE’s presentation
10:05 - 10:25 AM ICDREC’s presentation
10:25 - 11:10 AM Discussion about the next year’s joint workshop, etc
Fri, January 06, 2017 10:00 - 10:20 AM Registration
10:20 - 10:30 AM
Opening address, Dr. Van Thuyen Ngo
Vice President of University of Technology and Education, HCMC,
Vietnam
10:30 - 10:50 AM
Design of a 3-dimensional CMOS image sensor with a bit-configurable
pixel matrixes
Minkyu Song, Dongguk University, Seoul, Korea
10:50 - 11:10 AM A study of low-power dual-band smart tag
Yong Moon, Soongsil University, Seoul, Korea
11:10 - 11:30 AM
Design of clocking circuits for future memory systems
Jongsun Kim, Hongik University, Seoul, Korea
Yongseo Koo, Dankook University, Gyeonggi-do, Korea
11:30 - 11:50 AM
Sequential memristor crossbar
Kyeong-Sik Min, Kookmin University, Seoul, Korea
Kwang-Yeob Lee, Seokyeong University, Seoul, Korea
12:00 - 13:30 PM Lunch
13:30 - 13:50 PM
A Design of 400 MHz VCO and PA for UHF transceiver using direct
modulation transmitter architecture
Khanh Nguyen Tuan, Integrated Circuit Design Research and Education
Center (ICDREC)
13:50 - 14:10 PM
The study of multi-quantum well (MQWs) of LED structures and
fabrication process of far-red and blue LED for the Hi-tech agriculture
Hieu Van Nguyen, University of Science, VNU, HCMC, Vietnam
14:10 - 14:30 PM
Photoluminescence study on defects on thermoelectric properties of
Indium and Gallium dually-doped ZnO thin films
Bach Thang Phan, Vietnam National University, HCMC, Vietnam
14:30 - 14:50 PM
Beyond 22% efficient silicon heterojunction solar cells with industrially
feasible rear emitter
Vinh Ai Dao, University of Technology and Education,
HCMC, Vietnam
14:50 - 15:10 PM
New binary memristor crossbar architecture based multilayer neural
network
Huan Minh Vo, University of Technology and Education, HCMC,
Vietnam
15:10 - 15:45 PM Poster session
15:45 - 16:00 PM Closing address
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DESIGN OF A 3-DIMENSIONAL CMOS IMAGE
SENSOR WITH A BIT-CONFIGURABLE PIXEL
MATRIXES
Minkyu Song
Department of Semiconductor Science, Dongguk University, Seoul, Korea
Design of a three-dimensional CMOS image sensor (CIS) with a bit-configurable pixel
matrixes is discussed. A bit-configurable CIS pixel matrix with RGB and Infrared (IR)
color filters is adopted to implement an 3-dimensional image. Further, in order to
compensate the light density between RGB and IR, a novel single-slope ADC has a
variable bit-resolution performance. The 3-dimensional CIS has 4 different bit
resolutions for IR pixel, such as 12-bit, 10-bit, 8-bit and 6-bit. The scheme of ADC is a
two-step single-slope (TS SS) type which has a maximum resolution of 12-bit. The
proposed 3-dimensional CIS has a 100MHz clock, and it has been designed with 0.18μm
CIS technology.
Acknowledgement:
This research was supported by Basic Science Research Program through the National
Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and
Technology (2015R1D1A1A01058193).
Minkyu Song received the B.S. and M.S., and Ph.D. degree in Electronics Engineering
from Seoul National University, Korea in 1986, 1988 and 1993, respectively. From 1993
to 1994, he was a researcher at Asada Lab., VDEC, University of Tokyo, Japan where he
worked in the area of low power VLSI design. From 1995 to 1996, he was a researcher in
the CMOS Analog Circuit Design Team of Samsung Electronics, Korea. Since 1997, he
has been a professor at University of Dongguk, Korea. He is a member of IEEE and
IEIE. His major interest is design of CMOS analog circuits, mixed-mode circuits, and
low power digital circuits.
10:30 AM - 10:50 AM, Jan 06, 2017
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A STUDY OF LOW-POWER DUAL-BAND SMART
TAG
Yong Moon
School of Electronic Engineering, Soongsil University, Seoul, Korea
NFC (Near Field Communication) and RFID (Radio Frequency Identification) are used
in many applications like logistics and distribution systems nowadays. But current tags
are designed only for a specific system, so it will be very useful if two or more tags are
integrated in a single chip. So we have designed the Dual band Smart Tag which could
recognize and demodulate the signal of the UHF band (900MHz) and the HF band
(13.56MHz, NFC) respectively. The proposed Dual band Smart tag’s NFC Analog Front-
End is designed to dissipate low power and the digital block is verified using the Arduino
Uno. The Dual band Smart tag chip has been designed and fabricated using the SMIC
-Poly 4-Metal CMOS Process.
Yong Moon received the B.S., M.S., and Ph.D. degrees from the department of
Electronics Engineering, Seoul National University, Seoul, Korea, in 1990, 1992 and
1997, respectively. From 1997 to 1999, he was with LG Semicon co., Ltd., where he
contributed to senior research engineer in analog circuit design group. Since 1999, he has
been with Soongsil University, Seoul, Korea, where he is a professor in School of
Electronic Engineering. His research interests include PLL, low-power circuit, mixed
signal IC and RF circuits.
10:50 AM - 11:10 AM, Jan 06, 2017
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DESIGN OF CLOCKING CIRCUITS FOR
FUTURE MEMORY SYSTEMS
Jongsun Kim
School of Electronic and Electrical Engineering, Hongik University, Seoul, Korea
Yongseo Koo
Dept. of Electronic and Electrical Engineering, Dankook University, Gyeonggi-do, Korea
One of the main challenges in the design of high-speed DRAMs is the implementation of
low-power on-chip clocking circuits such as delay-locked loops (DLLs) and duty-cycle
corrector (DCCs). The double data rate 4 (DDR4) synchronous dynamic random access
memory (SDRAM) currently being used in top line computing systems operates at 1.6
GHz and offers data rates of 3.2 Gbps/pin. To achieve faster performance beyond DDR4,
next-generation SDRAMs require all-digital DLLs that can operate up to 3.2 GHz or
higher while maintaining fast locking, low power, small area, and low-jitter
performances. A new low-power, fast-locking DLL that uses a disposable time-to-digital
converter (TDC) is presented for future memory systems. To achieve fast locking and
high frequency operation, the proposed DLL utilizes a new hybrid (TDC + binary +
sequential) search algorithm that results in a fast locking time of 11 clock cycles without
the false lock and harmonic lock problems. By minimizing the intrinsic delay of the
digital delay line, the proposed DLL achieves an operating frequency range of 1.5-to-5.0
GHz which is higher than that of the current state-of-the-art all-digital DLLs. The DLL is
fabricated in a 65-nm CMOS process and it achieves a peak-to-peak (p-p) output clock
jitter of 14 ps (with a p-p input clock jitter of 8 ps) at 5 GHz. The DLL consumes 6.9 mW
at 1 V and occupies an active area of 0.025 mm2. Also, a new digital DCC architecture
that utilizes a feedback delay element (FDE)-based duty cycle amplifier is presented.
Acknowledgement:
This work (C0396252) was supported by Business for Cooperative R&D between
Industry, Academy, and Research Institute funded Korea Small and Medium Business
Administration in 2016. And This work was supported by Institute for Information &
communications Technology Promotion(IITP) grant funded by the Korea
government(MSIP) (No.B0186-16-1001, Form factor-free Multi Input and output Power
Module Technology for Wearable Devices).
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Jongsun Kim From 1994 to 2001, Prof. Jongsun Kim was with Samsung Electronics as a
senior research engineer in the DRAM Design Team, where he worked on the design and
development of DDR SDRAMs, SGDRAMs, Rambus DRAMs, and other specialty
DRAMs. He received the Ph.D. degree from the Electrical Engineering Department,
University of California, Los Angeles (UCLA) in 2006 in the field of Integrated Circuits
and Systems. He was a Postdoctoral Fellow at UCLA from 2006 to 2007. After his research
at UCLA, he returned to South Korea to continue his memory design career at Samsung,
where he was in charge of developing the next generation high-speed DDR3/DDR4
DRAMs. Dr. Kim joined the School of Electronic & Electrical Engineering, Hongik
University in March 2008. Prof. Kim’s research interests are in the area of high-
performance mixed-mode (analog & digital) circuits and systems design. His current
research areas include high-speed and low-power transceiver circuits for chip-to-chip
communications, clock recovery circuits (PLLs/DLLs/CDRs/SerDes), frequency
synthesizers, low-power and high-bandwidth memories (DRAM/FLASH), power-
management ICs (DC-DC converters), low-power neuromorphic circuits for AI, and low-
power sensors and transceivers for IoT.
Yongseo Koo From 1983 to 1993, Prof. Yongseo Koo was with Samsung Electronics as a
senior research engineer in the Process Team, where he worked on the design and
development of BJT Process. He received the Ph.D. degree from the Electrical Engineering
Department, University of Sogang, Seoul. 1993 to Aug 2009, he joined the faculty of
Seokyeoung University, Seoul, Korea. Engineering. And In September 2009, he joined the
department of Dankook University, where he is currently a Professor in the School of
Electronics and Electrical. His current research areas include ESD Protection Circuit,
Power semiconductor and PMIC.
11:10 AM - 11:30 AM, Jan 06, 2017
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SEQUENTIAL MEMRISTOR CROSSBAR
Kyeong-Sik Min
School of Electrical Engineering, Kookmin University, Seoul, Korea
Kwang-Yeob Lee
Department of Computer Engineering, Seokyeong University, Seoul, Korea
Most of human’s intelligent behaviors such as inference, prediction, anticipation, etc. are
based on the processing of sequential data from human’s sensory systems. Thus, a
sequential memory that can process sequential information is very essential to mimic
brain’s intelligent behaviors. In this paper, we propose a new sequential memristor
crossbar which is regarded as the first memristor circuit that copes with the sequential
data. The new crossbar is composed of two layers which are the base layer and the
sequential one, respectively. The base layer can recognize only static items one by one.
The sequential layer can detect the serial order of items and find the best match with the
detected sequence among many reference sequences stored in the memristor array. The
new crossbar can recognize the tested sequences of items as well as 88.6% on average
for the memristance variation of 0%. The variation tolerance is also tested from 0-%
variation to 20-% variation in the proposed sequential crossbar.
Acknowledgement:
The work was financially supported by NRF-2011-0030228, NRF-2015R1A5A7037615,
KIST Open Research Program (ORP), and Industrial Strategic Technology Development
program of MOTIE/KEIT (10052653) , and the Industrial Core Technology
Development Program (10049192, Development of a smart automotive ADAS SW-SoC
for a self-driving car) funded By the Ministry of Trade, industry & Energy. The CAD
tools were supported by IC Design Education Center (IDEC), Daejeon, Korea.
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Kyeong-Sik Min received the B.S. degree in Electronics and Computer Engineering
from Korea University, Seoul, Korea, in 1991, and the M.S.E.E. and Ph. D. degrees in
Electrical Engineering from Korea Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 1993 and 1997, respectively. In 1997, he joined Hynix
Semiconductor Inc., where he was engaged in the development of low-power and high-
speed DRAM circuits. From 2001 to 2002, he was a research associate at University of
Tokyo, Tokyo, Japan, where he designed low-leakage memories and low-leakage logic
circuits. In September 2002, he joined the faculty of Kookmin University, Seoul, Korea,
where he is currently a Professor in the School of Electrical Engineering. He was a
visiting professor at University of California, Merced, from Aug. 2008 to July 2009.
Prof. Min served on various technical program committees such as Asian Solid-State
Circuits Conference (A-SSCC), International SoC Design Conference (ISOCC), and
Korean Conference on Semiconductors (KCS). He and his students received IDEC CAD
& Design Methodology Award (2011), IDEC Chip Design Contest Award (2011), and
IDEC Chip Design Contest Award (2012). He is a member of Institute of Electrical and
Electronics Engineers (IEEE), Institute of Electronics Engineers of Korea (IEEK), and
Institute of Electronics, Information, and Communication Engineers (IEICE) in Japan.
His research interests include low-power VLSI, memory design, and power IC design.
Kwang-Yeob Lee received the B.S. degree in Electronics Engineering from Sogang
University, Seoul, Korea, in 1985, and the M.S.E.E. and Ph. D. degrees in Electrical
Engineering from Yonsei University, Seoul, Korea, in 1987 and 1994, respectively. In
1989, he joined Hynix Semiconductor Inc., where he was engaged in the development of
System Semiconductor. In September 1995, he joined the faculty of Seokyeong
University, Seoul, Korea, where he is currently a Professor in the Department of
Computer Engineering. He is a member of Institute of Electrical and Electronics
Engineers (IEEE), Institute of Electronics Engineers of Korea (IEEK), and Institute of
Electronics, Information, and Communication Engineers (IEICE) in Japan. His research
interests include System on Chip (SoC), Graphics Processor Unit(GPU), and Embedded
Processors.
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A DESIGN OF 400 MHZ VCO AND PA FOR UHF
TRANSCEIVER USING DIRECT MODULATION
TRANSMITTER ARCHITECTURE
Tuan Khanh Nguyen
Integrated Circuit Design & Education Research Center, HCMC, Vietnam
This paper presents the design of the RF transmitter of UHF Transceiver using 180-nm
CMOS technology at 400 MHz. The design of RF transmitter in this paper using direct
modulation architecture which includes VCO, buffer, divider and class AB of the power
amplifier. The results of the PA are maximum output power of 12.9 dBm, OP1dB of 11.7
dBm, PAE of 6.79 % with 3 bits power control and including LDO, bonding wire effect.
Acknowledgement:
The author wishes to thank Director Ngo Duc Hoang, Prof. Dang Luong Mo, Mr. Nguyen
Duc Nguyen and Mr. Thien Tran Vuong Trong for their kind help and advices. Thanks to
Ministry of Science and Technology, Viet Nam and VNU HCM for the grant in the form of
a state-level research project with code number: DAKHCN.2014/DT-03
Tuan Khanh Nguyen received the M.S. degrees in electrical engineering from HCM
University of Technology. Now he is the manager of RF department of ICDREC. His
research interests include transceiver architectures, PA, VCO & PLL design.
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THE STUDY OF MULTI-QUANTUM WELL
(MQWS) OF LED STRUCTURES AND
FABRICATION PROCESS OF FAR-RED AND
BLUE LED FOR THE HI-TECH AGRICULTURE
Hieu Van Nguyen
University of Science, VNU, HCMC, Vietnam
The advantage of III-nitride materials are a direct band gap and cover a wide wavelength
range of ultraviolet to visible red [3]. However, it was difficult to get the large power of
UV light. The UVLEDs are well-known, such as compact circuit, high efficiency, short
standby, low heat generation, no mercury used and narrow spectrum. In this work, the
multi-quantum wells (MQWs) of UVLED were studied in the range of violet wavelength
by the means of SiLENSe [1-2],[4-5] which have successfully fabricated by MOCVD
technology. Moreover, nowadays, the LEDs can be used as well as the green agriculture.
By the study of SiLENSe, we found out the 2 structures LED have wavelength are 630-
660nm and 690nm with the optimized structural parameters of LED for low cost of
fabrication. They were used to simulate with COMSOL to study the electrode shapes
which have optimal resistance parameters for the photolithography of fabricating process.
The change of parameters such as the time of baking, the time of exposing and time of
development in during experimental process depending on the sample size, we find out
the photolithography process with the best optimal parameters to fabricate of UVLED
die. Furthermore, the application of far-red LEDs in hi-tech agriculture can be studied the
growth of the lettuce plant in our RCHAA which were cooperation with LAFRTC
(CBNU, Korea).
Hieu Van Nguyen received his Ph.D degree in Physics from Graduate School of Science,
Osaka University, Japan. He became lecturer in faculty of Physics, University of Science
in 2007. Since May 2007, He is head of Department of Physics and Electronic
Engineering(Faculty of Physics and Engineering Physics). From Dec 2008 to Sep.2010,
he was appointed as Dean of Faculty of Electronics and Telecommunications in
University of Science. From Feb, 2010 to Apr. 2011, He was invited as visiting professor
for the project of UVLED (Ritsumeikan University, Japan). Moreover, since 2011, he has
also appointed as expert and inviting researcher for Lab of Semiconducting Technology
(Saigon Hi-Tech Park) for microelectronic projects.
Beside of professor position, since Dec., 2012, he was also appointed as head Office of
International Relations-Projects Management in University of Science-VNUHCM.
Therefore, he is a person in charge to enhance to relationships between University of
Science and other universities in world wide.
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Moreover, He is a member of Institute of Electrical and Electronic Engineering in Japan
(Since 2012); member of editor board of Korean Institution of Electrical and Electronic
EngineerKIEEE (Since Jan2013); member of Physics Society of Vietnam (Since 2008),
vice chair of the National Development Microelectronics program in Hochiminh City
(since Oct 2012).
In Nov. 2008, he took the International Dean Course ‘s South East Asian which organized
by DAAD (Germany). He became an alumnus and co-coordinator of DAAD for
education program in Hochiminh City. He was also a guest of the 2nd Roundtable under
the European Union – Asian Higher education Platform, Organization by EUA & DAAD
(Belgium; Jul, 2009). He was also an alumnus of Osaka University as JUACH, JAV,…in
Vietnam.
He was also invited talk in ASPA2013 (in SHTP, Vietnam), 4S international Conference
2010, 2012 (10th anniversary of SHTP), SHTP Annual Conference2014, The 41st
Congress on Science and Technology of Thailand (STT41), SHTP Annual
Conference2016. member of Scientific council of Saigon Hi-Tech Park (Since Feb2013);
semiconductor experts for Vietnam-United Photonics Co, Ltd in Vietnam.
Yearly, he has many lectures for students in Universities other institutes. Since 1995, He
was scientific supervisors for more than 34 bachelor and 20 master theses. He had more
than 30 talks in domestic and international conferences. His research group had around 40
published papers in the field of applied physics, magnetism, semiconducting devices,
MEMS, microelectronics… from 2004 up to now. He was also a program chair/ program
Committee,…of many Seminars, International workshops, Conferences: VJSE2005,
VJSE2006 (Japan),4S Forum (2012), IWTDMT2013, and 4S (2014), Nanomata.
13:50 PM - 14:10 PM, Jan 06, 2017
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PHOTOLUMINESCENCE STUDY ON DEFECTS
ON THERMOELECTRIC PROPERTIES OF
INDIUM AND GALLIUM DUALLY-DOPED ZNO
THIN FILMS
Bach Thang Phan
University of Science, Vietnam National University, HCMC, Vietnam
In this paper, we investigated the effect of single and multi-dopants on thermoelectrical
properties of the host ZnO films. Incorporation of single dopant Ga in the ZnO films
improved the conductivity and mobility but lowered the Seebeck coefficient. Dual Ga and
In doped ZnO thin films shows slightly decreased electrical conductivity but improved
Seebeck coefficient. The variation of thermoelectric properties is discussed in terms of
film crystallinity, which is subjected to the dopants’ radius. Small amount of In dopants
with large radius may introduce localized regions in the host film, affecting
thermoelectric properties. The point defects are determined through XPS, PL techniques.
Bach Thang Phan is Vice Dean of Faculty of Materials Science at University of Science
(US), VNUHCM. He received the BS degree in Physics (Applied Physics) from US,
VNUHCM, in 2001. He received the PhD degree in Electronic Materials in
SungKyunKwan University, South Korea (2009) and he became an Associate Professor
in Physics at US, VNUHCM (2015). His research focuses on nanostructured materials
applied in Resistive memory (RERAM), Memristive biosensor and thermoelectric
conversion.
14:10 PM - 14:30 PM, Jan 06, 2017
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BEYOND 22% EFFICIENT SILICON
HETEROJUNCTION SOLAR CELLS WITH
INDUSTRIALLY FEASIBLE REAR EMITTER
Vinh Ai Dao
Faculty of Applied Sciences, University of Technology and Education, HCMC, Vietnam
A higher energy conversion efficiency was achieved for a rear-emitter amorphous silicon
(a-Si:H)/crystalline (c-Si) heterojunction (SHJ) solar cells as compared with those of front-
emitter SHJ solar cells. Because of an improvement in fill factor (FF) and short-circuit
current density (Jsc), the energy conversion efficiency of 22.03% (Open-circuit voltage
(Voc) = 739.459 mV, FF = 77.190, and Jsc = 38.596 mA/cm2) was achieved with full
square 6-inch rear-emitter SHJ solar cells fine-line screen-printing. By varying both finger
spacing and finger width of the front side metal grid electrode, the FF and Jsc loss were
investigated. In case of the rear emitter design, a substantial part of the lateral carrier
transport is shifted from the front side TCO into the absorber, thus, lowering the effective
sheet resistance of the front side. Because of the advantage on lateral current path, the
trade-off between the optical and electrical loss of the finger electrodes are less pronouced
for a rear emitter cell design compared to the standard front emitter cell design. The
approach presented here can serve as a reasonable method to improve the conversion
efficiency for SHJ solar cells with less silver consumption, hence, cost-effectiveness.
Vinh-Ai Dao received the B.S. and the M.S degree in Physics from University of Science,
Vietnam National University Ho Chi Minh City, Vietnam in 1999 and 2005, respectively, the
Ph.D. degree from Sungkyunkwan University in 2011. Since 2016, he has been a lecturer in
the Faculty of Applied Sciences at HCMC University of Technology and Education.
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NEW BINARY MEMRISTOR CROSSBAR
ARCHITECTURE BASED MULTILAYER
NEURAL NETWORK
Minh Huan Vo
University of Technology and Education, HCMC, Vietnam
A new binary memristor crossbar architecture based multilayer neural networks is
proposed. In which, the memristor crossbar circuit acts as the weights of the network
combined with the activation function circuit of the network to determine the output. In
the crossbar architecture, the weights were arranged diagonally and divided into 2 arrays
according to positive and negative weights. A speech recognition application for 5 vowels
is implemented using the proposed architecture. The result shows that the average
recognition increases from 94% to 96.6% over 1,000 audio samples. A statistical table on
the number of bits of the input and the weight shows that the recognition rate and the
number of the memristors increase correspondingly to the number of bits used. From the
Monte Carlo simulation, the recognition rate of the binary memristor crossbar is
decreased slightly from 94% to 93.7%, though the percentage variation in memristance is
increased from 1% to 15%.
Minh Huan Vo received the B.S. and M.S.E.E. degrees in Electronics and
Communication Engineering from the Ho Chi Minh City University of Technology,
Vietnam in 2005 and 2007 and Ph.D. degree in Electronics Engineering from Kookmin
University, Seoul, Korea in 2013. He is currently working as a lecturer at the Faculty of
Electrical and Electronics Engineering, University of Technology and Education, Ho Chi
Minh City, Vietnam. His current research interests include low power design optimization
and neuromorphic computation using emerging technology like memristive devices.
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LIST OF SPONSORS
Keysight Technologies Singapore Pte. Ltd.
Vietnam-Japan International Orientation &
Education Center
Integrated Circuit Design & Education Research
Center
Renesas Design Vietnam Co., Ltd.
Bosch Vietnam Co., Ltd.
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DESIGN AND SIMULATION OF CMOS BANDGAP VOLTAGE
REFERENCE
Tran Huu Thong, Vinh Nguyen and Cuong Huynh
University of Science, VNU, HCMC, Vietnam
This paper shows the design method and simulation results of a CMOS Bandgap Voltage
Reference. This CMOS Bandgap Voltage Reference is designed and simulated in 130nm
CMOS technology using Cadence IC design tool. The simulation result shows this
bandgap circuit’s output voltage is about 600mV in temperature range from 0oC to
125oC, with voltage supply can change from 950mV to 1.5V. The Temperature
Coefficient (TC) of our bandgap circuit is 17 ppm/oC and power consumption is about
150µW.
Tran Huu Thong received B.S. and M.S. degrees in Physics and Electronics from Ho
Chi Minh City University of Science in 2011 and 2015, respectively. Currently, he is a
teaching assistant in Department of Physics and Electronics Engineering, Faculty of
Physics and Engineering Physics, Ho Chi Minh City University of Science.
Vinh Nguyen received the Master degree in Electrical Engineering from Ho Chi Minh
City University of Technology, in 2015. Currently, he is conducting research in
laboratory of Telecommunication faculty at Ho Chi Minh City University of Technology.
Cuong Huynh (S'08, M'11) received the B.S. and M.S. degrees in Electrical Engineering
from the Ho Chi Minh University of Technology (HCMUT) in 1998 and 2003,
respectively, and the Ph.D. degree in Electrical Engineering from Texas A&M
University, College Station, Texas, USA in 2012. From 2006 to 2012, he was a research
assistant at the Sensing, Imaging and Communications System Lab, Texas A&M
University where he designed CMOS/BiCMOS multi-band RF ICs for radar and wireless
communications systems working up to 50 GHz. From 2011 to 2012, he joined the
Mobile and Wireless Group at Broadcom Inc., Irvine, CA, USA where he was involved
in the verification of CMOS RF transceivers for cellular communications. Dr. Huynh is
currently a faculty at the Department of Telecommunications Engineering, Faculty of
Electrical and Electronics, HCMUT. His current research interests include Microwave
Engineering and CMOS/BiCMOS Analog/RF Integrated Circuits for sensing and
communication systems.
POSTER
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2nd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
18
MODELS OF MEMRISTORS AND APPLICATION IN DESIGN
LOGIC CIRCUITS
Van Quan Ha
University of Technology and Education, HCMC, Vietnam
Memristors are novel devices, which can be used in applications such as memory, logic,
and neuromorphic systems. Several models for memristors have been developed – the
linear ion drift model, the nonlinear ion drift model, the Simmons tunnel barrier model,
and the ThrEshold Adaptive Memristor (TEAM) model. Another interesting application
for memristive devices is logic circuits. MRL (Memristor Ratioed Logic) - a hybrid
CMOS-memristive logic family - is described. In this logic family, OR and AND logic
gates are based on memristive devices, and CMOS inverters are added to provide a
complete logic structure and signal restoration. Unlike previously published memristive-
based logic families, the MRL family is compatible with standard CMOS logic.
Van Quan Ha received the B.S. degree in Faculty of Electrical and Electronics
Engineering from the Ho Chi Minh City University of Technology and Education
(HCMUTE), Vietnam in 2013. I’m currently working at Samsung Electronics HCMC
complex and learning toward M.S degree in Electronics Engineering at Ho Chi Minh City
University of Technology, Viet Nam. My research interests is analysis about application
of memristor, memristive system, Internet of thing (IoT), and microprocessor.
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2nd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
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IMAGE IDENTIFICATION USING MEMRISTOR IN
NEUROMORPHIC SYSTEM
Pham Sanh, Minh Huan Vo
University of Technology and Education, HCMC, Vietnam
Image identification using memristor in neuromorphic system is a specific application to
demonstrate the usefulness and popularity of memristor in the future by the outstanding
features such as storage capacity, high integration density, low power energy. So, in this
paper I have identified includes 10 images, each image is a 5x6 pixel array, each pixel is
a signal to the system, so there will be 30 signals into the system and these signals pass
through 300 memristors, 300 memristors are divided into 10 memristor arrays, each array
will respectively have 30 memristors, the system will have 10 signals going out from 10
memristor arrays then continue into the integrated block. Integrated block has two
components which are neurons and switch controller. Image identification will perform
three modes is classify, training and test.
Pham Sanh received the B.S. degree in Electrical and Electronics Engineering from the
Ho Chi Minh City University of Technology, Vietnam in 2015. He is currently working
toward M.S degree in Electronics Engineering at Ho Chi Minh City University of
Technology, Viet Nam. His research interests construction system hardware neural
network memristor.
Minh Huan Vo received the B.S. and M.S.E.E. degrees in Electronics and
Communication Engineering from the Ho Chi Minh City University of Technology,
Vietnam in 2005 and 2007 and Ph.D. degree in Electronics Engineering from Kookmin
University, Seoul, Korea in 2013. He is currently working as a lecturer at the Faculty of
Electrical and Electronics Engineering, University of Technology and Education, Ho Chi
Minh City, Vietnam. His current research interests include low-power design
optimization and neuromorphic computation using emerging technology like memristive
devices.
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2nd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
20
DESIGN CIRCUIT ANTI-DEGRADATION DUE TO AGING ON
6T SRAM CELLS
Phuc Nguyen, Ngoc-Khoa Nguyen
University of Technology and Education, HCMC, Vietnam
The threshold voltage drifts induced by Positive Bias Temperature Instability (PBTI) and
Negative Bias Temperature Instability (NBTI) weaken NMOS and PMOS, respectively.
These long-term aging threshold voltage drifts degrade SRAM cell stability, margin and
performance. In this project, we research about SRAM cell and BTI aging effects, so we
propose a circuit use Adaptive Body Bias (ABB) technology for reducing the BTI effect
dependency of threshold voltage. The proposed circuit uses a control circuit and word
line voltage to control the voltage applied to the body of 6T SRAM cell’s transistors. The
proposed ABB reduces the HOLD SNM degradation by 3.03%, READ SNM degradation
by 7.7%, WRITE margin degradation by 15.23%, READ delay by 15.23% but increase
WRITE time by 3.52% compared to the conventional SRAM cell at 108 seconds aging
time.
Phuc Nguyen and Ngoc-Khoa Nguyen are final year students in Faculty of Electrical
and Electronics Engineering from the University of Technology and Education, Ho Chi
Minh City, Vietnam. We are current work in FPT Information System. We try to research
about Power Gating for low power on SRAM and Voltage Stability in regime for storing
data SRAM cell with objective become engineers in IC design industry.
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2nd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
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USING MEMRISTOR TO TRAIN AND GATE ON HARDWARE
Van Tien Nguyen
University of Technology and Education, HCMC, Vietnam
We propose a new architecture which uses only a two memristor instead of four
memristor in brige circuit for training AND gate. Based on working theory of memristor,
we can control memristance by the time. We train AND gate by using perceptron model.
The result is after 6 epoch; the training process is finished. It is similar to the training on
software.
Van Tien Nguyen received the B.S. and M.S. degree in Electronics and Communication
Engineering from the University of Technology and Education, Ho Chi Minh City,
Vietnam in 2014 and 2016. His current research interests include memristor and
memristor - based crossbar for neuromorphic computing systems.
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2nd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
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University of
Technology and
Education,
Ho Chi Minh City,
Vietnam
1 Võ Văn Ngân,
Phường Linh
Chiểu,
Quận Thủ Đức,
Thành phố Hồ Chí
Minh.
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Vo Van Ngan
Street,
Thu Duc District,
Ho Chi Minh City.
HCMUTE
LOCATION
2nd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
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3
2
7 6
4
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tree
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