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Digital System Design

Lecture 3: ASIC Design

Amir Masoud Gharehbaghi

[email protected]



Sharif University of Technology 3

Microelectronics Market

Primary Market

Information Systems

Telecommunications

Consumer Secondary Market

Systems (e.g. Transportation)

Manufacturing (e.g. Robots)




Electronic MarketSystems

Electronic Sub-Systems

Integrates Circuits

EDA




Trends in Microelectronics

Improvement in Device Technology

Smaller Circuits

Higher Performance

More Devices on a Chip Higher Degree of Integration

More Complex Systems

Lower Cost

Higher Reliability




Moore’s Law Every 18 Months:

Gate Count Doubles

Frequency Increases 50%




Integration-Scale Limitations

Intrinsic physical scaling limits

Capital investment for fabrication

Use of appropriate design styles

Large-scale design management Use of CAD tools for design




Microelectronic Design Problems

Use most recent technologies

Higher performance

Reduce design cost

Lower price Speedup design time

Shorten time-to-market




Rapid Prototyping

Prototype:

The original or model on whichsomething is based or formed

Something that serves as an exampleof its kind

Rapid:

Occurring within a short time Happening Speedily




Why Rapid Prototyping? Avoid high non-recurring engineering (NRE) costs

Avoid long construction time for "real" system Reduced time allowed from concept to product

Can quickly react to changing customerenvironment or requirements

Systems are too complex to simulate real-worldoperation in "bounded" time (need to build totest)

Customers won’t put up with unreliable products Sometimes the prototype is the product




Why Not Rapid Prototyping? Not the same performance as final

product (slower) Not the same size as final product

(bigger or more ICs required)

Prototype more expensive than finalproduction unit

More design time required to completeengineering of both prototype and finalsystem




VLSI Market

ASIC

Application Specific

Integrated Circuits

ASSP

Application SpecificStandard Part

Standard (Commodity) Part




Implementation Technologies




ASIC

Dedicated to single function, or limited

range of functions Not ASIC:

CPUs, Microprocessors

Memories: DRAM, SRAM, ROM, …

Standard Components (e.g. 74 Series)

ASIC:

Toy Chips

Mpeg Decoder/Encoder ICs

DSP Processors




Design Aspects Shorter product life-time

Shorter time-to-market More parallel design flow

Better communication between

different design groups




Design Aspects (cont.) More complex systems

More efficient design methods need tobe used

Design automation is a necessity

More tool-dependant design andoptimization

More difficult to ensure correct functionality




Design Aspects (cont.) Not fixed system specification when

starting the design entry More emphasis on high level design aspects

Flexible and very rapid design flow

Easy testability through the whole design

flow




Structures ASIC Design

Hierarchy: Subdivide the design into

many levels of sub-modules Regularity: Subdivide to max number of

similar sub-modules at each level

Modularity: Define sub-modulesunambiguously & well defined interfaces

Locality: Max local connections, keeping

critical paths within module boundaries




ASIC vs. Standard ICStandard IC

Typically lowcomponent cost

Parts available off theshelf

Low or insignificant ICdesign cost

Proven componentreliability

Multiple sourcing

System house not

required to have in-house experts in chipdesign

ASIC Good security of intellectual

property

Optimum system design

Relatively efficient use of boardspace (smaller systems)

Reliability enhanced at system level

(fewer components) Performance may be better than

comparable standard ICs (uniquefeatures and lower power

consumption) Possibility to optimize component cost

Design cost is high and design cycleis long




ASICsAdvantages

Efficient use of boardspace (lower finalsystem cost)

Product security

Unique features andfine-tuning theproduct

Optimized system

performance

Disadvantages

Potential for designfailure

Not off-the-shelf available

(specification, design,testing anddocumentation phasesare needed)

High unit cost of IC(higher initial costs of development)




Types of ASIC

Full Custom

Semi Custom

Cell based

Gate Array Programmable Logic

FPGA (Field Programmable Gate Array)

PLD (Programmable Logic Device)




Full Custom ASICs Some (or all) logic cells are customized

Demands longer design cycle All mask layers are customized Involves an implementation of a

completely new chip Designer must be an expert in VLSI

design It is used when:

existing cell libraries are not fast enough logic cells not small enough or consume too

much power technology migration (mixed-mode design)




Examples of Full Custom ICs

Analog (e.g. Sensor, Actuator)

Mixed Analog/Digital (e.g.Telecommunication)

High Voltage (e.g. Automobile) Low Power (e.g. PDA, Mobile)




Cell Based ASICs Use predesigned logic cells (standard

cells) in combination with larger cells(megacells)

Standard Cells Primitive Gates (and, or, …)

Multiplexers Registers

Mega cells (full-custom blocks, system-level macros, fixed blocks, cores,

functional standard blocks, or IP) Microcontrollers, Microprocessor, MPEG

decoder RAM, ROM




Cell Based ASICs (cont.)

Designers save time, money, and

reduce risk

Each standard cell can be optimized

individually All mask layers are customized

Custom blocks can be embedded




Gate Array Based ASICs Gate array (or prediffused array)

Transistors are predefined on the silicon wafer Base array: the predefined pattern of transistors Base cell: the smallest element that is replicated to

make the base array

Masked gate array (MGA) Only the top few layers of metal are defined by the

designer using custom masks The designer chooses from a gate-array library of

predesigned logic cells (macros)

Types of MGA ASICs Channeled gate arrays Channel-less gate arrays Structured gate arrays




Channeled Gate Array

Only the

interconnect iscustomized

The interconnect

uses predefinedspaces betweenrows of base cells




Channel-less Gate Arrays

Also known as

sea-of-gate(SOG)

only some masklayers arecustomized- the

interconnect




Structured Gate Array

Combine some of

the features of CBICs (Cell-BasedICs) and MGAs

Only theinterconnect iscustomized

Custom blocks canbe embedded

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