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VHDL Code for 2 x 1 MultiplexerPosted byCoding Talkson July 27, 2012

VHDLCode for2 x 1Multiplexer:

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Following codewill worklike 2:1 MUX insimulator. It very simple and easy to understand.

See Code :

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library ieee;

use ieee.std_logic_1164.all;

entity bejoy_2x1 is

port(d0,d1,s:in std_logic;

z:out std_logic;

z1,z2: inout std_logic);

end bejoy_2x1;

architecture arc of bejoy_2x1 isbegin

z1