Charge - Redistribution Successive Approximation

ADC

SYEDA NASIHA 3VY14LVS24

One of the most common implementation of successive approximation ADC.

It eliminates the need for separate sample and hold circuit.

The amount of charge on each capacitor of array is used to perform binary search operation

The conversion process begins by discharging capacitor array, via reset switch

Once the reset switch is closed, the capacitor array charges to the offset voltage of comparator.

The bottom plates of capacitors in array are connected to VIN

During hold mode reset is opened and bottom plates of capacitors are connected to ground.

Sampling VIN on capacitor array

The bottom plate of MSB capacitor is connected to Vref.

VTOP=-VIN+VOS+DN-1.VREF/2If output of comparator is high, the bottom plate of

MSB capacitor remains at VrefIf output of comparator is low, the bottom plate is

connected to ground

VTOP=-VIN+VOS+DN-1.VREF/2+DN-2.VREF/4

VTOP=-VIN+VOS+DN-1.VREF/2+DN-2.VREF/4+…….+ D1.VREF/2N-2+D0.VREF/2N-1=VOS

Redistribution(conversion)

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