3d chip design

8/13/2019 3D Chip Design

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3d chip design

CONTENTS

1. Introduction

2. Motivation for 3-D ICs

3. Scope of this study

4. Area and performance estimation of 3-D ICs

. Cha!!enges for 3-D Integration

". #vervie$ of 3-D IC techno!ogy

%. &resent scenario of the 3-D IC industry'. Advantages of 3-d memory

(. App!ications of 3-D ICs

1). *uture of 3-D IC industry

11. Conc!usion

12. +eference

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ABSTRACT

,he unprecedented gro$th of the computer and the Informationtechno!ogy industry is demanding ery arge Sca!e Integrated /SI0 circuits

$ith increasing functiona!ity and performance at minimum cost and po$er

dissipation. SI circuits are eing aggressive!y sca!ed to meet this Demand

$hich in turn has some serious pro!ems for the semiconductor industry.

Additiona!!y heterogeneous integration of different techno!ogies in one

sing!e chip /SoC0 is ecoming increasing!y desira!e for $hich p!anar /2-D0 ICsmay not e suita!e.

3-D ICs are an attractive chip architecture that can a!!eviate the

interconnect re!ated pro!ems such as de!ay and po$er dissipation and can a!so

faci!itate integration of heterogeneous techno!ogies in one chip /SoC0. ,he

mu!ti-!ayer chip industry opens up a $ho!e ne$ $or!d of design. ith the

Introduction of 3-D ICs the $or!d of chips may never !oo the same again.

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3d chip design

2. MOTIVATION FOR 3-D ICs

,he unprecedented gro$th of the computer and the information

techno!ogy industry is demanding ery arge Sca!e Integrated / SI 0 circuits

$ith increasing functiona!ity and performance at minimum cost and po$er

dissipation. Continuous sca!ing of SI circuits is reducing gate de!ays ut

rapid!y increasing interconnect de!ays. A significant fraction of the tota! po$er

consumption can e due to the $iring net$or used for c!oc distriution $hich

is usua!!y rea!i7ed using !ong g!oa! $ires.

*urthermore increasing drive for the integration of disparate signa!s

/digita! ana!og +*0 and techno!ogies /S#I Si9e 9aAs and so on0 is

introducing various SoC design concepts for $hich e6isting p!anner /2-D0 IC

design may not e suita!e.

INTERCONNECT LIMITED VLSI PERFORMANCE

In sing!e Si !ayer /2-D0 ICs chip si7e is continuous!y increasing despite

reductions in feature si7e made possi!e y advances in IC techno!ogy such as

!ithography and etching. ,his is due to the ever gro$ing demand for functiona!ity

and high performance $hich causes increased comp!e6ity of chip design

re:uiring more and more transistors to e c!ose!y paced and connected. Sma!!

feature si7es have dramatica!!y improved device performance. ,he impact of this

miniaturi7ation on the performance of interconnect $ire ho$ever has een !ess

positive. Sma!!er $ire cross sections sma!!er $ire pitch and !onger !ine to

traverse !arger chips have increase the resistance and capacitance of these !ines

resu!ting in a significant increase in signa! propagation /+C0 de!ay. As

interconnect sca!ing continues +C de!ay is increasing!y ecoming the dominant

factor determining the performance of advanced IC;s.

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3d chip design

PHYSICAL LIMITATIONS OF Cu INTERCONNECTS

At 2) nm techno!ogy node Cu $ith !o$- die!ectric $as introduced to

a!!eviate the adverse effect of increasing interconnect de!ay. on > a >chip /SoC0 is a road concept that refers to the

integration of near!y a!! aspects of a system design on a sing!e chip. ,hese chips

are often mi6ed-signa! and?or mi6ed-techno!ogy designs inc!uding such diverse

cominations as emedded D+AM high > performance and !o$-po$er !ogicana!og +* programma!e p!atforms /soft$are *&9As *!ash etc.0.

SoC designs are often driven y the ever-gro$ing demand for increased

system functiona!ity and compactness at minimum cost po$er consumption and

time to maret. ,hese designs form the asis for numerous nove! e!ectronic

app!ications in the near future in areas such as $ired and $ire!ess mu!timedia

communications inc!uding high speed internet app!ications medica! app!ications


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3d chip design

inc!uding remote surgery automated drug de!ivery and non invasive interna!

scanning and diagnosis aircraft?automoi!e contro! and safety fu!!y automated

industria! contro! systems chemica! and io!ogica! ha7ard detection and home

security and entertainment systems to name a fe$.

,here are seve!" #$!""e%&esto effective SoC designs@

1. arge sca!e integration of functiona!ities and disparate techno!ogies on a

sing!e chip dramatica!!y increases the chip area $hich necessitates the use of

numerous !ong g!oa! $ires. ,hese $ires can !ead to unaccepta!e signa!transmission de!ays and increase the po$er consumption y increasing the

tota! capacitance that needs to e driven y the gates.

2. Integration of disparate techno!ogies such as emedded D+AM !ogic and

passive components in SoC app!ications introduces significant comp!e6ity in

materia!s and process integration.

3. ,he noise generated y the interference et$een different emedded circuit

!ocs containing digita! and ana!og circuits ecomes a cha!!enging pro!em.

4. A!though SoC designs typica!!y reduce the numer of I?# pins compared to a

system assem!ed on a printed circuit oard/&C80 severa! high performance

SoC designs invo!ve very high I?# pin counts $hich can increase the cost

per chip

. Integration of mi6ed techno!ogies on a sing!e die re:uires nove! design

methodo!ogies and too!s $ith design productivity eing a ey re:uirement.

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3d chip design

3D ARCHITECTURE

,hree-dimensiona! integration to create mu!ti!ayer Si ICs is a concept that

can significant!y improve interconnect performance increase transistor pacing

density and reduce chip area and po$er dissipation. Additiona!!y 3D ICs can e

very effective !arge sca!e on chip integration of different systems.

In 3D design architecture and entire/2D0 chips is divided into a numer of

!ocs is p!aced on separate !ayer of Si that are staced on top of each other.

ach Si !ayer in the 3D structure can have mu!tip!e !ayer of

interconnects/IICs0 and common g!oa! interconnects.

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3d chip design

ADVANTAGES OF 3D ARCHITECTURE

,he 3D architecture offers e6tra f!e6ii!ity in system design p!acement

and routing. *or instance !ogic gates on a critica! path can e p!aced very c!ose

to each other using mu!tip!e active !ayers. ,his $ou!d resu!t in a significant

reduction in +C de!ay and can great!y enhance the performance of !ogica!

circuits.

,he 3D chip design techno!ogy can e e6p!oited to ui!d SoCs y p!acingcircuits $ith different vo!tage and performance re:uirements in different

!ayers.

,he 3D integration can reduce the $iring therey reducing the

capacitance po$er dissipation and chip area and therefore improve chip

performance.

Additiona!!y the digita! and ana!og components in the mi6ed-signa!

systems can e p!aced on different Si !ayers therey achieving etter noise

performance due to !o$er e!ectromagnetic interference et$een such

circuits !ocs.

*rom an integration point of vie$ mi6ed-techno!ogy assimi!ation cou!d

e made !ess comp!e6 and more cost effective y faricating such

techno!ogies on separate sustrates fo!!o$ed y physica! onding.

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3d chip design

3. SCOPE OF THIS STUDY

A 3D so!ution at first g!ance seems an ovious ans$er to the interconnect

de!ay pro!em. Since chip si7e direct!y affects the inter connect de!ay therefore

y creating a second active !ayer the tota! chip footprint can e reduced thus

shortening critica! inter connects and reducing their de!ay.


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3d chip design

'. AREA AND PERFORMANCE ESTIMATION OF 3D ICs

o$ $e present a methodo!ogy that can e used to provide an initia!

estimate of the area and performance of high speed !ogic circuits faricated using

mu!tip!e si!icon !ayer IC techno!ogy. ,he approach is ased on the empirica!

re!ationship no$n as +ent;s +u!e.

Re%()s Ru"e*

It corre!ates the numer of signa! input and output /I?#0 pins , to the

numer of gates in a random !ogic net$or and is given y the fo!!o$ing

e6pressions @

,& -------------/i0


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3d chip design

here 6 is a varia!e of integration representing !ength and ! is the !ength of the

interconnect in gate pitches. ,he derivation of the $ire-!ength distriuted in a Ic

is ased on +ent;s +u!e. ,o derive the $ire !ength distriution I/!0 of an

integrated circuit the !atter is divided up into !ogic gates $here is re!ated to

the tota! numer of transistor t in an integrated circuit y t?# $here # is a

function of the average fan-in/f.i) and fan-out/f.o0. ,he gate pitch is defined as

the average separation et$een the !ogic gates and is e:ua! to s:t/Ac?0 $here

Ac is the area of the chip.

In order to derive the comp!ete $ire-!ength distriution for a chip thestochastic $ire-!ength distriution of a sing!e gate must e ca!cu!ated.

,he numer of connections from the sing!e !ogic gate in 8!oc A to a!!

other gate that are !ocated at a distance of ! gate pitches is determined using

+ent;s +u!e. ,he gates sho$n in the figure are grouped into three distinct ut

adBacent !ocs/A8EC0 such that a c!osed sing!e path can encirc!e one t$o or

three of these !ocs. ,he numer of connections et$een 8!oc A and 8!oc C

is ca!cu!ated y conserving a!! I?# termina!s for !ocs A 8 and C $hich states

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3d chip design

that termina!s for !ocs A 8 and C are either inter!oc connections or e6terna!

system connections.

,8C ..GGGGGGGGGG./v0

Sustituting /iv0 and /v0 into /iii0 gives

,A to C ,A8F ,8C> ,8 - ,A8C GGGGGGGGGG/vi0

o$ the numer of I?# pins for any sing!e !oc or a group of !ocs can

e ca!cu!ated using +ent;s +u!e. If $e assume that and are the numer

of gates in !ocs A 8 and C respective!y then it fo!!o$s that

,8 /80& GGGGGGGGG/vii0

,A8 /AF 80& GG..GGGGGG../viii0

,8C /8 F C 0& GGG.GGGGGG/i60

,A8C /A F 8 FC0& GGGGGGGGG./60

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3d chip design

here AF 8 F C. Sustituting /vii0 > /60 into /vi0 gives

,A to C H/ AF 80&> /80&F /8 F C0&> /A F 8F C0& GG../6i0

,he numer of interconnects et$een 8!oc A and 8!oc C /IA to C0 is

determined using the re!ation

IA to C J /,A to C0

here J is re!ated to the average fan out /f.o.0 y

J f.o. ? /1Ff.o.0

App!ying +ent;s +u!e to a!! the !ayers $e have

,& /=

n

i 1

,i0 > ,int n/?n0&- ,int


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3d chip design

!ogic gates. *or the purpose of minimi7ing si!icon rea! estate and signa!

propagation de!ays the $iring net$or is segmented into separate tiers that are

physica!!y faricated in mu!tip!e !ayers.

An interconnect tier is categori7ed y factors such as meta! !ine pitch and

cross-section ma6imum a!!o$a!e signa! de!ay and communication mode /such

as intra !oc or inter !oc0. A tier can have more than one !ayer of meta!

interconnects if necessary and each tier or !ayer is connected to the rest of the

$iring net$or and the !ogic gates y vertica! vias. ,he tier c!osest to the !ogic

devices /referred to as the "#!" (e0 is norma!!y for short distance intra !oc

communications.

Meta! !ines in this tier $i!! norma!!y e the shortest. ,hey $i!! a!so

norma!!y have the finest pitch. ,he tier furthest a$ay from the device !ayer

/referred to as&"/!" (e0 is responsi!e for !ong distance across chip inter !oc

communications c!ocing and po$er distriution. Since this tier is popu!ated y

the !ongest of $ires the meta! pitch is the !argest to minimi7e signa! propagation

de!ays. A typica! modern IC interconnects architecture $i!! define three $iring

tiers@ "#!"0 se-&"/!"0 !% &"/!". ,he semi-g!oa! tier is norma!!y

responsi!e for inter !oc communications across intermediate distances.

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3d chip design

,he area of the chip is determined y the tota! $iring re:uirement. I

terms of gate pitch the tota! area re:uired y the interconnect $iring can e

e6pressed as

Are:uired KAc/&!octota!L!ocF&semitota!LsemiF&g!otota!Lg!o0?

here

Ac Chip area 5

numer of gates5

&!oc !oca! pitch5

&semi semi g!oa! pitch5

&g!oa! g!oa! pitch5

tota!L!oc tota! !engths of !oca! interconnects5tota!Lsemi tota! !ength of semi g!oa! interconnects5

tota!Lg!o tota! !ength of g!oa! interconnects5

,he tota! interconnects !ength for any tier can e found y integrating the

$ire-!ength distriution $ithin the oundaries that define the tier.


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tota!Lsemi N !i /!0 d!

tota!Lg!o N !i /!0 d!

here is a correction factor that converts the point >to > point interconnect

!ength to $iring net !ength /using a !inear net mode! 4?/f.o. F 30

C+ T,O ACTIVE LAYER 3-D CIRCUIT PERFORMANCE

,his ana!ysis is used to compare area and de!ay va!ues for 2-D and 3-D

ICs. ,he avai!ai!ity of addition of si!icon !ayers gives the designer e6traf!e6ii!ity in trading off area $ith de!ay. A numer of different cases are

discussed as fo!!o$s@

1. C$ !e! %4!(% 5($ 67e %(e#%%e#( e"!8


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since these $ires have a !arge cross section they have a greater area re:uirement.

Onder such circumstances the g!oa! tier egins to dominate and determine the

chip area.

,he curve for the 3-D case has a minimum simi!ar to the one otained for

the 2-Dcase.it can e oserved that the minimum chip area for the 3-D case is

aout P3)= sma!!er than that of the 2-D case. Moreover since the tota! $iring

re:uirement is reduced the semi g!oa! tier pitch is reduced for the 3-Dchip. ,he

significant reductions in chip area demonstrated y the 3-D resu!ts are a

conse:uence of the fraction of $ires that $ere converted from hori7onta! in 2-Dto vertica! IICs in 3-D. it is assumed that the area re:uired y IICs is

neg!igi!e.

,hese resu!ts demonstrate $ith given assumptions that a 3-D IC can

operate at the same performance !eve! as measured y the !ongest $ire de!ay as

its 2-D counterpart $hi!e using up aout 3)= !ess si!icon rea! estate.


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3d chip design

area sti!! remains $e!! e!o$ the area re:uired for the 2-D case. ,he figure a!so

he!ps defines a ma6imum > performance 3-D chip > a chip $ith the same area as

the corresponding 2-D chip $hich can e otained y increasing the semi g!oa!

pitch eyond that for the 4-9


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3d chip design

IICs egins to offset any area saving due to increasing the numer of active

!ayers.

E+ EFFECT OF INCREASING THE NUMBER OF METAL LAYERS

It is !ie!y that there are !oca! and semi g!oa! tiers associated $ith every

active !ayer and a common g!oa! tier is used . ,his $ou!d resu!t in an increase

in the tota! numer of meta! !ayers for the 3-D case. ,he effect of using 3-D case.

,he effect of using 3-D ICs $ith constant meta! !ayers and the effect of

emp!oying t$ice the numer of meta! !ayers as in 2-D are summari7ed in thefigure.

It can e oserved that y using t$ice the numer of meta! !ayers the

performance of the 3-D chip can e increased y an additiona! amount of 3= as

compared to the 3-d chip $ith the same tota! numer of meta! !ayers as in 2-d . It

can e oserved that for the more aggressive techno!ogies the decrease in

1(


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3d chip design

interconnect de!ay from 2-D to 3-D case is !ess impressive. ,his indicates that

more than t$o active !ayers are possi!y needed for those advanced nodes. ,he

figure a!so sho$s the impact of moving on!y the repeaters to the second !ayer Si

!ayer . It can a!so e oserved that for more aggressive techno!ogies the

decrease in interconnect de!ay from 2-D to 3-D case is !ess impressive ,his

indicates that more than t$o active !ayers are possi!y needed for those advanced

nodes.

F.OPTIMI9ATION OF INTERCONNECT DISTRIBUTION

In estimating chip area the meta! re:uirement is ca!cu!ated from the

otained $ire-!ength distriution. ,he tota! meta!!i7ation re:uirement is

appropriate!y divided among the avai!a!e meta! !ayers in the corresponding

techno!ogy . ,hus each tier the !oca! the semi g!oa! and the g!oa! has three

meta! !ayers . the resu!ting area of most dense!y paced tier determines the chip

area.

Conse:uent!y higher tier are routed $ithin a !arger than re:uired area .

An optimi7ation for this scenario is possi!e y rerouting some of the !oca! $ires

on the semi g!oa! tier and the !atter on the g!oa! $ithout vio!ating the

ma6imum a!!o$a!e ength / or de!ay 0 per tier. ,his is achieved y reducing

the ma6imum a!!o$ed interconnect !ength for the !oca! and semi g!oa! tiers.

Minimum chip area $i!! achieved $hen a!! the tiers are e:ua!!y congested. ,he 2-

D chip area is seen to reduce y (= as a resu!t of this optimi7ation is a!so app!ied

to app!ied to 3-D ICs .

2)


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3d chip design

:.CHALLENGES FOR 3-D INTEGRATION

A+ THERMAL ISSUES IN 3-D ICs

An e6treme!y important issue in 3-D ICs is heat dissipation. ,herma!

effect s are a!ready no$n to significant!y impact interconnected ?device

re!iai!ity and performance in high-performance 2-D ICs. ,he pro!em is

e6pected to e e6acerated y the reduction in chip si7e assuming that same

po$er generated in a 2-D chip $i!! no$ e generated in a sma!!er 3-D chip

resu!ting in a sharp increase in the po$er and density Ana!ysis of therma!

pro!ems in 3-D circuits is therefore necessary to comprehend the !imitations of

this techno!ogy and a!so to eva!uate the therma! roustness of different 3-D

techno!ogy and design options.

It is $e!! no$n that most of the heat energy in integrated circuits arises

due to transistor s$itching. ,his heat energy is typica!!y conducted through the

si!icon sustrate to the pacage and then to the amient y a heat sin .ith

mu!ti !ayer device designs devices in the upper !ayer $i!! a!so generate a

significant fraction of the heat .*urthermore a!! the active !ayers $i!! e insu!ated

from each other y !ayers of die!ectrics /,#


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3d chip design

B+ RELIABLITY ISSUES IN 3-D ICs

,hree dimensiona! IC s $i!! possi!y introduce some ne$ re!iai!ity

pro!ems. ,hese re!iai!ity issues may arise due to the e!ectro therma! and

thermo mechanica! effects et$een various active !ayers and the interfaces

et$een the active !ayers $hich can a!so inf!uence e6isting IC re!iai!ity ha7ards

such a e!ectro migration and chip performance. Additiona!!y heterogeneous

integration of techno!ogies using 3-d architecture $i!! increase the need to

understand mechanica! and therma! ehavior of ne$ materia! of ne$ materia!

interfaces and thin fi!m materia! therma! and mechanica! properties.

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3d chip design

;. OVERVIE, OF 3-D IC TECHNOLOGY

1+ BEAM RECRYSTALI9ATION

A very popu!ar method of faricating a second active !ayer /Si0 on top of

an e6isting sustrate /o6idi7ed Si $afer 0is to deposit po!ysi!icon and faricate

thin fi!m transistors /,*,0. ,o enhance the performance of such transistors an

intense !aser or e!ectron eam is used to induce recrysta!isation of the

po!ysi!icon fi!m to reduce or even e!iminate most of the grain oundaries.

Av!%(!&e

1. M#S on transistors faricated on po!ysi!icon e6hiit very !o$ surface

moi!ity va!ues Hof the order of 1) cm?s.

2. M#S transistors faricated on po!ysi!icon have high thresho!d vo!tages

/severa! vo!ts0 due to the high density of surface states /severa! 1) cm 0

present at the grain oundaries.

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3d chip design

Ds!v!%(!&e

1. ,his techni:ue ho$ever may not e very practica! for 3-D devices

ecause of the high temperature invo!ved during me!ting of the

po!ysi!icon.

2. Difficu!ty in contro!!ing the grain si7e variations.

2+ SILICON EPITA


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3d chip design

Ds!v!%(!&e

1. ,he high temperatures invo!ved in this process cause significant

degradation in the :ua!ity of devices on !o$er !ayers.

2. PROCESSED ,AFER BONDING*

An attractive a!ternative is to ond t$o fu!!y processed $afers on $hich

devices are faricated on the surface inc!uding some interconnects such that the

$afers comp!ete!y over!ap.Interchip vias are etched to e!ectrica!!y connect oth$afers after meta!!i7ation and prior to the onding process at 4)) degree Ce!sius.

*or app!ications $here each chip is re:uired to perform independent processing

efore communicating $ith it;s neighor this techno!ogy can prove attractive .

Av!%(!&e

1. Devices on a!! active !eve!s have simi!ar e!ectrica! properties.

2. Since a!! chips can e faricated separate!y and !ater onded there is

independence of processing temperature.

Ds!v!%(!&e

1. ,he !ac of precision restricts the interchip communication to g!oa! meta!

!ines.

3. SOLID PHASE CRYSTALLI9ATION =SPC+

In this techni:ue a !ayer of amorphous Si is crysta!!i7ed on top of the

!o$er active !ayer devices. ,he amorphous fi!m is random!y crysta!!i7ed to form

a po!ysi!icon fi!m. Device performance can e enhanced y e!iminating the grain

oundaries in the po!ysi!icon fi!m. *or this purpose !oca! crysta!!i7ation can e

induced using !o$ temperatures processes /R"))C0 such as using patterned

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3d chip design

seeding of germanium . In this method 9e seeds imp!anted in narro$ patterns

made on amorphous Si can e used to inc!uded !atera! crysta!!i7ation. ,his resu!ts

in the formation of sma!! is!ands $hich are near!y sing!e crysta!. CM#S

transistors can then e faricated $ithin these is!ands to give S#I !ie

performance.

Av!%(!&es

1. ,his techni:ue offers f!e6ii!ity of creating mu!tip!e active !ayers

2. ,his is a !o$ temperature techni:ue

B+ VERTICAL INTERLAYER INTERCONNECT TECHNOLOGY

OPTIONS

,here is direct re!ation et$een improved chip performance and increased

uti!ity of IICs. It is therefore important to understand ho$ to connect different

active !ayers $ith a re!ia!e and compati!e process. Opper !ayer processing

needs to e compati!e $ith meta! !ines underneath connecting !o$er !ayer

devices and meta! !ayers. ith Cu techno!ogies this !imits the processing

temperatures to R4) c for upper !ayers. #ther$ise Cu diffusion through arrier

!ayers and the re!iai!ity and therma! stai!ity of materia! interfaces can degrade

significant!y. ,ungsten is a refractory meta! that can e used to $ithstand higher

processing temperatures ut it has higher resistivity. Current via techno!ogy cana!so e emp!oyed to achieve IIC functiona!ity. ,he under!ying assumption

here re:uires that inter!ayer gates are interconnected using regu!ar hori7onta!

meta! $ires and vias $hi!e inter!ayer interconnects can e IICs connecting

the $iring net$or for each !ayer.

2"


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3d chip design

+ecent!y inter!ayer /IC0meta!!i7ation schemes for 3-d ICs have een

demonstrated using direct $afer onding. ,hese techni:ues are ased on the

onding of t$o $afers $ith their active !ayers connected through vias $hich

serve as IICs .

#ne method is ased on the onding of a thinned top $afer to a ottom

$afer $ith a organic adhesive !ayer of po!yamide in et$een.

Interchip vias are etched through the ID/inter !eve! die!ectric 0the

thinned top si!icon $afer and through the cured adhesive !ayer $ith an appro6

depth of 2) m prior to the onding process .the interconnect chip via made of

chemica! $afer depositor /CD0. ,in !iner and CD- p!ug provides a vertica!

interconnect /IIC0et$een the upper most meta!!i7ation !eve!s of oth !ayers .

the onding et$een the t$o $afers is done using a f!ip-chip onder $ith sp!it

eam optics at a temperature of 4)) degree Ce!sius

A second techni:ue rea!i7es on the ($e #ess% onding

et$een the meta! parts in each $afer.

In this method Cu-,a pads on oth $afers save as e!ectrica! contacts

et$een the interchips via on the top thinned si!icon $afer and the upper most

interconnects on the ottom si!icon $afer. ,he Cu-,a pads can a!so function as

sma!! ond pads for $afer onding. Additiona!!y dummy meta! patterns can e

made to increase the surface area for $afer onding. ,he Cu-,a i!ayer pads

$ith a comined thicness of %)) nm are fused together y app!ying a

compressive force at 4)) degree Ce!sius. ,his techni:ue offers the advantage of

a meta! >meta! interface that $i!! !o$er the interface therma! resistance et$een

the t$o $afers /and hence provide etter conduction0 and can e eneficia! as a

partia! ground p!ane for !o$ering the e!ectromagnetic effects.

>. PRESENT SCENARIO OF THE 3-D IC INDUSTRY

2%


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3d chip design

Many companies are $oring on the 3-D chips inc!uding groups at

Massachusetts institute of techno!ogy /MI,0internationa! usiness

machines/I8M0. +ensse!ar &o!ytechnic and SO A!any are a!so doing

research on techni:ues for onding conventiona! chips together to form mu!tip!e

!ayers .$hichever approach u!timate!y $ins the mu!ti!ayer chip ui!ding

techno!ogy opens up a $ho!e ne$ $or!d of design .

pane! !i:uid crysta!

disp!ays to ui!d chips $ith mu!ti!ayer of circuitry.

,he company;s first products $i!! e memory chips ca!!ed 3-Dmemory

for consumer e!ectronics !ie digita! cameras and audio p!ayers. current f!ash

memory cards for such devices are re$rita!e ut e6pensive .ho$ever the ne$!y

produced chips $i!! cost ten times !ess aout as much as an audio tape or a ro!!

of fi!m ut $i!! on!y record information once. ,he cost is so !arge!y ecause the

staced chips contain the same amount of circuitry as f!ash cards ut use a much

sma!!er area of the e6treme!y e6pensive si!icon $afers that form the asis for a!!

si!icon chips. ,he chips $i!! a!so offer a permanent record of the images and

sounds users record. ,he amount of computing po$er the company can

u!timate!y ui!d in to its chips cou!d e !imited .the company hopes to eventua!!y

ui!d chips for ce!! phones or !o$ performance micro processors !ie those

found in app!iances5 such chips $ou!d e aout one tenth as e6pensive as current

ones.

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3d chip design

,he patent techno!ogy opens up the ai!ity to ui!d ICs in three

dimensions- TupU as $e!! as ToutU in the hori7onta! directions as in the case no$

$ith conventiona! chip designs. ,he resu!t is a ten fo!d increase in the potentia!

no of its on a si!icon die according to the company .moreover the 3-D circuits

can e produced $ith todays standard semiconductor materia!s fa e:uipments

and processors the 3-D memory $i!! e used in memory devices $hich $i!! e

mareted under $e!! no$n rand names for porta!e e!ectronics devices

inc!uding digita! cameras digita! audio p!ayers games &DAs and archiva!

digita! storage .the 3-D memory can a!so e used for pre recorded content such

as music e!ectronics oos digita! maps games and reference guides.

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3d chip design

?. ADVANTAGES OF 3-D MEMORY

Diss are ine6pensive ut they re:uires drives that are e6pensive u!y

fragi!e and consume a !ot of attery po$er . Accidenta!!y dropping a drive or

scratching a dis can cause significant damage and the potentia! !oss of va!ua!e

pictures and data. *!ash and other non vo!ati!e memories are much more rugged

attery efficient compact and re:uire no u!y drive techno!ogies . Dropping

them is not a pro!em they are ho$ever much more e6pensive. 8oth re:uire the

use of a pc.

,he idea! so!ution is a 3-D memory that !everages a!! the enefits of non

vo!ati!e media costs as !itt!e as a dis and is as convenient as 3 mm fi!m and

audio tape.

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3d chip design

@. APPLICATIONS

&orta!e e!ectronic digita! cameras digita! audio p!ayers &DAs smart

ce!!u!ar phones and handhe!d gaming devices are among the fastest gro$ing

techno!ogy maret for oth usiness and consumers. ,o date one of the !argest

constraints to gro$th has een afforda!e storage creating the mareting

opportunity for u!tra !o$ cost interna! and e6terna! memory. ,hese app!ications

share characters eyond rapid maret gro$th.

&orta!e devices a!! re:uire sma!! form factors attery efficiency

roustness and re!iai!ity. 8oth the devices and consuma!e media are e6treme!y

price sensitive $ith high vo!umes coming on!y $ith the ai!ity to hit !o$ price

points. Device designers often trade app!ication richness to meet tight cost

targets. 6isting mas +#M and AD f!ash non vo!ati!e techno!ogy force

designers and product p!anners to mae the difficu!t choice et$een !o$ cost or

fie!d programmai!ity and f!e6ii!ity. Consumers va!ue the convenience and ease

of vie$s of readi!y avai!a!e !o$ cost storage. ,he potentia! to dramatica!!y

!o$er the cost of digita! storage $eapons many more marets than those !isted

aove. Manufacturers of memory driven devices can no$ reach price points

previous!y inaccessi!e and deve!op richer easier to use products.

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3d chip design

1. FUTURE OF THE 3-D IC INDUSTRY

Matri6 is $oring $ith partners inc!uding Microsoft Corp ,homasMu!timedia astman Voda and Sony Corp. three product categories are

p!anned@ !and memory cards@ cards so!d pre!oaded $ith content such as

soft$are or music 5 and standard memory pacages for using emedded

app!ications such as &DAs and set-top o6es .

T$s% e"e#(%#s the uropean e!ectronic giant $i!! egin to

incorporate 3-D memory chips from matri6 semiconductor in porta!e storagecards a strong endorsement for the chip start >up.

T$s% u"(e!$i!! incorporate the 3-D memory in memory cards

that cane e used to store digita! photos or music. A!though the cards p!ug into

cameras ,homson is a!so $oring on card readers that $i!! a!!o$ consumers to

vie$ digita! photos on a te!evision. ,he ,homson ?matri6 cards price maes the

difference from comp!eting f!ash cards from Sony and ,oshia .the "4 M8,homson card $i!! cost aout as much as camera fi!m does today. to further

strengthen the re!ationship $ith fi!m the cards $i!! e so!d under the name

,echnico!or Digita! Memory Card.

Simi!ar f!ash memory cards from other companies cost around +s.1()) or

more-though consumers can erase and rerecord data on them un!ie the matri6

cards. As a resu!t of their price consumers uy very fe$ of them. ,homson y

contrast e6pects to maret its $rite-once cards in retai! out!et such as a!-

Mart.

,he first ,echnico!or cards $i!! offer "4 M8 of memory5 version $ith 12'

M8 and 1(2 M8 $i!! appear !ater. ,he first 3-D chips $i!! contain "4 M8.

,ai$an Semiconductor Manufacturing Co. is producing the chips on eha!f of

matri6.

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3d chip design

11. CONCLUSION

,he 3 D memory $i!! Bust the first of a ne$ generation of dense

ine6pensive chips that promise to mae digita! recording media oth cheap and

convenient enough to rep!ace the photographic fi!m and audio tape. e can

understand that 3-D ICs are an attractive chip architecture that can a!!eviate the

interconnect re!ated pro!ems such as de!ay and po$er dissipation and can a!so

faci!itate integration of heterogeneous techno!ogies in one chip. ,he mu!ti!ayer

chip ui!ding techno!ogy opens up a $ho!e ne$ $or!d of design !ie a city

sy!ine transformed y syscrapers the $or!d of chips may never !oo at the

same again.

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12. REFERNCES

1. &roceedings of the I vo! '(no may 2))1@

/a0 Wose Schutt-Aine sung-Mo Vang

TInterconnections >addressing the ne6t cha!!enge of IC techno!ogyU at

page '3

/0 +oert h

3d chip design

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