3d technology evolution to smart interposer and high density 3d ics

3D technology evolution

to smart interposer and

high density 3D ICs

Patrick Leduc, Jean Charbonnier, Nicolas Sillon, Séverine Chéramy, Yann Lamy, Gilles Simon

CEA-Leti, Minatec Campus

© CEA. All rights reserved

| 22012 Semicon Europa - P. Leduc

Why 3D integration?To integrate complex electronic systems on silicon

A silicon interposerWith very heterogeneous dice on it (various substrates, various technologies co-existing, various chip makers…).

3D ICs

Smaller, more functionality, higher performance

System on board(Smatphone PCB)



Facts & Figures

CEA-Leti: an “early-adopter” of 3D,

thanks to its background in MEMS &

Microelectronics (first TSV patent in

1988)

Today, 100+ people full time on 3D integration

Present to major IC conferences (regular presence at

IEDM) and packaging conferences. An average of 30

papers / year

15 “3D” patents in 2011

Leti at the heart of Grenoble ecosystem on 3D

R. Cuchet et al, 1988

Laser drilled TSV



Contents

Si interposer

…Towards smart interposer

3D IC

…Towards high density

Conclusions



Silicon Interposer Technology

Interposer size: 26x26mm² (warp management required)

TSV: 10x100µm

Cu damascene routing : Metal1-Via1-Metal2, 0.5µm line/0.5µm space

Micro copper pillars: Pitch 50µm, 100 000/interposer

TSV exposure

RDL and passivation: 10µm Line / Space, one level

Large copper pillar: pitch 500µm, height 70µm

Large Cu Pillar

TSV

RDL and Passivation

Damascene

Micro Cu pillar

TSV exposure

J. Charbonnier et al., ESTC 2012Joined Lab



L/S=0.5/0.5µm

L/S=0.7/0.7µm

L/S=1/1µm

Line 2

Line 1

TSV 10x100µm

Via

| 6

SEM Cross section after front side passivation opening

Copper in TSV stabilized for further integration process

Dense routing 0.5/0.5µm design performed successfully

TSV and Front side routing

J. Charbonnier et al., ESTC 2012

Joined Lab



Front side Copper micro pillar 10µm height, Ø25µm and 50µm pitch

Deposit uniformity within wafer: +/- 1µm

Cu/Ni/Au stack for oxidation protection

100.000 per interposer

Au capping

Ni diffusion barrier

Cu base

J. Charbonnier et al., ESTC 2012Joined Lab



Backside RDL and Bumps

RDL L/S=10µm

Organic passivation by spin

coating

Large bumps Ø250µm and 500µm pitch pillars

Cu/Ni/Au electroplating

Stripping, seed layer wet etch

Total thickness 70µm

SEM tilted 60°

RDL

Passivation

bump

Zoom top view on RDL and pillars




Interposer cross section

Good integrity of the overall structure: no delamination

No copper extrusion or residue between TSV and Line 1

No copper extrusion or residue between TSV and Backside RDL




Si interposer on tape (200mm wafer)

100µm thick interposer on dicing tape after debonding




Electrical tests

Chain A Chain B Chain C

cum

ulat

ive

100% yield on 100 and

1000 TSV chains




Si Interposer Demonstrator

Chip A Chip B

Organic substrate

Chip

Si-IPSi-IP

TSV

Cu Pillar

Features Cu TSV, AR10

2 to 4 layers routing, Damascene thick

copper, L/W 0.5/0.5 x 1.4μm

Temporary bonding

Thinning, Stress Monitoring, Warp

Management

Under-fill

Ken Miyairi, Masahiro Sunohara, Jean Charbonnier et al, IMAPS, San Diego 09/2012



High Density Interposer

Smart Interposer

More than wires…

More wires…

Interposer evolution



Smart interposer: More than Wires

Passives Interposer

Thermal Interposer

Photonic Interposer

Active Interposer

RF Platform for BasebandLightingApplication Processor (decouplingcapacitance)Health: Implantable electronics

ComputingPowerLightingApplication processor

Power managementHigh VoltageExternal I/O(Mature node)

ServersData centersComputing

Smart interposer



Smart interposer for a pacemaker

~1.2mm~900um

RF Die PICS

3D Si capacitors integration in implantable module SiP Package for pacemaker:•RF Transceiver•SAW Filter•400MHz & 2.4GHz Matching network with integrated coils•Decoupling capacitances

- 40 % area decrease- 25 % height decrease

14mm

8mm

Integrated passives in Si interposer leads to 40% size

reduction of the RF module compared to PCB

Source: Vivarès, Voiron, Lamy, et al. LETI –IPDIA-SORIN -Minapad 2011

Collaboration between:

6.45

mm

11.2mm

Si interposer



Contents

Si interposer

…Towards smart interposer

3D IC

…Towards high density

Conclusions



Wide IO Memory Logic-on-analogLogic-on-logic(Advanced on Mature)

Active interposer Modular and Stackable logic(3D Network-On-Chip)

2,5D

3D

Si interposer

3D IC evolution

Large grain 3D

partitionning

(∼∼∼∼50µm pitch)


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Wide I/O Demonstrator

Wide I/O SDRAM JEDEC memory standard released Jan. 2012

TSV’s Ø 10 μm, AR 8, Pitch 40 μm, Number 1016

Compatible with FD-SOI

Chip to Chip Cu Pillars Ø20 μm, Height 20 μm, Pitch 40 μm, Number 1016

SoC to Substrate Cu Pillars Ø55 μm, Height 40 μm, Pitch >200 μm, Number 933

FBGA Package Size 12x12mm, Ball Pitch 0.4mm,Ball Matrix 29x29, 1.2

mm thickness

Si - Wide I/O Memory

TSV80µm

Si -SoC

Cu Pillar

WIOMING, G.Kimmich, G.Qualizza 2012-06-28


| 192012 Semicon Europa - P. Leduc | 19

Cu RDL

Cu TSV

BEOL

Cu TSV

3D Partitioning : Digital - Analog

TSV

Top - Digital

Bottom - Analog

BGA

Die - die connection Die - BGA connection

Wireless application High definition video transmitter, >1GHz

Integration technology proven and concept demonstrated TSV + 7 metal layers, 65nm technology

Cost evaluation dependant on product complexity and design 3D Integration of a Wireless product with Design Pa rtitioning

G. Druais et al., 3DIC 2012





2,5D

3D

Si interposer

3D IC evolution

Large grain 3D

partitionning




Logic-on-logic : 3D Asynchronous NoC

Constraints ? High bandwidth between dies,

Easy staking, no clock distribution issues

Power distribution,

Testability, Fault Tolerance

Proposal : 3D Asynchronous NoC Fast serial link

Full asynchronous logic

2D NoC Router

3D NoC Router

Processing Unit

NoC Serial Links

Demonstration in 2014

Easily stackable logic “tiles” A set of tiles will give you the performance for your application

Increase number of applications for a single die, reach required volume

production



Active Interposer Concept

SDRAMMulti-core SoC

Multi-core SoC Multi-core SoC

Heterogeneous integration rationale: Small dies shorten new process introduction and improve overall yield

Analog design and IOs doesn’t shrink a lot with process technology

Short interconnect improves signal and power integrity

SoC partitioning into several dies, with different technology nodes

Active Interposer:Analog, interconnect, memory control and I/O peripherals

Processing layer:High performance multi-core processors

Memory layer:High bandwidth,Wide data interface

Demonstration in 2015





2,5D

3D

Si interposer

3D IC evolution

Fine grain 3D

partitionning


3D Cache memory on

manycore processor

Large grain 3D

partitionning



2012 Semicon Europa - P. Leduc

3D Cache Memory on manycore Non-uniform Memory Architecture (NUMA) : spliting uniform cache into

multiple banks interconnected with a NOC

3D stacking adding flexibility, high capacity and a gain on power consumption

High bandwidth and fault tolerance

Eric Guthmuller et al., “Adaptive Stackable 3D

Cache Architecture for Manycores”, ISVLSI2012

1Oµm TSV pitch required

>10000 TSVs per chip


2012 Semicon Europa - P. Leduc | 25

TSV shrink for cost reduction

Surface Cost TSV surface + Keep away zone (KAZ)

Active + M1-Mx layers

Number of TSVs (today 1000 for Wide IO memory)

KAZ

TSV diameter

TSV

Si

Si

0

1

2

3

4

5

6

0 2 4 6 8 10

Su

rfa

ce [

mm

²]

TSV diameter [µm]

Surface occupied by x TSV [mm²]

1000

2000

5000

10000



Low diameter TSV

Reducing Si thickness : 15µm

High Density TSV’s demosntrated in 65nm MOSFETS

3µm

M1

M5

15µm15µm

Investigation on TSV impact on 65nm CMOS devices an d circuitsH. Chaabouni, M. Rousseau, P. Leduc et al., IEDM 2010



Acoustic image of bonding

0.5 µm thick line

>90% yield of daisy Chain with 30000 3x3µm² Cu contacts

Contact resistance : 2,5 mΩ

Cu direct bonding

Contact chain SEM cross section

Res

ista

nce

(Ω)

Full characterization of Cu/Cu direct bonding for 3D integration, Rachid Taibi, Léa Di Ciocciobet al., ECTC2010

standard deviation σ ~ 1.2%

Optical top view



Conclusions

Si interposer has been successfully demonstrated in Leti

Smart Interposers

Promising solution to integrate more devices on Si

3D IC technology is ready for coarse grain partitioning (∼500 TSV/mm²)

Promising solution to reduce the cost of advanced SOC

(<28nm)

Fine grain partitioning for higher performances

Increased density of TSV and interconnects

Low TSV diameter required

Thanks for

your attention

3d technology evolution to smart interposer and high density 3d ics

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