3dic system design impact, challenge and · pdf file3dic system design impact, challenge and...

© 2014 TSMC, Ltd

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TSMC 300mm Wafer with WideIO-1 Parts

3DIC System Design

Impact, Challenge and

Solutions

ISPD 2014

William Wu Shen

March 31st, 2013

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Agenda

From 2D to 3DIC Design

TSMC CoWoStm Test Vehicle Platform

Design Challenges in 3DIC

Next Steps and Design Flow Support

Lesson Learned and Suggestions

Summary

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SoC Integrations Trend

SoC

Function

4

Function

6

Function

5

External Memory

Function

7

Function

1

Function

2 Function

2 Function

3

As Moore’s law predicted, semiconductors density

doubled every two years in last two decades

Logic die can host more and more functions

From Wikipedia, the free encyclopedia, Author: Wgsimon

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Trend for Future SoC Partition

External Memory

Function

5

Function

6

Function

6

Function

4

Function

3 Function

2 Function

1

Function

7

Driven by Cost & Yield

Driven by bandwidth, power and form factors

IO Interface

Logic Core

3DIC Memory

Interposer Carrier

Function

5

Function

5

Function

5

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System Packaging Evolution Trend

Single-die Flip-chip

PoP

Flip-chip MCM

Fan-In WLP Fan-Out WLP

Interposer

Vertical 3D-IC

2

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3D IC Design Paradigm

Partners &

Eco systems

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Agenda


TSMC CoWoS Test Vehicle Platform




Summary

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CoWoS Technology

Technology Optimization

Backside

TSV Reveal

CoW Bonding

oS (Packaging)

Silicon Interposer

Yield Design

Rules

Integrate multiple chips into one single package using a sub-

micron scale silicon interface (interposer)

CoWoS chip chip

chip chip

chip chip

PCB

Substrate 20mm

0.03mm

Tighter integration Cross section view of CoWoS system

Collaborate with customers to shorten time to market

Si-Interposer

C4 bump TSV

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2D - 3D Improvements

Provide wider interface, boost performance

2x HBM stack, BW up to 256GB/s

Save space, wiring distance and power

Est. each HBM ~3.5W, total power ~7W

PCB area reduction from 120x120mm to 40x40mm

CoWoS

8GByte GDDR5 + GPU on 40x40mm substrate

PCB area ~12cmx12cm

8 GDDR5 BW=192GB/s, Power 42W

GPU (10x18mm) with 2 HBM stack on interposer 40x40mm

substrate

2 HBM, 8 die total, 8GByte, BW 256GB/s, Est. power 7W

HBM

HBM GPU

0.03mm

~20mm

40mm

High end Graphic Card Example

GDDR5 GDDR5

GDDR5 GDDR5

GDDR5

GDDR5

GDDR5

GDDR5

GPU

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CoWoS Platform Test Chip with WideIO

DRAM Integration of third party die on interposer

Logic die (40nm)

TSMC DRAM (40nm)

1GHz/1024bits (128 GB/s)

JEDEC Wide-I/O die

200MHz/512bits (12.8 GB/s)

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WideIO DRAM in TSMC CoWoS

200MHz

18.2GB/s

285MHz 12.8GB/s

200MHz +8%=1.32V

-5%=1.14V

JEDEC Spec

WideIO-1 DRAM performs very well on CoWoS structure

At test chip set up, 200Mhz DRAM was overdriven up to 285MHz

with full operations

With limited address and pattern, memory interface reached

380Mhz

200 MHz

300 MHz

400 MHz

1.1V 0.935V 1.265V

380MHz @ 1.1V (Spec. 200MHz)

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Uncertainty with Third Party Die

Wide-I/O DRAM is JEDEC compliant die

JEDEC standard defines the physical foot print of the die

Key Barriers

µbump size, material & density matching between Wide-I/O

DRAM and interposer

Matching of location of support pillars/µbumps

Signal routing and power delivery to Wide-I/O DRAM

Long/short wire/trace analysis to calculate signal/power integrity

affect

Silicon to Standard matching

How to ensure die is compliant to JEDEC standard?

TSMC CoWoS design methodology and routing kit to

address the above challenges

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Agenda






Summary

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Design Challenge & Solutions Complexity vs. Efficiency

Footprint, Power, Performance

3D IC or CoWoS

DFT and Monitors

Testing of dies and stacks (Logic-Logic & Logic-Memory), plug-n-

play

Sensors for thermal and other 3D effects

Test for Packaging

Reliability and testing flow

Thin wafer handling, mechanical stress

Partner and Ecosystem

First time EDA flow adoption, 3D IC specific IPs and IP quality

Analysis and Verification

Heterogeneous dies integration knowhow

Verification of 3D elements, stack-level STA

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Multi-Tower 3D-DFT Architecture

Industry’s first multi-tower

architecture based on

IEEE 1500 Std.

Position of PAD cells and

wrapper cells is swapped

for clarity

Features

Low-pin count: TAP-

based control from

package pins

Complete tower can be

bypassed during test

Each channel in wide-IO

DRAM can be bypassed

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Supported Modes Example

Three die Interconnect Test (SOC-Wide-I/O DRAM) Test SOC-DRAM Test

SOC-to-Wide-

I/O DRAM SOC-to-TSMC

DRAM

High-speed interface test with the reduce function Instruction set

Exceeds the specification for both interfaces

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Test Flow Optimization

Wafer

Die 1

Interposer

Die 3

Die 2

1

Ubump

development

Ubump

development

Ubump

development

Ubump

development

2

Dicing

Dicing

Dicing

3

4

Molding

&

C4 bump

placement

5

Dicing &

Packaging

6

Pre-bond test

Mid-bond test

Post-bond test

Package test

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Agenda






Summary

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Inter-die LVS/DRC

Integrated IR/EM

Thermal analysis

Package level DFT & BIST

Stacking STA & post-simulation

SSN(SI/PI)/PDN simulation

Stacking System

Substrate routing

Substrate RLC extraction

Package Substrate

Implementation

(Micro-bump alignment

Routing, MiM)

RC Extraction

LVS/DRC

SSN(SI/PI) RLC extraction

PDN RLC extraction

Passive Silicon

Bump assignment

RDL routing

Wafer level DFT & BIST

Micro-bump DRCB

Top Chips

CoWoS and 3D IC Design Solutions

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TSMC 3D / CoWoS IC Readiness

Complete

CoWoS Capability Readiness

Top Chips

Bump Assignment / RDL Routing

Wafer-level DFT & BIST

mbump DRC

Interposer

Bump Alignment & Interposer Routing

RCX

LVS/DRC

SSN (SI/PI) RLC Extraction

PDN RLC Extraction

Substrate Substrate Routing

Substrate RLC Extraction

Stacked

System

Inter-die LVS/DRC

Concurrent IR/EM

Thermal Dissipation Analysis

Package-level DFT & BIST

Stacking STA / Post-sim

SSN (SI/PI) / PDN Simulation

Memory IP Controller, PHY

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Demonstrated vertical stacking of memory on 28nm logic for

mobile applications

Characterized TSV (Through-Silicon-Via) design rule for

customer’s test vehicle design and functional verification

Memory

TSV Logic

Substrate

Bump

Micro Bump

Memory cube on 28HPM DRAM on 28HPM Logic

DRAM Cube 28HPM

TSV / 3D-IC Vertical Stacking

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Completed

3D IC Capability Readiness

Silicon

Chips

Bump Assignment / RDL Routing

Wafer-level DFT & BIST

mbump DRC

Cu-pillar Bump Implementation

Custom Design Support

TSV-to-TSV Coupling RCX / TSV RLC

Subckt Replacement

Substrate Substrate Routing

Substrate RLC Extraction

Stacked

System

Inter-die LVS/DRC

Concurrent IR/EM

Transient Thermal Analysis

Integrated DFT & BIST

Cross-die STA / Post-sim

System PDN Simulation / TSV SSN

Decap/Mimcap Co-optimization

Chip-Package Bump Co-optimization

Memory IP Controller, PHY

Validated with 3DIC

TTS Test Vehicle

WIO-1 Memories

C4

BGA

Package Substrate

SoC

WIO Bump Array WIO Cntrl + PHY

WIO Cntrl + PHY

WIO Cntrl + PHY

WIO Cntrl + PHY

3D IC TTS Design Solution

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Lesson Learned and Proposal - ESD

JEDEC has a very good ESD specification for all chip

IO pins. However in 3DIC, interconnect pins are not

ESD protected to reduce the input loading

capacitance

Only the direct access test pins are ESD protected

DA functions are vendor specified. Different vendor may

use different DA pins and may not protect the unused pins

with ESD

Proposed JEDEC to standardize DA pin set. All DA

pins have to be ESD protected per Human Body

Mode at any time

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Lesson Learned and Proposal –

Boundary Scan needs JEDEC has adopted different Boundary Scan standard or a simplified

version of standard

WIO1 and WIO2 have used a portion of IEEE1149 like design but not a

complete package.

The EDA tools have to be adjusted from IEEE std to adapt the DRAM interface

HBM has adopted the complete IEEE 1500 package

Do not have a standard software interpretation on DRAM

portion of Boundary Scan logic

On WIO1, a small variation generated on one vendor’s software

package may not fit the other vendor’s parts

Suggestion:

Specification has to be carefully defined to avoid ambiguity, which

may cause adoption of different logic interpretations

Continue to encourage adopting full IEEE standard instead of

partial standard

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Lesson Learned and Proposal – Support

balls

JEDEC has defined all signal ball and part of support

ball in the MO file with detailed mechanical drawings

Other mechanical support balls are vendor defined

This makes the over all footprint mismatch one vendor parts

to others

JEDEC has started standardizing all support ball

positions

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Summary

Semiconductor industry will continue to drive the

technology evolution per Moore’s law

The 3D IC transition is here

Better performance, lower power, smaller form factor

Die partitioning improves yield

It has create different dimension from Moore’s law

More than Moore system integration enabled by TSMC

3DIC and FOWLP solutions

CoWoS Reference Flow released at OIP 2012

3DIC TTS Reference Flow released at OIP 2013

3dic system design impact, challenge and · pdf file3dic system design impact, challenge and...

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