3_files and programs

7/28/2019 3_Files and Programs

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MicroLogix PackagedControllers

ProgrammableController

Basics

Files And Programs


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We are going to discuss...

1. What Are Program Files

2. Program File Functions

3. Ladder Logic Concepts

4. I/O Addressing

5. Logic

6. Examples


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Memory Organization

MicroLogix 1000

MEMORY

PROGRAM

FILES 01

23

45

6 - 15

S

ystem

Reserved

MainProgram

ErrorFile

HSCFile

STIFile

Subroutine

Files

DATAFILES 01

23

45

67

OutputFile

InputFile

StatusFile

BitFile

TimerFile

CounterFile

Control

File

Intege

rFiles

MicroLogix 1000 only


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Memory Organization

PROGRAM

FILES 01

23

45

6 - 15

S

ystem

Reserved

MainProgram

ErrorFile

HSCFile

STIFile

Subroutine

Files

MicroLogix 1000

MEMORY

MicroLogix 1000 only


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File 0 - System File

Dedicated & Reserved file Used to store various system related information.

Processor type and configuration

Communication parameters

I/O configuration

Passwords

Misc...


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File 1 - Reserved

Future

New enhancements

New features

New functionality


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File 2 - Main Program

Dedicated & Open file

Main Ladder Program

Typically is where the main user program resides

Must have some program logic


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File 3 - Error File

Preconfigured and Open file Referred to as the Error Subroutine

Will be scanned whenever a recoverable fault is detected (Allows users to clearcertain errors and inhibit a shutdown)

Recoverable faults include:

Retentive data lost (0005)

Startup protection after power loss (0016)

Minor Error at end of scan (0020)

File boundaries violated ( Sequencers 0032, Stacks and Bit Shifts (0033)

Negative data in ACC or PRE of a timer (0034)

Invalid HSC preset (0037)

May be used as a user subroutine, but is not recommended


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File 4 - High Speed Counter File

Preconfigured and Open file Referred to as the HSC Subroutine

Will be scanned whenever a HSC interrupt occurs

HSC Interrupts are:

Preset data value is reached (High or Low) Underflow or Overflow conditions are detected



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File 5 - Selectable Timed Interrupt File

Preconfigured and Open file

Referred to as the STI subroutine

Scanned whenever the STE instruction is set (1)

Adjustable interval, 10msec resolution



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Files 6-15 - User Subroutines

Open Files Typically used for application specific requirements.

Accessed from file 2 (Main program) through special program

flow instructions

JSR Jump to Subroutine and return SBR Subroutine Identifier

RET Ret to Main program

Nesting of subroutines is allowed(8 Levels allowed, 3 Levels if the

Error, HSC or STI subroutines are enabled) MicroLogix 1000 and SLC 500 only


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What is Relay Ladder Logic?

Is the primary programming language for PLCs

A graphical representation of the program designed to look like

relay logic

Relay Ladder Logic (RLL)


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Ladder Logic Concepts

| | |/|

Read / Conditional

Instructions

Write / Control

Instructions

| | |/|

| | |/|

| |

| | |/| ( )

| |

( )

( )

( )

( )

| |

Start (Rung #1)

End (Rung #5)


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Ladder Logic Concepts

Read / Conditional

Instructions

Write / Control

Instructions

No Logical Continuity

|/| | |T F F

|/| |/|

( )

( )

T T T

Logical Continuity


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Logical AND Construction

IF input 4AND input 5 have power

THEN energize output 0

| |I/4

| |I/5

( )O/0

Logical Continuity

T T T

On


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Complex Construction

|/|I/11

| |I/5

|/|I/7

|/|I/1

| |I/3

| |I/2

| |I/4

|/|I/0

| |I/1

| |I/1

|/|I/8

| |I/9

( )O/0

| |I/10


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Read Instructions

Unused I / 2I / 1I / 0COM I / 3 I / 6I / 5COMI / 4 I / 7 I / 9I / 8

Supply

Voltage

Unused

LS 1

False

True

Examine OFF

-|/|-XIO

False

The instruction is:

The inputbit is

Logic 0

Logic 1True

Examine ON

-| |-XIC

If theinput

device is

Open (0)

Closed (1)


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Write Instruction

Rung

StateOutput

Bit

Output

Terminal

De-energized

TRUE

FALSE

ON

OFF

OTE

Output Energize

-( )-

| | |/| ( )T T T

ENERGIZED

GNDL 1 O / 0VAC

VDC

L 2 / N VAC

VDC

VAC

VDC

O / 2VAC

VDC

O / 1 O / 3 O / 5O / 4VAC

VDC

SupplyVoltage


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Putting it Together

| | ( )

I/8 O/0

GNDL 1 O / 0VAC

VDC

L 2 / N VAC

VDC

VAC

VDC

O / 2VAC

VDC

O / 1 O / 3 O / 5O / 4VAC

VDC

Supply

Voltage

Unused I / 2I / 1I / 0COM I / 3 I / 6I / 5COMI / 4 I / 7 I / 9I / 8

Supply

Voltage

Unused

PB1


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Addressing Example

L1 L2

PB1 LS1 PS2 SOL6

DEVICE

PB1

LS1

PS2

SOL6

| | ( )| | | |I/5 I/6 O/0I/7

HHP

I/5

I/6

I/7

O/0

Logix

I:0/5

I:0/6

I:0/7

O:0/0

ADDRESS


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INPUT Address Assignment:PB1- I/4 PB2- I/5

LS1- I/6 LS2- I/7

LS3- I/8 LS4- I/9

OUTPUT Address Assignment:

SOL2- O/0 M1- O/1

|/|

CR3

CR3 M1

PB1 LS1 SOL2

PB2LS1

LS3

LS4

I/8

I/4 I/6 O/0

O/1

| | | | ( )

I/5I/7 B/0

| | | | ( )

| |

|/|B/0

( )

Relay Logic to Ladder Logic

| |I/9

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