3mm x 3mm 5mm x 5mm smallest tec power drivers for optical … · 2013. 6. 4. · and bias the tec...

General DescriptionThe MAX8520/MAX8521 are designed to drive thermo-electric coolers (TECs) in space-constrained opticalmodules. Both devices deliver ±1.5A output currentand control the TEC current to eliminate harmful currentsurges. On-chip FETs minimize external components andhigh switching frequency reduces the size of externalcomponents.

The MAX8520 and MAX8521 operate from a single supplyand bias the TEC between the outputs of two synchro-nous buck regulators. This operation allows for temper-ature control without “dead zones” or other nonlinearitiesat low current. This arrangement ensures that the controlsystem does not hunt when the set point is very close tothe natural operating point, requiring a small amount ofheating or cooling. An analog control signal preciselysets the TEC current.

Both devices feature accurate, individually adjustableheating current limit and cooling current limit, alongwith maximum TEC voltage limit to improve the reliabilityof optical modules. An analog output signal monitorsthe TEC current. A unique ripple cancellation schemehelps reduce noise.

The MAX8520 is available in a 5mm x 5mm thin QFNpackage and its switching frequency is adjustable up to1MHz through an external resistor. The MAX8521 is alsoavailable in a 5mm x 5mm thin QFN, as well as a space-saving 3mm x 3mm UCSP™, with a pin-selectableswitching frequency of 500kHz or 1MHz.

ApplicationsSFF/SFP Modules

Fiber-Optic Laser Modules

Fiber-Optic Network Equipment

ATE

Biotech Lab Equipment

Features Circuit Footprint of 0.31in2

Low-Profile Design

On-Chip Power MOSFETs

High-Efficiency Switch-Mode Design

Ripple Cancellation for Low Noise

Direct Current Control Prevents TEC CurrentSurges

5% Accurate Adjustable Heating/Cooling CurrentLimits

2% Accurate TEC Voltage Limit

No Dead Zone or Hunting at Low Output Current

ITEC Monitors TEC Current

1% Accurate Voltage Reference

Switching Frequency Up to 1MHz

Synchronization (MAX8521)

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Smallest TEC Power Drivers for Optical Modules

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2586; Rev 0; 10/02

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

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AL

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TIO

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ITA

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PART TEMP RANGE PIN-PACKAGE

MAX8520ETP -40°C to +85°C 20 Thin QFN 5mm x 5mm

MAX8521EBX -40°C to +85°C 36 UCSP 3mm x 3mm

MAX8521ETP -40°C to +85°C 20 Thin QFN 5mm x 5mm

UCSP is a trademark of Maxim Integrated Products, Inc.

INPUT3V TO 5.5V

VDDPVDD

COMP

GND

SHDN

ITEC

ONOFF

TEC CURRENTMONITOR

CTLI

LX1

PGND1

CS

OS1

OS2LX2

PGND2

TEC ITEC = ± 1.5A

REF

CURRENT-CONTROL

SIGNAL

FREQ

ANALOG /DIGITALTEMPERATURE CONTROL

OUTPUT

MAX8521

Typical Operating Circuit

Pin Configurations appear at end of data sheet.

3mm x 3mm

CSP

5mm x 5mm

QFN

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ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

VDD to GND..............................................................-0.3V to +6VSHDN, MAXV, MAXIP, MAXIN,

CTLI to GND.........................................................-0.3V to +6VCOMP, FREQ, OS1, OS2, CS, REF,

ITEC to GND...........................................-0.3V to (VDD + 0.3V)PVDD1, PVDD2 to GND...............................-0.3V to (VDD + 0.3V)PVDD1, PVDD2 to VDD ...........................................-0.3V to +0.3VPGND1, PGND2 to GND .......................................-0.3V to +0.3VCOMP, REF, ITEC Short to GND ...................................IndefiniteLX Current (Note 1) ........................................±2.25A LX Current

Continuous Power Dissipation (TA = +70°C)20-Pin 5mm x 5mm x 0.9mm QFN (derate 20.8mW/°Cabove +70°C) (Note 2)...................................................1.67W3mm x 3mm UCSP (derate 22mW/°Cabove +70°C).................................................................1.75W

Maximum Junction Temperature .....................................+150°CStorage Temperature Range .............................-65°C to +150°CLead Temperature (soldering 10s) ..................................+300°C

ELECTRICAL CHARACTERISTICS(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 3). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF,TA = 0°C to +85°C, unless otherwise noted. Typical values at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Supply Range VDD 3.0 5.5 V

Maximum TEC Current ±1.5 A

Reference Voltage VREF VDD = 3V to 5.5V, IREF = 150µA 1.485 1.5 1.515 V

Reference Load Regulation ∆VREF VDD = 3V to 5V, IREF = 10µA to 1mA 1.2 5.0 mV

VMAXI_ = VREF 140 150 160VDD = 5V

VMAXI_ = VREF/3 40 50 60

VMAXI_ = VREF 143 150 155MAXIP/MAXIN ThresholdAccuracy

VDD = 3VVMAXI_ = VREF/3 45 50 55

mV

VDD = 5V, I = 0.2A 0.09 0.14NFET On-Resistance RDS(ON-N)

VDD = 3V, I = 0.2A 0.11 0.16Ω

VDD = 5V, I = 0.2A 0.14 0.23PFET On-Resistance RDS(ON-P)

VDD = 3V, I = 0.2A 0.17 0.30Ω

VLX = VDD = 5V, TA = +25°C 0.03 4NFET Leakage ILEAK(N)

VLX = VDD = 5V, TA = +85°C 0.3µA

VLX = 0, TA = +25°C 0.03 4PFET Leakage ILEAK(P)

VLX = 0, TA = +85°C 0.3µA

500kHz mode 11 14VCOMP = VREF =1.500V, VDD = 5V 1MHz mode 16 21

500kHz mode 8 11No-Load Supply Current

IDD(NOLOAD) VCOMP = VREF =

1.500V, VDD = 3.3V 1MHz mode 11 14

mA

Shutdown Supply Current IDD-SD SHDN = GND, VDD = 5V (Note 4) 2 3 mA

Thermal Shutdown TSHUTDOWN Hysteresis = 15°C +165 °C

VDD rising 2.50 2.65 2.80UVLO Threshold VUVLO

VDD falling 2.40 2.55 2.70V

Note 1: LX has internal clamp diodes to PGND and PVDD. Applications that forward bias these diodes should take care not to exceedthe IC’s package power dissipation limits.

Note 2: Solder underside metal slug to PC board ground plane.

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ELECTRICAL CHARACTERISTICS (continued)(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 3). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF,TA = 0°C to +85°C, unless otherwise noted. Typical values at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MAX8521, FREQ= VDD, VDD = 3V to 5V 0.8 1 1.2

MAX8521, FREQ= 0, VDD = 3V to 5V 0.4 0.5 0.6

MAX8520, REXT = 60kΩ, VDD = 5V 0.8 1 1.2

MAX8520, REXT = 60kΩ, VDD = 3V 0.76 0.93 1.10

MAX8520, REXT = 150kΩ, VDD = 5V 0.4 0.5 0.6

Internal Oscillator SwitchingFrequency

fSW-INT

MAX8520, REXT = 150kΩ, VDD = 3V 0.36 0.46 0.56

MHz

External Sync Frequency Range 25% < duty cycle <75% (MAX8521 only) 0.7 1.2 MHz

LX_ Duty Cycle (Note 5) 0 100 %

OS1, OS2, CS Input CurrentIOS1, IOS2,

ICS0 or VDD -100 +100 µA

SHDN, FREQ Input CurrentISHDN,IFREQ

0 or VDD, FREQ applicable for theMAX8521 only

-5 +5 µA

SHDN, FREQ Input Low Voltage VILVDD = 3V to 5.5V, FREQ applicable for theMAX8521 only

VDD x0.25

V

SHDN, FREQ Input High Voltage VIHVDD = 3V to 5.5V, FREQ applicable for theMAX8521 only

VDD x0.75

V

VMAXV = VREF x 0.67, VOS1 to VOS2 = ±4V,VDD = 5V

-2 +2 %

MAXV Threshold AccuracyVMAXV = VREF x 0.33, VOS1 to VOS2 = ±2V,VDD = 3V

-3 +3 %

MAXV, MAXI_ Input Bias CurrentIMAXV-BIAS,IMAXI_-BIAS

VMAXV = VMAXI_ = 0.1V or 1.5V -0.1 +0.1 µA

CTLI Gain ACTLI VCTLI = 0.5V to 2.5V (Note 6) 9.5 10 10.5 V/V

CTLI Input Resistance RCTLI 1MΩ terminated at REF 0.5 1 2.0 MΩError-Amp Transconductance gm 50 100 160 µS

VITEC Accuracy VOS1 to VCS = ±100mV, VOS1 = VDD/2 -10 +10 %

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ELECTRICAL CHARACTERISTICS(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 2). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA =-40°C to +85°C, unless otherwise noted.) (Note 7)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

Input Supply Range VDD 3.0 5.5 V

Maximum TEC Current ±1.5 A

Reference Voltage VREF VDD = 3V to 5.5V, IREF = 150µA 1.480 1.515 V

Reference Load Regulation ∆VREF VDD = 3V to 5V, IREF = 10µA to 1mA 5 mV

VMAXI_ = VREF 140 160VDD = 5V

VMAXI_ = VREF/3 40 60

VMAXI_ = VREF 143 155MAXIP/MAXIN ThresholdAccuracy

VDD = 3VVMAXI_ = VREF/3 45 55

mV

VDD = 5V, I = 0.2A 0.14NFET On-Resistance RDS(ON-N)

VDD = 3V, I = 0.2A 0.16Ω

VDD = 5V, I = 0.2A 0.23PFET On-Resistance RDS(ON-P)

VDD = 3V, I = 0.2A 0.30Ω

500kHz mode 14VCOMP = VREF =1.500V, VDD = 5V 1MHz mode 21

500kHz mode 11No-Load Supply Current

IDD(NOLOAD) VCOMP = VREF =

1.500V, VDD = 3.3V 1MHz mode 14

mA

Shutdown Supply Current IDD-SD SHDN = GND, VDD = 5V (Note 4) 3 mA

VDD rising 2.50 2.80UVLO Threshold VUVLO

VDD falling 2.40 2.70V

MAX8521, FREQ = VDD, VDD = 3V to 5V 0.8 1.2

MAX8521, FREQ = 0, VDD = 3V to 5V 0.4 0.6

MAX8520, REXT = 60kΩ, VDD = 5V 0.8 1.2

MAX8520, REXT = 60kΩ, VDD = 3V 0.76 1.10

MAX8520, REXT = 150kΩ, VDD = 5V 0.4 0.6

Internal Oscillator SwitchingFrequency

fSW-INT

MAX8520, REXT = 150kΩ, VDD = 3V 0.36 0.56

MHz

External Sync Frequency Range 25% < duty cycle <75% (MAX8521 only) 0.7 1.2 MHz

LX_ Duty Cycle (Note 5) 0 100 %

OS1, OS2, CS Input CurrentIOS1, IOS2,

ICS0 or VDD -100 +100 µA

SHDN, FREQ Input CurrentISHDN,IFREQ

0 or VDD, FREQ applicable for the MAX8521only

-5 +5 µA

SHDN, FREQ Input Low Voltage VILVDD = 3V to 5.5V, FREQ applicable for theMAX8521 only

VDD x0.25

V

SHDN, FREQ Input High Voltage VIHVDD = 3V to 5.5V, FREQ applicable for theMAX8521 only

VDD x0.75

V

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ELECTRICAL CHARACTERISTICS (continued)(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 2). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA =-40°C to +85°C, unless otherwise noted.) (Note 7)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

VMAXV = VREF x 0.67, VOS1 to VOS2 = ±4V,VDD = 5V

-2 +2 %

MAXV Threshold AccuracyVMAXV = VREF x 0.33, VOS1 to VOS2 = ±2V,VDD = 3V

-3 +3 %

MAXV, MAXI_ Input Bias CurrentIMAXV-

BIAS,IMAXI_-BIAS

VMAXV = VMAXI_ = 0.1V or 1.5V -0.1 +0.1 µA

CTLI Gain ACTLI VCTLI = 0.5V to 2.5V (Note 6) 9.5 10.5 V/V

CTLI Input Resistance RCTLI 1MΩ terminated at REF 0.5 2.0 MΩError-Amp Transconductance gm 50 160 µS

VITEC Accuracy VOS1 to VCS = ±100mV, VOS1 = VDD/2 -10 +10 %

Note 3: Enter 1MHz mode by tying a 60kΩ resistor from FREQ to ground for the MAX8520, and tying FREQ to VDD for the MAX8521.Note 4: Includes PFET leakage.Note 5: Duty-cycle specification is guaranteed by design and not production tested.Note 6: CTLI Gain is defined as:

Note 7: Specifications to -40°C are guaranteed by design and not production tested. A

VV VCTLI

CTLI

OS CS=

−( )∆

∆ 1

Typical Operating Characteristics(VDD = 5V, circuit of Figure 1, TA = +25°C, unless otherwise noted)

EFFICIENCY vs. TEC CURRENT(VDD = 5V, RTEC = 2Ω)

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TEC CURENT (A)

EFFI

CIEN

CY (%

)

1.41.20.8 1.00.4 0.60.2

10

20

30

40

50

60

70

80

90

00 1.6

FREQ = 500kHz

FREQ = 1MHz

EFFICIENCY vs. TEC CURRENT(VDD = 3.3V, RTEC = 1.3Ω)

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2

TEC CURRENT (A)

EFFI

CIEN

CY (%

)

1.41.20.8 1.00.4 0.60.2

10

20

30

40

50

60

70

80

90

00 1.6

FREQ = 500kHz

FREQ = 1MHz

COMMON-MODEOUTPUT VOLTAGE RIPPLE

MAX8520/21 toc03

400ns/div

VOS220mV/divAC-COUPLED

VOS120mV/divAC-COUPLED

ITEC = 1A

C2 = C7 = 1µF

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DIFFERENTIALOUTPUT VOLTAGE RIPPLE

MAX8520/21 toc04

400ns/div

VOS2 - VOS11mV/divAC-COUPLED

C2 = C7 = 1µF

ITEC = 1A

VDD RIPPLEMAX8520/21 toc05

400ns/div

VDD20mV/divAC-COUPLED

ITEC = 1A

TEC CURRENT RIPPLEMAX8520/21 toc06

400ns/div

10mA/divAC-COUPLED

0A

1.5A

TEC CURRENT vs. CTLI VOLTAGEMAX8520/21 toc07

20ms/div

VCTLI1V/div

ITEC1A/div

0A

0V

ZERO-CROSSING TEC CURRENTMAX8520/21 toc08

1ms/div

VCTLII00mV/div

ITEC100mA/div

0A

1.5V

VITEC vs. TEC CURRENT

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9TEC CURRENT (A)

V ITE

C (V

)

1.51.00.50-0.5-1.0-1.5

0.5

1.0

1.5

2.0

2.5

3.0

0-2.0 2.0

Typical Operating Characteristics (continued)(VDD = 5V, circuit of Figure 1, TA = +25°C, unless otherwise noted)

ITEC vs. AMBIENT TEMPERATURE

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AMBIENT TEMPERATURE (°C)

TEC

CURR

ENT

(A)

6040200-20

0.460

0.470

0.480

0.490

0.500

0.510

0.520

0.450-40 80

FREQ = 1MHzVCTLI = 2VRTEC = 1Ω

SWITCHING FREQUENCYvs. TEMPERATURE

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TEMPERATURE (°C)

SWIT

CHIN

G FR

EQUE

NCY

(kHz

)

806040200-20

500

600

700

800

900

1000

1100

400-40

FREQ = 1MHz

VCTLI = 1.5VRTEC = 1Ω

FREQ = 500kHz

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SWITCHING FREQUENCY CHANGE vs. VDD

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VDD (V)

SWIT

CHIN

G FR

EQUE

NCY

CHAN

GE (k

Hz)

5.04.54.03.5

200

400

600

800

1000

1200

03.0 5.5

FREQ = 500kHz

FREQ = 1MHz

SWITCHING FREQUENCY vs. REXT

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REXT (kΩ)

SWIT

CHIN

G FR

EQUE

NCY

(kHz

)

14012010080

500

600

700

800

900

1000

1100

40060 160

VDD = 3.3V

VDD = 5V

VDD STEP RESPONSEMAX8520/21 toc19

10ms/div

VDD2V/div

ITEC10mA/div

1A

0V

REFERENCE VOLTAGE CHANGE vs. VDD

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VDD (V)

REFE

RENC

E VO

LTAG

E CH

ANGE

(mV)

5.04.54.03.5

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

-1.43.0 5.5

REF SOURCING 150µA

REFERENCE VOLTAGE CHANGEvs. TEMPERATURE

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TEMPERATURE (°C)

REFE

RENC

E VO

LTAG

E CH

ANGE

(mV)

8040 600 20-20

-4

-3

-2

-1

0

1

2

3

4

5

-5-40

REF SOURCING 150µA

REFERENCE VOLTAGE CHANGEvs. LOAD CURRENT

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LOAD CURRENT (mA)

REFE

RENC

E VO

LTAG

E CH

ANGE

(mV)

0.80.60.40.2

-10

-8

-6

-4

-2

0

-120 1.0

STARTUP AND SHUTDOWN WAVEFORMSMAX8520/21 toc17

200µs/div

VSHDN5V/div

ITEC500mA/div

IDD200mA/div

0mA

0mA

0V

CTLI STEP RESPONSEMAX8520/21 toc18

1ms

VCTLI1V/div

ITEC1A/div

0A

1.5V

Typical Operating Characteristics (continued)(VDD = 5V, circuit of Figure 1, TA = +25°C unless otherwise noted)

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Typical Operating Characteristics (continued)(VDD = 5V, circuit of Figure 1, TA = +25°C unless otherwise noted)

THERMAL STABILITY,COOLING MODE

MAX8520/21 toc20

4s/div

TEMPERATURE0.001°C/div

TTEC = +25°CTA = +45°C

THERMAL STABILITY,ROOM TEMPERATURE

MAX8520/21 toc21

4s/div


TTEC = +25°CTA = +25°C

THERMAL STABILITY,HEATING MODE

MAX8520/21 toc22

4s/div


TTEC = +25°CTA = +5°C

Pin Description

PIN

QFN UCSPNAME FUNCTION

1 E1, E2 LX1 Inductor Connection. LX1 is high-impedance in shutdown.

2 D1, D2, D3 PGND1Power Ground 1. Internal synchronous-rectifier ground connection. Connect all PGNDpins together at power ground plane.

3 C1 SHDN Shutdown Control Input. Pull SHDN low to turn off PWM control and ITEC output.

4 C2 COMP Current-Control Loop Compensation. Refer to the Compensation Capacitor section.

5 B1 ITECTEC Current-Monitor Output. The ITEC output voltage is a function of the voltage acrossthe TEC current-sense resistor. VITEC = VREF + 8 (VOS - VCS). Keep capacitance on ITEC<150pF.

6 A1 MAXIN

Maximum Negative TEC Current. Connect MAXIN to REF to set default negative currentlimit to -150mV/RSENSE. To lower this current limit, connect MAXIN to a resistor dividernetwork from REF to GND. The current limit will then be equal to -(VMAXIN/VREF) x(150mV/RSENSE).

7 A2 MAXIPMaximum Positive TEC Current. Connect MAXIP to REF to set default positive current limitto 150mV/RSENSE. To lower this current limit, connect MAXIP to a resistor divider networkfrom REF to GND. The current limit will then be equal to (VMAXIP/VREF) x (150mV/RSENSE).

8 A3 MAXVMaximum Bipolar TEC Voltage. Connect MAXV to REF to set default maximum TECvoltage to VDD. To lower this limit, connect MAXV to a resistor-divider network from REF toGND. The maximum TEC voltage is equal to 4 x VMAXV or VDD, whichever is lower.

9 A4 REF 1.50V Reference Output. Bypass REF to GND with a 0. 1µF ceramic capacitor.

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PIN

QFN UCSPNAME FUNCTION

10 A5 CTLI

TEC Current-Control Input. Sets TEC current. Center point is 1.50V (no TEC current). Thecurrent is given by:ITEC = (VOS1 - VCS) / RSENSE = (VCTLI - 1.50) / (10 x RSENSE). When (VCTLI - VREF) > 0,then VOS2 > VOS1 > VCS.

11 A6 GND Analog Ground. Start connect to PGND at underside exposed pad for QFN package.

12 B6 VDD Analog Supply Voltage Input. Bypass VDD to GND with a 1µF ceramic capacitor.

For MAX8520: Analog FREQ Set Pin (see the Switching Frequency section).

13 C5 FREQ For MAX8521: Digital FREQ Selection Pin. Tie to VDD for 1MHz operation, tie to GND for500kHz operation. The PWM oscillator can synchronize to FREQ by switching at FREQbetween 700kHz and 1.2MHz.

14 D4, D5, D6 PGND2Power Ground 2. Internal synchronous rectifier ground connection. Connect all PGNDpins together at the power ground plane.

15 E5, E6 LX2 Inductor Connection. LX2 is high impedance in shutdown.

16 F5, F6 PVDD2 Power Input 2. Connect all PVDD inputs together at the VDD power plane.

17 F4 CSCurrent-Sense Input. The current through the TEC is monitored between CS and OS1. Themaximum TEC current is given by 150mV/RSENSE and is bipolar.

18 C6 OS2Output Sense 2. OS2 senses one side of the differential TEC voltage. OS2 is a sensepoint, not a power output. OS2 discharges to ground in shutdown.

19 F3 OS1Output Sense 1. OS1 senses one side of the differential TEC voltage. OS1 is a sensepoint, not a power output. OS1 discharges to ground in shutdown.

20 F1, F2 PVDD1 Power Input 1. Connect all PVDD inputs together at the VDD power plane.

B2, B5,C3, C4

GND2Ground. Additional ground pads aid in heat dissipation. Short to either GND or PGNDplane.

B3, B4E3, E4

N.C. No Connect. Connect no-connect pads to GND2 to aid in heat dissipation.

Pin Description (continued)

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Detailed Description The MAX8520/MAX8521 TEC drivers consist of twoswitching buck regulators that operate together to directlycontrol the TEC current. This configuration creates a differential voltage across the TEC, allowing bidirectionalTEC current for controlled cooling and heating. Controlledcooling and heating allow accurate TEC temperature con-trol to within ±0.01°C. The voltage at CTLI directly setsthe TEC current. An external thermal- control loop is typi-cally used to drive CTLI. Figures 1 and 2 show examplesof the thermal control-loop circuit.

Ripple CancellationSwitching regulators like those used in the MAX8520/MAX8521 inherently create ripple voltage on the output.The dual regulators in the MAX8520/MAX8521 switch inphase and provide complementary in-phase dutycycles so ripple waveforms at the TEC are greatlyreduced. This feature suppresses ripple currents andelectrical noise at the TEC to prevent interference withthe laser diode.

Switching FrequencyFor the MAX8521, FREQ sets the switching frequency ofthe internal oscillator. With FREQ = GND, the oscillatorfrequency is set to 500kHz. The oscillator frequency is1MHz when FREQ = VDD.

For the MAX8520, connect a resistor (REXT in Figure 2)from FREQ to GND. Choose REXT = 60kΩ for 1MHzoperation, and REXT = 150kΩ for 500kHz operation. Forany intermediary frequency between 500kHz and1MHz, use the following equation to find the value ofREXT value needed for VDD = 5V:

where REXT is the resistance given in kΩ, and fs is thedesired frequency given in MHz. Note that for VDD <5V, the frequency is reduced slightly, to the extent ofabout 7% when VDD reaches 3V. This should be takeninto consideration when selecting the value for REXT ata known supply voltage.

Voltage and Current-Limit SettingBoth the MAX8520 and MAX8521 provide control of themaximum differential TEC voltage. Applying a voltageto MAXV limits the maximum voltage across the TEC.The voltage at MAXIP and MAXIN sets the maximumpositive and negative current through the TEC. Thesecurrent limits can be independently controlled.

Current Monitor OutputITEC provides a voltage output proportional to the TECcurrent (ITEC). See the Functional Diagram for moredetails:

VITEC = 1.5V +(8 (VOS1-VCS))

Reference OutputThe MAX8520/MAX8521 include an on-chip voltage ref-erence. The 1.50V reference is accurate to 1% overtemperature. Bypass REF with 0.1µF to GND. REF canbe used to bias an external thermistor for temperaturesensing as shown in Figures 1 and 2.

Thermal and Fault-Current ProtectionThe MAX8520/MAX8521 provide fault-current protectionin either FET by turning off both high-side and low-sideFETs when the peak current exceeds 3A in either FET. Inaddition, thermal-overload protection limits the totalpower dissipation in the chip. When the device’s die junc-tion temperature exceeds +165°C, an on-chip thermalsensor shuts down the device. The thermal sensor turnsthe device on again after the junction temperature coolsdown by 15°C.

Design ProceduresDuty-Cycle Range Selection

By design, the MAX8520/MAX8521 are capable of oper-ating from 0% to 100% duty cycle, allowing both LX out-puts to enter dropout. However, as the LX pulse widthnarrows, accurate duty-cycle control becomes difficult.This can result in a low-frequency noise appearing at theTEC output (typically in the 20kHz to 50kHz range). Whilethis noise is typically filtered out by the low thermal-loopbandwidth, for best results, operate the PWM with a pulsewidth greater than 200ns. For a 500kHz application, therecommended duty-cycle range is from 10% to 90%. Fora 1MHz application, it is from 20% to 80%.

R

fsEXT = × −

901 1

3

TEC CONNECTION THERMISTOR

Heating mode PTC

Cooling mode NTC

Table 1. TEC Connection for Figure 1

TEC CONNECTION THERMISTOR

Heating mode NTC

Cooling mode PTC

Table 2. TEC Connection for Figure 2

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______________________________________________________________________________________ 11

VDD

RSENSE0.09Ω

C21µF

C510µF

L24.7µF

R2

REF

RTHER

LX1

VDD L14.7µF

CS

OS1

OS2

PVDD1

C11µF

C31µF

C41µF

C60.1µF

49.9kΩ

100kΩ

PGND1

PGND2

REF

MAXIP

MAXIN

MAXV

PVDD2MAX8521

LX2

COMP

FREQ

ITEC

ON

OFFSHDN

CTLI GND

0.022µF

10µF243kΩ10kΩ 1µF

510kΩ

100kΩ 10kΩ

TOU3BOUTPUT

DACINPUTS

VDD

VDDREF

C71µFC8

0.1µF

MAX4477

MAX4477

MAX4475

MAX5144

U1

U2

U4

U3A

U3B

Figure 1. MAX8521 Typical Application Circuit

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12 ______________________________________________________________________________________

VDD

RSENSE0.09Ω

C21µF

C510µF

L24.7µF

R2

REFLX1

VDD L14.7µF

CS

OS1

OS2

PVDD1

C11µF

C31µF

C41µF

C60.1µF

49.9kΩ

100kΩ

PGND1

PGND2

REF

MAXIP

MAXIN

MAXV

PVDD2

MAX8520

LX2

COMP

FREQ

ITEC

ON

OFFSHDN

CTLI GND

0.022µF

10µF243kΩ1kΩ 10µF

50kΩ

0.01µF REF

DACINPUTS

VDD

C71µFC8

0.1µF

REXT60kΩ

RTHER

MAX5144

U1

MAX4238

U2

U4

Figure 2. Typical Application Circuit for the MAX8520 with Reduced Op-Amp Count Configuration

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______________________________________________________________________________________ 13

Inductor SelectionThe MAX8520/MAX8521 dual buck converters operatein phase and in complementary mode to drive the TECdifferentially in a current-mode control scheme. At zeroTEC current, the differential voltage is zero; hence, theoutputs with respect to GND are equal to half of VDD.As the TEC current demand increases, one output goesup and the other goes down from the initial point of0.5VDD by an amount equal to 0.5 VTEC (VTEC = ITEC RTEC). Therefore, the operating duty cycle of eachbuck converter depends on the operating ITEC andRTEC. Since inductor current calculations for heatingand cooling are identical, but reverse in polarity, thecalculations only need to be carried out for either one.

For a given inductor and input voltage, the maximuminductor ripple current happens when the duty cycle isat 50%. Therefore, the inductor should be calculated at50% duty cycle to find the maximum ripple current. Themaximum desired ripple current of a typical standardbuck converter is in the range of 20% to 40% of themaximum load. The higher the value of the inductor, thelower the ripple current. However, the size is physicallylarger. For the TEC driver, the thermal loop is inherentlyslow, so the inductor can be larger for lower ripple current for better noise and EMI performance. Pickingan inductor to yield ripple current of 10% to 20% of themaximum TEC current is a good starting point.

Calculate the inductor value as follows:

where LIR is the selected inductor ripple-current ratio,ITEC(MAX) is the maximum TEC current, and fs is theswitching frequency.

As an example, for VDD = 3.3V, LIR = 12%, and fs =1MHz, L = 4.58µH.

Even though each inductor ripple current is at its maxi-mum at 50% duty cycle (zero TEC current), the ripplecancels differentially because each is equal and inphase.

Output Filter CapacitorSelection

Common-Mode Filter CapacitorsThe common-mode filter capacitors (C2 and C7 of Figure1) are used as filter capacitors to ground for each output.The output ripple voltage depends on the capacitance,the ESR of these capacitors, and the inductor ripple current. Ceramic capacitors are recommended for theirlow ESR and impedance at high frequency.

L

V

LIR I fsDD

TEC MAX=

×( )× ×0 25.

( )

CTLI RSENSE

CSREF

OS1

CCOMP

RR

0.5X

REF 1.2XCOMP

PWM4X

LX2

3/4 VDD

1/4 VDD

LX1

-1.2

+1.2

10X

1

gm

Figure 3. Functional Diagram of the Current-Control Loop

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lated as follows:

VRIPPLE(P-P) = LIR x ITEC(MAX) (ESR + 1/8 x C x fs)

A 1µF ceramic capacitor with ESR of 10mΩ with LIR =12% and ITEC(MAX) = 1.5A results in VRIPPLE(P-P) of24.3mV. For size-constraint applications, the capacitorcan be made smaller at the expense of higher ripplevoltage. However, the capacitance must be highenough so that the LC resonant frequency is less than1/5 the switching frequency:

where f is the resonant frequency of the output filter.

Differential Mode Filter CapacitorThe differential-mode filter capacitor (C5 in Figure 1) isused to bypass differential ripple current through theTEC as the result of unequal duty cycle of each output.This happens when the TEC current is not at zero. AsTEC current increases from zero, both outputs moveaway from the 50% duty-cycle point complementarily.The common-mode ripple decreases, but the differentialripple does not cancel perfectly, and there is a resultingdifferential ripple. The maximum value happens whenone output is at 75% duty cycle and the other is at 25%duty cycle. At this operating point, the differential rippleis equal to 1/2 of the maximum common-mode ripple.The TEC ripple current determines the TEC perfor-mance, because the maximum temperature differentialthat can be created between the terminals of the TECdepends on the ratio of ripple current and DC current.The lower the ripple current, the closer to the idealmaximum. The differential-mode capacitor provides alow-impedance path for the ripple current to flow, so thatthe TEC ripple current is greatly reduced. The TEC ripplecurrent can then be calculated as follows:

ITEC(RIPPLE) = (0.5 x LIR x ITEC(MAX)) x (ZC5)/(RTEC+ RSENSE + ZC5)

where ZC5 is the impedance of C5 at twice the switchingfrequency, RTEC is the TEC equivalent resistance, andRSENSE is the current-sense resistor.

Decoupling Capacitor SelectionDecouple each power-supply input (VDD, PVDD1,PVDD2) with a 1µF ceramic capacitor close to the supplypins. In applications with long distances between thesource supply and the MAX8520/MAX8521, additional

bypassing may be needed to stabilize the input supply.In such cases, a low-ESR electrolytic or ceramic capaci-tor of 100µF or more at VDD is sufficient.

Compensation CapacitorA compensation capacitor is needed to ensure current-control-loop stability (see Figure 3). Select the capacitorso that the unity-gain bandwidth of the current-controlloop is less than or equal to 10% the resonant frequencyof the output filter:

where:

fBW = unity-gain bandwidth frequency, less than orequal to 10% the output filter resonant frequency

gm = loop transconductance, typically 100µA/V

CCOMP = value of the compensation capacitor

RTEC = TEC series resistance; use the minimum resis-tance value

RSENSE = sense resistor

Setting Voltage and Current LimitsCertain TEC parameters must be considered to guaranteea robust design. These include maximum positive current,maximum negative current, and the maximum voltageallowed across the TEC. These limits should be used toset the MAXIP, MAXIN, and MAXV voltages.

Setting Max Positive and Negative TEC CurrentMAXIP and MAXIN set the maximum positive and nega-tive TEC currents, respectively. The default current limitis ±150mV/RSENSE when MAXIP and MAXIN are con-nected to REF. To set maximum limits other than thedefaults, connect a resistor-divider from REF to GND toset VMAXI_. Use resistors in the 10kΩ to 100kΩ range.VMAXI_ is related to ITEC by the following equations:

VMAXIP = 10(ITECP(MAX) RSENSE)

VMAXIN = 10(ITECN(MAX) RSENSE)

where ITECP(MAX) is the maximum positive TEC currentand ITECN(MAX) is the negative maximum TEC current.Positive TEC current occurs when CS is less than OS1:

ITEC x RSENSE = OS1 - CS

when ITEC > 0.

ITEC RSENSE = CS - OS1

when ITEC < 0.

Cgf

RR RCOMP

m

BW

SENSE

SENSE TEC≥

× ×

×

242π( )

f

LC= 1

2π


14 ______________________________________________________________________________________

Take care not to exceed the positive or negative cur-rent limit on the TEC. Refer to the manufacturer’s datasheet for these limits.

Setting Max TEC VoltageApply a voltage to the MAXV pin to control the maximumdifferential TEC voltage. MAXV can vary from 0 to REF.The voltage across the TEC is four times VMAXV andcan be positive or negative:

|VOS1 - VOS2| = 4 x VMAXV or VDD, whichever is lower

Set VMAXV with a resistor-divider between REF andGND using resistors from 10kΩ to 100kΩ. VMAXV canvary from 0 to REF.

Control Inputs/OutputsOutput Current Control

The voltage at CTLI directly sets the TEC current. CTLIis typically driven from the output of a temperature con-trol loop. The transfer function relating current throughthe TEC (ITEC) and VCTLI is given by:

ITEC = (VCTLI - VREF) / (10 RSENSE)

where VREF is 1.50V and:

ITEC = (VOS1 - VCS) / RSENSE

CTLI is centered around REF (1.50V). ITEC is zero whenCTLI = 1.50V. When VCTLI > 1.50V, the current flow isfrom OS2 to OS1. The voltages on the pins relate as follows:

VOS2 > VOS1 > VCS

The opposite applies when VCTLI < 1.50V current flowsfrom OS1 to OS2:

VOS2 < VOS1 < VCS

Shutdown ControlThe MAX8520/MAX8521 can be placed in a power-savingshutdown mode by driving SHDN low. When theMAX8520/MAX8521 are shut down, the TEC is off (OS1and OS2 decay to GND) and supply current is reduced to2mA (typ).

ITEC OutputITEC is a status output that provides a voltage proportionalto the actual TEC current. VITEC = REF when TEC currentis zero. The transfer function for the ITEC output is:

VITEC = 1.50 + 8 (VOS1 – VCS)

Use ITEC to monitor the cooling or heating currentthrough the TEC. For stability, keep the load capaci-tance on ITEC to less than 150pF.

Applications InformationThe MAX8520/MAX8521 typically drive a TEC inside athermal-control loop. TEC drive polarity and power areregulated based on temperature information read from athermistor or other temperature-measuring device tomaintain a stable control temperature. Temperature sta-bility of ±0.01°C can be achieved with carefully selectedexternal components.

There are numerous ways to implement the thermal loop.Figures 1 and 2 show designs that employ precision opamps, along with a DAC or potentiometer to set the con-trol temperature. The loop may also be implemented dig-itally, using a precision A/D to read the thermistor orother temperature sensor, a microcontroller to implementthe control algorithm, and a DAC (or filtered-PWM signal)to send the appropriate signal to the MAX8520/MAX8521CTLI input. Regardless of the form taken by the thermal-control circuitry, all designs are similar in that they readtemperature, compare it to a set-point signal, and thensend an error-correcting signal to the MAX8520/MAX8521 that moves the temperature in the appropriatedirection.

PC Board Layout and RoutingHigh switching frequencies and large peak currentsmake PC board layout a very important part of design.Good design minimizes excessive EMI and voltagegradients in the ground plane, both of which can resultin instability or regulation errors. Follow these guide-lines for good PC board layout:

1) Place decoupling capacitors as close to the IC pinsas possible.

2) Keep a separate power ground plane, which is con-nected to PGND1 and PGND2. PVDD1, PVDD2,PGND1, and PGND2 are noisy points. Connectdecoupling capacitors from PVDDs to PGNDs asdirectly as possible. Output capacitors C2 and C7returns are connected to PGND plane.

3) Connect a decoupling capacitor from VDD to GND.Connect GND to a signal ground plane (separatefrom the power ground plane above). Other VDDdecoupling capacitors (such as the input capacitor)need to be connected to the PGND plane.

4) Connect GND and PGND_ pins together at a singlepoint, as close as possible to the chip.

5) Keep the power loop, which consists of inputcapacitors, output inductors, and capacitors, ascompact and small as possible.

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______________________________________________________________________________________ 15

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error, keep the board layout adjacent to the negativeinput pin of the integrator (U2 in Figure1) clean andfree of moisture. Any contamination or leakage current into this node can act to lower the DC gain ofthe integrator, which can degrade the accuracy ofthe thermal loop. If space is available, it can also behelpful to surround the negative input node of theintegrator with a grounded guard ring.

Refer to the MAX8520/MAX8521 evaluation kit for a PCboard layout example.

Chip InformationTRANSISTOR COUNT: 3007

PROCESS: BiCMOS


16 ______________________________________________________________________________________

20 19 18 17

PVDD

1

OS1

OS2

CS

16PV

DD2

13

12

11

14

15

VDD

FREQ

PGND2

LX2

GND

4

3

2

1

COMP

SHDN

PGND1

LX1

5ITEC

6 7 8 9

MAX

IN

MAX

IP

MAX

V

REF

10CT

LI

MAX8520/MAX8521

TOP VIEW

THIN QFN

F6PVDD2

LX2 LX2 N.C. N.C. LX1 LX1

PGND2 PGND2 PGND2 PGND1 PGND1 PGND1

OS2 FREQ GND2 GND2 COMP SHDN

VDD GND2 N.C. N.C. GND2 ITEC

GND CTLI REF MAXV MAXIP MAXIN

PVDD2 CS OS1 PVDD1 PVDD1F5 F4 F3 F2 F1

E6 E5 E4 E3 E2 E1

D6 D5 D4 D3 D2 D1

C6 C5 C4 C3 C2 C1

B6 B5 B4 B3 B2 B1

A6 A5 A4 A3 A2 A1

UCSP

MAX8521

Pin Configurations

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______________________________________________________________________________________ 17

GND

FREQ(MAX8520)

COMP

CTLI

ITEC

MAXIP

FREQ (MAX8521)

PWM CONTROLAND

GATE CONTROLMAXIN

RSENSE

PGND1

PGND2

MAXV

REF

SHDNREF

OS1

OS2

CS

LX1

LX2

ON

OFF

3V TO5.5V

OS1

REF

CS

MAX VTEC =VMAXV × 4OR VDD

MAX ITEC =(VMAXIP/VREF) ×(0.15V/RSENSE)

MAX ITEC =(VMAXIN/VREF) ×(0.15V/RSENSE)

PVDD1

PVDD2VDD

VDD

MAX8520/MAX8521

Functional Diagram

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18 ______________________________________________________________________________________

Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)

QFN

TH

IN.E

PS

D2

(ND-1) X e

e

D

C

PIN # 1 I.D.

(NE-1) X e

E/2

E

0.08 C

0.10 C

A

A1 A3

DETAIL A

0.15 C B

0.15 C A

DOCUMENT CONTROL NO.

21-0140

PACKAGE OUTLINE16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm

PROPRIETARY INFORMATION

APPROVAL

TITLE:

CREV.

21

E2/2

E2

0.10 M C A B

PIN # 1 I.D.

b

0.35x45

L

D/2D2/2

LC

LC

e e

LCCL

k

k

LL

22

21-0140REV.DOCUMENT CONTROL NO.APPROVAL

PROPRIETARY INFORMATION

TITLE:

COMMON DIMENSIONS EXPOSED PAD VARIATIONS

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220.

NOTES:

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

C

PACKAGE OUTLINE16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm

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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19

© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)

36L,

UC

SP

.EP

S

3mm x 3mm 5mm x 5mm smallest tec power drivers for optical … · 2013. 6. 4. · and bias the tec...

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