4.1

4 Circuit Characterization

1. Linear Circuit Components ; R, L & C

2. Dominant Components in each -region(delay, voltage drop)

3. inverter DC & delay characteristics

4. R & C Model for MOSFET’s & wires MOS(internal) device capacitance

Diffusion(external device ; source/drain) capacitance

Routing capacitance, resistance

5. Gate delay input slope

series-connected(stacked) MOSFET configuration : Penfield-Rubinstein model

inverter stage ratio

Contents

4.2

6. CMOS 용 inverter & Power dissipation Static

dynamic

Short-circuit

Ring counter

7. High-Current Effects Power/Ground bounce

EM/ESD/EOS(Electro-migration/Electro-Static Discharge/Electrical Over-Stress)

4.3

1. Linear Circuit components : R, L & C

Resistance CR) : ivR

v iR

i

R

vi=qv

V

t

V

t

VelocitySaturation

m

e

Em

eEav

VLav

2

aVav : mean time

between collision

4.4

Capacitance(C) :

Inductance(L) :

i cdvdt

C1

V

v1

v2

i Advdt

1

i v

iC

v2

i Cdvdt

V L

ii

+ v -

dt

diLV

4.5

2. Dominant components

V=Z • i (z = impedance)

I II III

c L

L

C1

R

Z() 1) region I : C dominates

2) region II : R dominates

3) region III : L dominates

4.6

3. Inverter DC & delay characteristics

Role of inverter : 1. Signal buffering/transmission2. Logic function

10

1 0

0

load

seesaw rope seesaw

seesaw

seesaw balance rdendez-vous2 foods

4.7

Inverter is composed of driver and load

VGS4(8V)

VGS3(6V)

VGS2(4V)

VGS1(2V)

triodelinear

driver(transistor) characteristics Load characteristics

i1 i2

VDS V12

G

D

S

i1RL

1

2

i2in

out

4.8

Putting them together, KCL(Kirchoff’s Current Low) demands i1=i2

VDD

RL

Vo

Vi

i

VDD

i

I = (Vo-VDD)1

RL

Vo

Vi

<Output Characteristics>

<Transfer Characteristics>

RL increase

IdealVo

Vi

4.9

Resistor, as a passive load, requires large silicon area.

RL(10K) = 100 R (100 / )

Active load is better for digital purposes.

Large area(100 s)

VDD

Vi

Vo

GND

4.10

Problems with Enhancement load

1. Slow charge/discharge due to small load current

especially when Vo VDD

2. Vo cannot be raised higher than VDD-VT’

(VT’ : threshold voltage considering body effect)

A

Vi = 5V

Dynamic load line

B VDD-VT VDD

: Static load lineib

2V V VL DD T O

2 ( )

Vi = 0V

Q1

Q2

4.11

i) Static Load Line : iL = iD

ii) Dynamic Load Line(due to load capacitance, CL)

charging(Q1 Q2) ;

iD = iL -

discharging(Q2 Q1) ;

iD = iL +

CdV

dtLo

CdV

dtLo

Magnitude of average charging/discharging current is given

as the area of AQ1Q2B

iL

iD

Vo

CL

VDD

Vi

4.12

How to improve Inverter speed is how to increase charge/discharge current.

Sol. 1. Bootstrap method

Vi

VDD

Vo

T3

T1

T2X

CX

Q2

Q1

Q3

Vi=5V

Dynamic load line(due to CX)

Vi=0V

Static load line

i2

V 2V VL DD T o2

( )

VDD-2VT VDD

I

VO

4.13

Sol.2 Depletion load method

Question) Why cannot one use depletion MOSFET as a logic element ?

VTD<0 VTD>0

ID

Depletionelement

Enhancementelement

0- +VG

VG=0V

ID

VG=0VVDD

VG=-1V

VG=-2V

VG=1V

VG=2V

Depletion type

Enhance-ment type

VG=2V

4.14

Gate and Source terminals of Depletion device is tied together to suppr

ess the Vo-dependence of iL, i.e., iL=(0-VTD)2= VTD 2, acting like a c

onstant current source.

iL

iD

Vi

Vo

VDD Vi=5V

iL=(-VTD)2iD

Vi=0V

VDS(=V0)VDD

body 효과를고려한 부하선

4.15

Speed comparison between R, E, D-load

C

it = 0

VDD

R iV V

RRDD:

E ib

2V 0 2V VE DD DD

2: ( . )

D iV

R0 V 0 4VD

DDDD: , .

V V

0.6R0.4V V VDD

DD DD

,VDD

R

i

VDD

R VDD

0.6R

D

D’R

E

VDD0.8VDD

Charging time vs. voltage

Eq.(1)

Eq.(2)

Eq.(3)

4.16

E

D’

R

dtdV

VDD+VTD=0.4VD

VDD

VDD-VTE=0.8VD

dtdV

Ci=

eq(2) eq(1) 를 invert & integrate 한 curve

eq(3)

t0

t

Output voltage, V

V'

0 )V(i

dVCt

4.17

최대전류값 (Vo=0 일때 ) 이 같도록 한 경우 , R, E, D - 부하 각각의

충전시간의 계산 ;

dt

dVC)V(i

V'

0

)V'(t

0 )V(i

dVCdtt

R-load

VDD

C

R)e1(VV(t) RC

t

DD

eq.(1)

4.18

E-load :

C

VDD

iE(v)v

dt

dVC=V)-V-(V

2)V(i 2

TEDDE

2DD )V(0.8V

dV=dt

2C

t1

0.8V V

1

0 8VDD DD

(.

)

V 0 8V 10.8V

t +0.8V

DDDD

DD

. ( )

eq.(2)

D-load : t 0 4V CV

R0 4RC0 DD

DD . /( ) .

-1

0.4VDD<V<VDD 에서는 0.6R 의 저항을 통한 충전 :

V 0 4V 0 6V 1 expt t

0.6RCDD DD0. . [ ( ) eq.(3)

4.19

Inverter delay()

정의 ) = 한 inverter 가 같은 size 의 연결된 inverter 의 입력전압을

방전시키는 시정수

Cg

RL

RD Cg

SW1

SW2

k

RD

Cg

RL

Cg

RL : depletion 소자 등가저항

RD : driver 의 등가저항

k (W / L)load

(W / L)driver; inverter ratio =

1

4

inverter ratio k is determined as 4, from the following static consideration

DDDD

DD

LD

TDTEinV V

VV

VVV 5.0

1/4

6.02.0

/

4.20

Inverter chain 에서의 충전시정수는 k=4,

방전시정수는 로 주어지며 , fanout 이 n 이거나 부하용량이

CL=mCg 인 경우 , 충방전 시정수는 각각 m 배 !

v1 v2 v3

v1

v2

v3

4.21

Effective load capacitance, CL = CS+ Cgs +2 Cgd >> Cg

Cs

Cgs

mCgd Av: inverter 전압이득

m=1-Av

Miller capacitanceCgd BA

VAv V (1-Av) V ; effective voltage change

Effective capacitance =

( )

( )1

1A V C

VA CV gd

V gd

Total charge change

input voltage change

Miller factorFor digital inverter(1-Av) => 2

4.22

4. R & C Models for MOSFET’s & wires

)(

exp35.0 frompoutpd

PDfDDDD CCR

tVV

135.0

1ln ),(

35.0

1ln)(

poutpdpoutpdPDf CCRCCRt

Transistor as R

4.23

B

S

G

CGS

D

CGD

CDBCSB

CGB

MOSFET Capacitance

CGB

CGS

CGD

CG(total)

off

0

0

0

non-sat.

0

sat.(short-channel)

0depOX CC ||

OXC2

1

OXC2

1

OXC

)9.0(3

2OXOX CC

)1.0(0 OXC

)(3

2OXOX CC

MOSFET: 4-terminal device

i) Gate capacitance

0.5

2/3

off sat. lin. VGS

CGB

CGS

CG=CGS+CGD+CGB

CGDC[COX]

4.24

MOSFET parastic capacitance(=junction cap.+overlap cap.)

4.25

ii) Junction capacitance

junction) edge channel(

junction) sidewall(

junction) (bottom

BSJGATE

BSSW

BSJBS

C

C

CC

JmBBSJSBSJ VCAC )/1( 56.0 :ex Jm

SJWmBBSJSWSBSSW VCPC )/1( 52.0 :ex JSWm

Sidewall junction is more abrupt

4.26

iii) Overlap capacitance(due to lateral diffusion)

DeffGSOeffGBOV

DeffGSOeffGDOVGSOV

LLLCLC

WWWCWCC

2 ,

2 ,

4.27

Capacitance, Conductance values(typical) for SPICE

DS

DSds

BS

DSmb

GS

DSm V

Ig

V

Ig

V

Ig

, ,

4.28

iv) Routing Capacitance

S W

t

Cp

Cf

CswCp: fringing cap.

Csw: sidewall cap.

Cp: planar cap.

Cf

Csw

Cp

For high-(t/w), multi-bit bus, Csw dominates.

W(=S)

Assume t=const

4.29

Distributed RC line

R = r dx (r:resistance per length)

C = c dx(c:capacitance per length)

CdV

dt

V V

R

V V

Rj j j j j

1 1

rcdVdt dx

V V Vd Vdxj j j

122 1 1

2

2( )( ) : Diffusion equation

2);( kxtt

xfV x (tx : time for propagating distance x)

R R R R

C C C

Vj-1 Vj Vj+1

4.30

Frequency domain solution of the distributed RC line to unit step input is

SRCS

LsVout

cosh)(

RCtt

RCerfctVout ,

4)(

1 1 2 0 9 .36 exp( .54 / ) .37exp( .46 / ),t RC t RC t RC

as cosh(x) =e ex x

2

ex

x

21,

12 4

12 4

x x

x! !

,

4.31

Distributed vs. Lumped

Time elapsedTime elapsed

Distributed LumpedLumped

0 - 90%

0 - 63%

0 - 10%

0 - 90%

0 - 63%

0 - 10%

RC

0.5RC

0.1RC

RC

0.5RC

0.1RC

2.3RC

RC

0.1RC

2.3RC

RC

0.1RC

R

C

R

C(Distributed) (Lumped)

Vout

DL

time

4.32

Characteristic of Diffusion : tx kx2

For t=410-15 2[ in m]

I) with buffer

tp = 8ns + buf

ii) without buffer

tp = 16nsbuffer

1mm 1mm

x1 2 3 40

t=1t=4

t=9t=16

4.33

5. Gate Delay tT = tD + ti + tslew, tslew = rslew CL

tD : internal delay of the cell

ti = delay due to the intrinsic output capacitance

rslew : output slew rate [ns/pF]

CL : load capacitance for each output

tD = tD,O Kt Kv Kp

processprocess KpKp

Slow

typ.

fast

Slow

typ.

fast

1.34

1.00

0.72

1.34

1.00

0.72

input

output tD ti

tslewEx. tQ=1.39+0.83+1.63CL

KV Kt

VDD3.0 3.3 3.6 -30 RT +90

4.34

input slope dependence

t tn

tf f o r in

, ,

1 26

(n = , : input rise time)VV

Tn

DD

tr in,

t tp

tr r o f in

, ,

1 26

(p = , : input fall time)V

VTP

DD

tf in,

4.35

Series-connected(stacked) MOSFET Configuration

Penfield-Rubinstein model : t R Cd ii

i

Ri : Summed resistance from i to power/ground

Ci : Capacitance at point i

td = R1C1 + (R1+R2)C2 + (R1+R2+R3)C3 + (R1+R2+R3+R4)C4

= R1(C1+C2+C3+C4) + R2(C2+C3+C4)+R3(C3+C4)+R4C4

Elmore delay model

A

B

C

D C1

C2

C3

N1

N2

N3

N4C4

4.36

Elmore delay

TAB = R1(C2+C3+C4 +C5 +C6 +C7 +C8 +C9 +C10)

+R2( +C3+C4 +C5 + C6 +C7 +C8 +C9 +C10 )

+R3( +C4 +C5 + C6 +C7 +C8 +C9 +C10)

C2

2C3

2

TBD = R4( +C7 +C8 +C9)

+R7( +C9)

24C

27C

TBE = R5( +C6 +C10)

+R6( +C10)

C5

2C6

2

4.37

Delay Modelling

i) 50%-50% delay : for multiple levels of static logic circuit

4.38

ii) 10%-90%(90-10) delay : rise time(fall time)

: for precharged dynamic circuit

4.39

Delay model of interconnection driven by Rtr & terminated by CL

T90% = 1.0RintCint + 2.3(RtrCint+

RtrCL+ RintCL)

Rint

Cint

Rtr

CL

4.40

Inverter Stage Ration

Driving large C load using graded inverter chain

CLCg

f2 fNf1

Q. Determine the scale-up factor, f

minimizing total delay time for driving CL from Cg

4.41

A. mumber of inverters, N is given by

Total delay is Nf, which is to be minimized.

Total delay = =

* In real situation, f could be much larger than 2.7 to reduce the chip area consumption

fCC

N L

g

=Y, i.e., N=

n

n

Yf

fromNff

Yf

ffn

n

( )( )

n

n

f ff

f

1

02( ) nf f e1 2 7.

Ne eCCn

L

g

4.42

6. CMOS Inverter & Power Dissipation

Static Transfer Characterictic

I

PMOS

NMOS

Vi Vo

VDD

G

G

D

D

S

S(VSS or GND)

0 VTN

VDD- VTD

VDDVDD

2

VDD

Vo

A B D E

C

Vi

Region A

Region B

Region C

Region D

Region E

NMOS

cutoff

sat

sat

linear

linear

PMOS

linear

linear

sat

sat

cutoff

Static powerdissipation

4.43

Adjustment of VTN, VTP

i) VTN + VTP < VDD-VSS : static current flows

ii) VTN + VTP = VDD-VSS : ideal case

iii) VTN + VTP > VDD-VSS : hysteresis

Both are off0 VDD

VTN

VTP

PMOS NMOS

VoVi

VTN

Vi

VDD-VTP

VoVo

Vi

4.44

Influence of PN asymmetry on the transfer characteristics

Vi

Vo

VDD

1p

n

infinite transfer gain 0.1 10

ideal zero output conductance

4.45

Power Consumption

i) dynamic power dissipation

ni

pi

LC

VoVi

t=0 pt2ptVi

Vo

Ptp

in t V dttp

i t V V dtdyn o p DDtp

tptp

o 1 1

20

2 ( ) ( )( )

i t CdVdtn L

o( ) Substituting, and i t CdVdtp L

o( )

PCtp

V dVCtp

V VdynL

o O

V L

V DD o

DD

DD

0

0( )

C V

tpC V fL DD

L DD2

(f : switching frequency)

eq.(1.11)

4.46

Energy stored in CL charged up to VDD is

C VL DD2

Q V dV C vdV C VL

V V

L DD

DD DD

( ) 0 0

212

from eq.(1.11), switching energy consumed per cycle is

where did 12

2C VL DDgo ?

4.47

Modelling of resistive dissipation in ideal switch

replace MOSFET by ideal switch in serial with a resistance, R

i) In Vo’s going up ;

Vo

LC

R

R

i

VDD

E i Rdt i RCdV

CdVdt

diss

t

L

V o

Lo

DD

,

( )1

2

0

2

0

1

RC idv RCV V

RdVL o L

DD oVV

o

DDDD

00

12

2C VL DD (indep. of R!) ; energy dissipated

in R as Vo is being raised from 0 to VDD

4.48

ii) In Vo’s going down

LCR

i

E i Rdt i RCdV

CdVdt

diss t

t

LV

o

Lo

p

DD,

( )2

2 20

1

RC idV RCVR

dVL o Lo

VV oDDDD

00

C V dVC

VL o o

V LDD

DD

0

2

2

Energy dissipated in R as CL is being discharged

LC

R

R

lose 1/2

lose 1/2store 1/2

VDD

VDD

GND

4.49

iii) Short-circuit dissipation

ref. H.J.M. Veendrick, “Short-circuit dissipation of static CMOS…”

IEEE J. Solid-state Circuits, Vol. SC-19, Aug, 1984. Pp 468-473

assumption: CL = 0

VDD

Vi Voi

i

imax

iav

Vi

VDD

VDD-|VTP|

VDD/2

VTN

r f

T

(A) (B)

t1 t2 t3t=0

4.50

For simplicity, assume , t = tr = tf and VT = VTN = -VTP

(waveform (A) = waveform(B), (A) is symmetric w.r.t t = t2 )

setting

IT

i t dtav

t

t

1

1

2

( ) i t v t Vi T( ) ( ( ) ) 2

2

2,,)( 21

tV

VtV

ttV

DD

TDDi

IT

i t dtT

Vt V dtav

t

tDD

TVV

T

DD

1 2

1

2

2

2

( )

2 2 1

3 2

12

2

2

0

2

2 3

3

Tu

Vdu

T VV

V

T

V V

V

DD

VV

DD

DDT

DD T

DD

DDT

uV

t VDDT

pn

4.51

Short-circuit current waveform with finite CL obtained from SPICE

CL=0CL=200fF=2x10-13F

CL=500fF

CL=1pF

CL=

ISC

200A

VDD - |VTP|

VTN

time(nsec)

time(nsec)

0.8 2 3 4 5

CL

=n=p=170 A/V2

Vt=Vtn=|Vtp|=0.8V

4.52

outputvoltage

CL=0CL=500fF

CL=1pF

time(nsec)PT=Pdyn+ PSC

=20ns

=10ns

=5ns

=1ns

total dissipation(PT)ln PT

ln C*

dynamic dissipation limit

ln CL

: input voltage rise time

PdynPSC

(sec)

For a load capacitance C*, = 5ns in near optimal input transient

C P P

P P

L dyn sc

i sc dyn

: ,

: ,

4.53

I

i1C

i1d

i2C

i2d

i3C

i3d

i4C

i4d

i5C

i5d

VDD

V1 V2 V3 V4 V5

VO

Cg

C) Ring counter for measuring gate delay

4.54

i1C i1d

i2C i2d

i3C i3d

i4C i4d

i5C i5d

g g = T / NT

Total discharge current at I-meter

2g

Power-delay product per gate=energy consumption per switching=QVDD=CgVDD

2=(VDDIDCT/N)*2

)2( gDCDD IV

4.55

7. High-current Effects

Electro-migration: directional movement of charge carriers(DC current)

– causes deformation, breakage of conductor, occurs at the constriction point.

– ex) fuse(positive use of EM effect)

depending on current density, temperature, and crystal structure

limiting current: 2mA/m2

– rule of thumb: use 0.4-1.0mA/ m2 for VDD & VSS

4.56

Power & Ground Bounce temporary level change in the power and ground voltag

e due to sudden change of charging/discharging current

called simultaneous switching noise, I-noise, dI/dt noise

due to iR and/or L di/dt drop in the power/ground rail

originates from large current drivers such as clocking buffer, I/O buffer

4.57

Power-distribution path in IC and the electrical model

4.58

Simplified electrical model of a CMOS chip

4.59

8. Technology scaling(Constant E-field scaling)

4.60

공부를 하고 학위를 받는 것의 가장 큰 의미는 무슨 일을 못하거나 (능력 ) 안하는데 (태도 ) 대한핑계를 제거 해 준다는 것이다 .

공부를 하고 학위를 받는 것의 가장 큰 의미는 무슨 일을 못하거나 (능력 ) 안하는데 (태도 ) 대한핑계를 제거 해 준다는 것이다 .

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