4 digital electronics
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L O G I C G A T E S
F L I P - F L O P S
R E G I S T E R S
A D D E R S
Digital Electronics
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Numbers in a computer:
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In the Microprocessor and memory Bits are storedelectronically
Each bit is represented by an electrical signal which
is either a high or low voltage level. high 1 and low 0
high 0 and low 1
NormalLogic
InverseLogic
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High and Low
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1:
High
0
:
Low
CMOS
NO MANS LAND74HCxx
0.1 1.0 Volts
3.5 4.9 Volts
Transistor TransistorLogic (TTL)
NO MANS LAND74LSxx
0.8 0.4
Volts
2.0 2.4Volts
It is actually a bit more complicated than this since there are different thresholdsfor inputs and outputs and their noise margins (indicated here in RED)..
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Making a Zero or and One
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How do you actually make a 0 or 1 ?
It is clear that dependingupon the position of the J1switch the line will be either
0or 1
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Binary Logic
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Once the bits are stored, we want to be able toperform various operations on the bits
The operations which the microprocessor carries out
can all be constructed with a few simple circuits The basic building blocks are logic gates
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Binary Logic truth tables
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A B AND
0 0 0
0 1 0
1 0 0
1 1 1
A B OR
0 0 0
0 1 1
1 0 1
1 1 1
A NOT
0 1
1 0
You mayrememberfrom the first
year lab the
gates AND,OR, NOT
Any digitaldevice can bemade out of
either ORs andNOTs or ANDsand NOTs.
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DeMorgans Theorem
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You can swap ANDs with ORs if at the same timeyou invert all inputs and outputs :
Exercise:Write truth table for both and prove thatthis is correct
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An AND out of NOTs and ORs
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Exercise: Test the claim that you can make any logicdevice exclusively out of NOTs and ORs by makingan AND out of NOTs and ORs:
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Answer:
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Show that this device has an identical truth tableas the AND gate.
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Exercise: Exclusive OR
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Construct an exclusive OR (XOR)gate using OR, ANDs, and NOT:
A B XOR
0 0 0
0 1 1
1 0 1
1 1 0
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The Exclusive OR
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Solution:
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Storing Zeros and Ones: Registers
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Registers are electronic devices capable of storing 0s or 1s
D-FLIP-FLOPsare the most elementary registers
can store one bit 8 DFFs clocked together make a one byteregister Capable of storing 8 bits
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SR Latch: Set and Reset
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Gate level designof an SR latch
S* R* Q Q*
0 1 1 0
1 0 0 1
When S* is low and R*High, Q is high (Set)
When S* is high and
R* is low Q is cleared(Reset)
Q and Q* arecomplements
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SR Latch: Hold
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Gate level designof an SR latch
S* R* Q Q*
1 1 1 0
1 1 0 1
When S* and R* arehigh both states for Qare possible (andstable)
The latch remembersthe last state it was in,and holds Q in thatstate
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SR Latch: Dont do this
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Gate level designof an SR latch
S* R* Q Q*
0 0 1 1
When S* and R* arelow Q and Q* are nolonger complementary
The latch can alsoenter a race conditionwhere it oscillates
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SR Latch: 1 bit memory
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Gate level design of an SRlatch
S R Q Q*
H H H L
H H L H
H L L H
L H H L
L L H H
S/R high is ambiguous, but stable This circuit remembers that S
went low
Ambiguousbut stable
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Gated D Latch
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Ensures that S and R are always complementary.When the Clock is high D is set on the outputs of the latch and it is held therewhen the clock is lowExercise: Fill out the truth table for this circuit.
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D latch timing
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The input Data to the gated D latch appears on the output(Q)while the clock is high.
Sometimes we want to transfer the data into the register onlyat a specified moment (for example when the clock changes)
The D Flip-Flop uses two d-latches to latch the data on theedge (depending on the design either positive or negative) ofthe input clock
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Master Slave D Flip Flop
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Data is stored inthe Master latch(Qm) when theclock is high
When the clock
goes from high tolow The data is held in
the Master The Data is stored in
the slave latch
output The Qsoutput can
only change whenthe clock goes fromhigh to low
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A real D-Flip-Flop (DFF)
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CLK D S R Q Q-bar
X X L H H L
X X H L L H
X X L L H H
H H H H L
L H H L H
When S and R are High, on therising edge of the clock the dataare transferred and stored in Q.
One can Set or Reset (Clear)the DFF using S or R
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4-bit Register
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A register thatstores 4 bits
Data coming inD0,D1,D2,D3
Data Stored on risingedge of clock inQ0,Q1,Q2,Q3
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Byte Register
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8 bit register in a singlepackage
74F574
Also contains tri-state outputs
CLK
Byte coming in
Byte Stored
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Addition with Binary Logic Gates
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Example: Adding two 4 bit numbers results in a 4 bit number plusone carry bit or effectively a 5 bit numberLets construct this adder from gates
Computers carry out addition with binary addition ofbits stored in registers
We can build additions of large numbers of bits out ofunits which add two bits
$3+$4 $3+$C $D+$4 $D+$C
0011 0011 1101 1101
+ 0100 + 1100 + 0100 + 1100
= 0111 = 1111 =10001 =11001
$7 $F $11 $19
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Additions of two bits: The half adder
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A B C S
0 0 0 01 0 0 1
0 1 0 1
1 1 1 0
Adding two bitsgenerates two bits ofoutput
1 Sum Bit S
1 Carry Bit C
The truth table for thisoperation is shown along
with an implementationusing two gates
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Full Adder
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In order to add larger numbers, weneed to be able to bring the carryfrom the lower order bits, and addthis to the sum
The inputs are: the two bits to be added (A,B) The Carry Bit (C)
The outputs are: The Sum Bit (S) The Carry Out Bit (C+)
We can build this from two halfadders and an XOR gate
A B C C+ S
0 0 0 0 0
0 1 0 0 1
1 0 0 0 1
1 1 0 1 00 0 1 0 1
0 1 1 1 0
1 0 1 1 0
1 1 1 1 1
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Two bit adder
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We can construct logicthat adds more than 1 bittogether by usingmultiple full adder
circuits
Exercise:Construct a circuit that adds two two bit words (Ao,A1) and(B0,B1) and produces three Sum Bits (S0,S1,S2)
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Solution
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With the Full adderbuilding block we cangeneralize to produce acircuit which adds larger
numbers
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Four plus Four
bit addition
This can clearly begeneralized to anynumber of bits
There is a problem in
building circuits thisway as the carry bitsneed to propogatethrough the circuitbefore the answer iscorrect
There are other ways toconstruct adder circuitswhich avoid thisproblem
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Arithmetic Logic Unit (ALU)
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Centre of everycomputer
Composed of buildingblocks we have beenlearning about Adders
Flip Flops
Registers
We also need to have a
data bus to move data inand out - we will learnabout this soon