470 ieee transactions on circuits and systems ...b90022/ringosc1.pdf470 ieee transactions on...

470 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 3, MARCH 2011

The Design and Analysis of Dual-Delay-PathRing Oscillators

Zuow-Zun Chen and Tai-Cheng Lee, Member, IEEE

Abstract—A dual-operation-mode ring oscillator that employsdual-delay paths is presented. The two operation modes, referredto as the differential and common modes, have different outputwaveform characteristics and oscillation frequencies. A nonlinearmodel for the dual-delay-path ring oscillator and the analysis ofthe stability of each operation mode are proposed to confirm bothsimulation and measurement results. Furthermore, a method foroperation-mode selection is presented. The differential four-stagedual-delay-path ring oscillator is fabricated in a 0.18- m CMOStechnology. Measurements show that the tuning ranges are from1.77 to 1.92 GHz and from 1.01 to 1.055 GHz for differential- andcommon-mode operations, respectively.Index Terms—Multiphase signals, phase-locked loops (PLLs),

ring oscillators, voltage-control oscillators.

I. INTRODUCTION

R ING OSCILLATORS have been widely employed inmost clock generators and frequency synthesizers for

their small die size, quadrature or multiphase outputs, and easyintegration in standard CMOS technologies. Because the oscil-lation frequency of ring oscillators is mainly determined by thepropagation delay of each delay cell, the maximum frequencyof single-loop ring oscillators is limited by the delay time of thedelay cells. Several techniques have been reported to explorethe maximum frequency levels of ring oscillators [1]–[9]. Thesetopologies are similar in that auxiliary delay paths are used toconstruct fast subfeedback loops. Although ring oscillators withauxiliary delay paths exhibit higher oscillation frequencies, it isfound that they may have more than one stable operation mode.Multiple operation modes in such type of ring oscillators werealso pointed out in [5] and [8]; however, the characteristics ofthe multiple operation modes, such as the number of operationmodes, oscillation frequencies, amplitudes, and phase relationbetween each stage, are limited. Thus, it is risky for a systemto rely on such ring oscillators. For example, in phase-lockedloops (PLLs), the behavior of the voltage-controlled oscillatorshould be well determined; otherwise, the PLLs may fail tolock the input clock.Multiple operation modes of various types of -tank oscil-

lators have been investigated in the past. Two stable operation

Manuscript received January 14, 2010; revised May 12, 2010; accepted July07, 2010. Date of publication November 15, 2010; date of current version Feb-ruary 24, 2011. This work was supported by National Science Council (NSC)under Contract 98-2220-E-002-035- and 98-2622-8-002-001-A1. This paperwas recommended by Associate Editor A. Tasic.The authors are with the Department of Electrical Engineering and the Grad-

uate Institute of Electronics Engineering, National Taiwan University, Taipei106, Taiwan.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCSI.2010.2072390

Fig. 1. Differential four-stage dual-delay-path ring oscillator.

modes were reported for a fourth-order -tank oscillator [10],[11]. The multiple operation modes of coupled -tank oscil-lators were studied in [12] and [13]. It was shown that, becauseof circuit nonlinearity, the operational mode with the greatestgain or the one that is properly initiated sustains, whereas theother modes die off. Recently, the ambiguous multiple operationmodes of quadrature oscillators and injection-locked oscil-lators were interpreted using a hard-limiting nonlinear modeland perturbation method [14], [15].Multiple operation modes of ring oscillators with auxiliary

delay paths are, compared with -tank oscillators, less re-ported. In this work, a differential four-stage dual-delay-pathring oscillator is implemented for its high oscillation frequen-cies, as shown in Fig. 1[6]. Experimental results indicate thatthe ring oscillator has two stable operationmodes.When turningthe power on and off, the oscillator is found operating in eithera mode with the designed oscillation frequency or a mode withalmost half of the designed oscillation frequency. The two op-eration modes are discriminated by their oscillation frequenciesand output waveform characteristics. In contrast to the typicaldifferential outputs of a single delay cell, the outputs are in phasein the other operation mode. Moreover, the output amplitudesof the two modes are different. The main objective of this studyis to resolve the ambiguous dual operation modes in differen-tial four-stage dual-delay-path ring oscillators and provide de-sign strategies for similar types of ring oscillators. To this end,we use a small-signal linear model to predict possible operationmodes of the ring oscillator. Thereafter, the stability of the twomodes is shown by introducing a nonlinear model of the ringoscillator where differential pairs are modeled as hard-limitingtransconductors. The stability of either mode manifests the req-uisite considerations for operation-mode selection. The linearand nonlinear models provide full insight into the fundamentalbehaviors of the dual-operation-mode ring oscillator.The rest of this paper is organized as follows. In Section II, the

two operation modes of a differential four-stage dual-delay-pathring oscillator are predicted in a theoretical small-signal linearanalysis. In Section III, a nonlinear model and perturbation anal-ysis are presented to illustrate the stability of each operation

1549-8328/$26.00 © 2010 IEEE

CHEN AND LEE: DESIGN AND ANALYSIS OF DUAL-DELAY-PATH RING OSCILLATORS 471

mode. The circuit technique for operation-mode selection is pro-posed in Section IV. In Section V, experimental results of adifferential four-stage dual-delay-path ring oscillator are pre-sented. Finally, the paper is concluded in Section VI.

II. SMALL-SIGNAL LINEAR MODELFig. 2 shows the schematic of a delay cell in the ring os-

cillator shown in Fig. 1. Because the long propagation delayin single-loop ring oscillators limits the oscillation frequency,delay cells with an auxiliary delay path is introduced to re-duce the delay time and improve the oscillation frequency [6].Transistors and are the input devices of themain delay signal and the auxiliary delay signal, respectively.

constitutes a CMOS latch whose driving strength iscontrolled by . Specifically, when is high, the ef-fective driving strength of the latch becomes strong and it re-sists the voltage switching in the differential delay cell. Conse-quently, the delay time increases. To illustrate the possible oper-ation modes of the ring oscillator, a simplified model is first pre-sented. Fig. 3(a) and (b) shows the redrawn circuit schematics ofthe ring oscillator in Fig. 1. Each node is denoted with respect toFig. 1. The inverters in Fig. 3(b) represent the equivalent circuitin gate level. and are the simplified loading capacitanceand equivalent resistance at the output node, respectively. Forsimplicity, the transistors used for frequency tuning inFig. 2 are neglected in this model. The simplified model makesthe analysis easier while maintaining the essence of the oscil-lator. According to Fig. 3, the vector differential equation de-scribing the node voltages of the ring oscillator can be writtenas

(1)

where

(2)

(3)

Vectors , , and denote the output currents ofinverter stages , , and , respectively; ,

, and are their output current functions. Itshould be noted that dc components are not included in the

voltage and current expressions of (2) and (3). Since thesefunctions are intrinsically nonlinear, the analysis performed onthe basis of these nonlinear functions is typically complicated.However, a first-order linear function describing small-signalbehavior at the bias point can be derived. For square-lawMOSFET transistors

(4)

and are the corresponding dc current and transcon-ductance of the active devices at the bias point, respectively,where is , , or and is , , , , , , , or. Equation (3) can then be rewritten as

(5)

Substituting (5) into (1), a system of first-order linear equationscan be obtained, , where is an 8 8 matrix definedas shown at the bottom of the page. , , andare the products of , , and with , respec-tively. Fig. 4(a) shows a plot of the eight eigenvalues of matrixon the complex plane. Parameters are evaluated by a SPICE

simulation at the bias point, and is normalized to unity. In thiscase, no auxiliary delay path is involved . Only onepair of eigenvalues lies in the right half plane, and their valuesare

(7)

For this complex pair of eigenvalues, the general solution of (1)can be postulated as

...(8)

(6)


Fig. 2. Circuit implementation of delay cell.

Fig. 3. (a) Simplified model of differential four-stage dual-delay-path ring os-cillator. (b) Circuit of delay stages in (a).

where is a constant. In practice, the gain term is madegreater than zero, so that periodic oscillation with an angularfrequency given by will grow exponentially. As the am-plitude increases, the oscillator departs from linearity and non-linear terms should be considered. The amplitude will be even-tually limited, and the oscillator remains in steady-state oscilla-tion. Fig. 4(b) shows the phase relation of each output node.If the auxiliary path is added, rises from zero and leads

to an increment in the frequency term , as indicated in (7).Thus, a higher oscillation frequency can be attained. However,by increasing , the real part of another pair of eigenvaluestends to increase. This pair is given by

(9)

The general solution of (1) for this pair of eigenvalues is

...(10)

Fig. 4. (a) Eigenvalues of . (b) Phasor diagram of general solution .

where is a constant. When increases, moves tothe right. As exceeds , enters the righthalf plane, as shown in Fig. 5(a). The phase relation of eachoutput node in this case is shown in Fig. 5(b). Now, in additionto the original pair of eigenvalues, another pair is located inthe right half plane. When the oscillator starts up, initially, thesignals and are small and the linearmodel is valid. By thesuperposition principle, the output node signal can be expressedas

(11)

If and are both positive, the amplitudes of the two op-erationmodes increase. Since the other eigenvalues lie in the lefthalf plane, their respective signals lead to decaying exponentialterms and can be ignored. The analysis, thus far, neglects nonlin-earities of the oscillator. This may imply that the ring oscillatorcan oscillate in the two operation modes simultaneously. How-ever, as the amplitude grows up, nonlinearity of the oscillatorcircuit would take place, one of the operation modes dominatesthe ring oscillator and the other dies away. The mechanism thatdrives operation-mode selection will be discussed later.

III. NONLINEAR ANALYSIS OF DUAL-OPERATION-MODE RINGOSCILLATORS

In Section II, a small-signal linear approach was presented forpredicting the two operation modes of a differential four-stagedual-delay-path ring oscillator. In general, the nonlinear cur-rent functions , , and are rather compli-cated. Several attempts characterized by polynomials have beenmade to approximate the functions [10]–[13]. Nevertheless, arather straightforward method is to model differential circuits ashard-limiting transconductors [14], [15], as shown in Fig. 6(a).Suppose that input signals are sufficiently large such that the tailcurrent switches abruptly and the succeeding low-pass stage at-tenuates all high-order harmonics. Thus, for a sinusoidal input


Fig. 5. (a) Eigenvalues of . (b) Phasor diagram of general solution .

voltage, although the hard limiter produces a square-wave cur-rent, only the fundamental of the output current is concerned.The circuit shown in Fig. 6(b) can be expressed by the differen-tial equation

(12)

We assume the input and output voltages are sinusoidalsignals , ,and . The hard limiters are drivenby the sinusoidal voltages and produce square-wave cur-rents with fundamentals of and

, where and denote theequivalent tail currents. By substituting the terms into (12) andseparating the real and imaginary parts, the time-varying phaseand amplitude of the output node are obtained as

(13)

Assume that the oscillator starts up from the bias point andthe dc gains of differential and common modes do not vary with

Fig. 6. (a) Differential pair circuit modeled as hard-limiting transconductors.(b) Operation of hard-limiting transconductors.

time. The amplitude of the signal with larger gain rises faster.In fact, referring to (8) and (10), the signal with larger gainterm value contains an exponential part that grows faster. More-over, although multiple operation modes are possible, since thesignal with larger amplitude drives the clipping characteristicof the hard limiter, the smaller signals will be suppressed [14].In other words, the larger signal dominates the nonlinear circuitand the gain of the lagging operation mode is reduced. The lag-ging operation mode dies off, and the dominating mode reachessteady-state oscillation. In what follows, the stability of the twopossible operation modes of the ring oscillator is analyzed byproperly applying the nonlinear model in each case.

A. Differential-Mode OperationFor the first operation mode derived in (8) and shown in

Fig. 4(b), the output waveforms and are differentiallyphased, as are and , and , and and . Thus,operation in this mode is referred to as differential-mode oper-ation. Considering the differential phase characteristic of thesesignals, the circuit diagram of Fig. 3 is redrawn by substitutingthe differential pairs with the hard-limiting model shown inFig. 6(a). The rearranged diagram is shown in Fig. 7. Theprocess is similar to representing differential pairs with theirhalf-circuit equivalents. By applying (12) and (13) to each stageand as previously defined, equals to half the tail currentof a differential pair. The state equations for the ring oscillatorare obtained as shown at the bottom of the next page. In steadystate, the amplitudes of output signals remain constant and

...

(14)


the derivatives of phases are constants equal to the oscillationfrequency . The steady-state output amplitude andoscillation frequency can be derived from (14) as

(15)

where . Toinvestigate the stability of differential-mode operation, we con-sider the effect of a small disturbance and investigate the prop-erties of (14) in response to this disturbance. Small fluctuationsin the phases at a fixed point are introduced as

(16)

Substituting (16) into (14) and assuming that the amplitudevaries slowly, we obtain the differential equations

(17)where and

(18)

The eigenvalues of the matrix on the right-hand side of (17) are

(19)

Fig. 8 shows that all eigenvalues lie in the left half plane, ex-cept for the eigenvalue at the origin, where is normalized tounity. This proves the stability of differential-mode operation.The zero eigenvalue exhibits the integration property of ring os-cillators with small phase disturbance. As mentioned in [15],this indicates that the free-running oscillator is an autonomousphase integrator.

B. Common-Mode Operation

A similar analysis can be applied to the second operationmode derived in (10). As shown in Fig. 5(b), the output wave-forms and are in phase, as are and , and , and

Fig. 7. (a) Nonlinear model of the ring oscillator operating in differential mode.(b) Circuit of delay stages in (a).

Fig. 8. Locations of eigenvalues.

and . Thus, this operation mode is referred to as common-mode operation, in contrary to the differential-mode operationwhich has differential output characteristics. Additionally,and are differentially phased, as are and . We redrawthe full circuit diagram of Fig. 3 by substituting the differentialpairs with the hard-limiting model in Fig. 6(a). The simplifiedschematic is shown in Fig. 9. Now, applying (12) and (13) toeach stage, we obtain the state equations

(20)

The steady-state output amplitude and oscillation frequency incommon-mode operation are given as

(21)


Fig. 9. Nonlinear model of the ring oscillator operating in common mode.

Fig. 10. Output waveforms. (a) Differential-mode operation. (b) Common-mode operation.

where . Wenow perturb the phases at the fixed point, i.e.,

(22)

Substituting (22) into (20) and assuming that the amplitudevaries slowly results in the following differential equations:

for (23)

The eigenvalues of matrix are 2 and 0, which shows thestability of common-mode operation.Fig. 10(a) and (b) shows the output waveforms of the differ-

ential four-stage dual-delay-path ring oscillator operating in thedifferential and common modes, respectively. As predicted bythe small-signal linear model, the outputs and are differ-entially phased in differential-mode operation and are in phase

in common-mode operation. Moreover, the steady-state ampli-tude and oscillation frequency are different in the two operationmodes, as indicated in (15) and (21).

IV. OPERATION-MODE SELECTION

The proposed nonlinear analysis shows that the ring oscillatorremains stable in each mode. Therefore, it is important to ensurethat the ring oscillator starts up in the mode of interest (typicallythe differential mode). As mentioned previously, when the ringoscillator starts up from its bias point and if dc gains do not varywith time, the signal that grows fastest suppresses the others atthe output [14]. With this property, (7) and (9) can be used fordesign considerations. When the oscillation begins, initially, thetwo signals are small; if is greater than , the differen-tial-mode amplitude grows faster and dominates the nonlinearcircuit. That is

(24)

Ratio value is introduced for expression convenience. Toachieve high-frequency oscillation, is chosen to berelatively small and can be neglected in the mode-selectiondesign consideration. Therefore, (24) becomes

or

(25)

If the oscillation starts from the bias point where(latch device ignored), the constraint to ensure dif-

ferential-mode operation is .However, the rate at which the power supply ramps up from 0 to1.8 V also affects mode selection. It has been found for the delaycell shown in Fig. 2 that, even if the dc differential-mode gainis designed larger than common-mode gain at the bias point,differential-mode gain may be smaller than common-modegain during power-supply ramp-up, as explained below. Duringramping up of the power supply, the ring oscillator has iden-tical output node voltage before the oscillation begins. Thus,the circuit can be considered as diode-connected transistors,as shown in Fig. 11(a). Current flows through the outputloadings and charges . Here, is the sum of drain currents

, , and . Because is greater thanduring ramping up of the power supply, the value

in (25) becomes less than unity for a period of time, whichimplies common-mode gain greater than differential-modegain. Fig. 11(b) shows the value in (25) with respect to timein a SPICE simulation under 1- s power-supply ramp-up rate.As shown, during power-supply ramp-up, is less than unity inregion A, and as the power supply continues to rise, becomeslarger than unity in region B. This causes uncertain steady-stateoperation mode; either differential or common mode sustains.Fig. 12(a) and (b) shows the output waveforms under fast and

slow power-supply ramp-up rate; the ring oscillator operates indifferential and common modes, respectively. The results of a


Fig. 11. (a) Equivalent circuit. (b) Simulated gain ratio.

more elaborated simulation are shown in Fig. 13, where dif-ferent power-supply ramp-up rates and various gain term values

were tested by sweeping the multiplier number of aux-iliary devices. Simulation shows that, after power supply set-tles down, the ring oscillator operates in either differential orcommon mode. Neither simultaneous oscillation of differentialand common mode nor other operation modes have been ob-served. Furthermore, as indicated in the figure, larger andlonger power-supply ramp-up time, which causes longer pe-riod of time for greater than (region A), gives thecommon-mode amplitude more time to build up and dominatethe nonlinear circuit. In contrast, shorter power-supply ramp-uptime and smaller drives the steady-state operation of thering oscillator to differential mode. Therefore, for mode selec-tion, the gain ratio during power-supply ramp-up needs to beconsidered as well. should be designed greater thanthroughout the entire ramp-up process. However, this gives riseto design tradeoffs between high-frequency oscillation and gainvalues [8]. For example, designing the dual-delay-path ring os-cillator with weaker auxiliary devices or stronger latch devicesdecreases common-mode gain, but also reduces the oscillationfrequency of differential mode.To eliminate the dependence of gain ratio with respect

to power-supply ramp-up rate, which causes ambiguoussteady-state operation, and to ensure differential-mode (orcommon-mode) operation, a startup circuit is presented, asshown in Fig. 14(a). The circuit is composed of eight identicalsubblocks, and the output of each subblock is connected toone of the output nodes of the ring oscillator. The startupcircuit charges the output nodes to a predefined initial valueat circuit startup. The operation is shown in Fig. 14(a). Whencontrol signal is high, the output nodes are charged toan initial condition value. Moreover, when becomes low,the oscillator starts to operate autonomously. sets the

Fig. 12. Operation-mode simulation. (a) Fast power-supply ramp-up. (b) Slowpower-supply ramp-up.

Fig. 13. Operation-mode simulation of different multiplier numbers of auxil-iary devices and different rates of power-supply ramp-up from 0 to 1.8 V.

initial condition value. The startup circuit was tested throughsimulations under various gain term values by sweepingthe multiplier number of auxiliary devices. Fig. 14(b) showsthe simulation results. Since the startup circuit is employed,the power-supply ramp-up rate does not need to be considered.The black line shows the case that output nodes are prechargedto ensure differential-mode operation; the gray line shows thecase of output nodes precharged to ensure common-mode oper-ation. Simulation results show that the startup circuit correctlycontrols the oscillator to operate in either mode. In Fig. 14(b)and as derived in (15) and (21), a larger increasesthe oscillation frequency of differential mode and decreasesthe oscillation frequency of common mode. The limitation ofthe differential-mode oscillation frequency is caused by theincrease in parasitic capacitance as the multiplier number of


Fig. 14. (a) Startup circuit. (b) Simulated oscillation frequency of ring oscil-lator with startup circuit employed.

Fig. 15. (a) Microphotograph of the dual-delay-path ring oscillator. (b) Mea-surement setup.

becomes large and eventually cancels out the drivingstrength of the increment and reduces the frequency.

V. EXPERIMENTAL RESULTSA differential four-stage dual-delay-path ring oscillator

was designed and fabricated in 0.18- m CMOS technology.Fig. 15(a) shows the microphotograph of the fabricated circuit.To achieve high-frequency oscillation in differential mode,the auxiliary devices are designed to be stronger andlatch devices designed to be weaker. The two operation

Fig. 16. Measured output waveform. (a) Output waveform. (b) Zoom in.

Fig. 17. Output spectrum and frequency range of the ring oscillator. (a) Differ-ential mode. (b) Common mode.

modes are experimentally demonstrated. It should be notedthat the fabricated dual-delay-path ring oscillator contains nostartup circuit, because the dual-mode operation was foundduring the experiment rather than in the design and simulationstage. To specify either operation mode for measurement, adifferent ramp-up rate of the power supply is applied to startup oscillation, as already verified by the SPICE simulationsshown in Figs. 12 and 13. The measurement setup is shown inFig. 15(b). To control the power startup, an arbitrary waveformgenerator (Tektronix AWG520) is used to supply voltage to thering oscillator. A sequential power-supply signal with a slowramp-up slope followed by a steep ramp-up slope is applied to


TABLE ISUMMARY OF EXPERIMENTAL RESULTS

the ring oscillator, as shown in the lower portion of Fig. 15(b).The output waveforms measured using an oscilloscope (AgilentDSO80404B) are shown in Fig. 16. In Fig. 16(b), the oscillationfrequency with the slow ramp-up of the power supply is abouthalf of that with the fast ramp-up, indicating the operation ofthe ring oscillator in the differential and common mode, respec-tively. This is in agreement with postsimulation results. Theoutput tuning characteristics were measured using a spectrumanalyzer (Agilent E4404B). The supply voltage was set to 1.8 Vafter properly starting up the ring oscillator. Fig. 17(a) and (b)shows the output spectrum and frequency range of the ringoscillator operating in the differential and common modes,respectively. Table I summarizes the experimental results.

VI. CONCLUSIONRing oscillators with auxiliary delay paths are often em-

ployed for obtaining higher oscillation frequencies in ringoscillators. However, multiple operation modes are foundin such type of ring oscillators. A differential four-stagedual-delay-path ring oscillator that generates dual-operationmode has been presented. The main difference between the twooperation modes is the output waveform characteristic. Insteadof typical differential outputs in a single delay cell, the outputsare in phase in the other mode. Moreover, the amplitude andoscillation frequency of the two modes differ. In this paper, asmall-signal linear model has been proposed for predicting thetwo operation modes of differential four-stage dual-delay-pathring oscillators. In nonlinear model analysis, the two opera-tion modes are shown to provide steady-state oscillation. Theanalysis based on linear and nonlinear models shows the fun-damental behaviors of the two operation modes and providesdesign guidelines for dual-delay-path ring oscillators. Properinitialization of the oscillator is required. A startup circuit hasbeen proposed to control the operation modes.

REFERENCES[1] D. Y. Jeong, S. H. Chai, W. C. Song, and G. H. Cho, “CMOS current-

controlled oscillators using multiple-feedback-loop architectures,” inProc. IEEE ISSCC Dig. Tech. Papers, Feb. 1997, pp. 386–387.

[2] S. J. Lee, B. Kim, and K. Lee, “A novel high-speed ring oscillatorfor multiphase clock generation using negative skewed delay scheme,”IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 289–291, Feb. 1997.

[3] C. H. Park and B. Kim, “A low-noise, 900-MHz VCO in 0.6- mCMOS,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 586–591, May1999.

[4] L. Sun, T. Kwasniewski, and K. Iniewski, “A quadrature output voltagecontrolled ring oscillator based on three-stage subfeedback loops,” inProc. IEEE ISCAS, Jul. 1999, vol. 2, pp. 176–179.

[5] L. Sun and T. A. Kwasniewski, “A 1.25-GHz 0.35- m monolithicCMOS PLL based on a multiphase ring oscillator,” IEEE J. Solid-StateCircuits, vol. 36, no. 6, pp. 910–916, Jun. 2001.

[6] Y. A. Eken and J. P. Uyemura, “A 5.9-GHz voltage-controlled ringoscillator in 0.18- m CMOS,” IEEE J. Solid-State Circuits, vol. 39,no. 1, pp. 230–333, Jan. 2004.

[7] Y. A. Eken and J. P. Uyemura, “The design of a 14 GHz I/Q ring os-cillator in 0.18 m CMOS,” in Proc. IEEE ISCAS, May 2004, vol. 4,pp. 133–136.

[8] S. S. Mohan, W. S. Chan, D. M. Colleran, S. F. Greenwood, J. E.Gamble, and I. G. Kouznetsov, “Differential ring oscillators with mul-tipath delay stages,” in Proc. IEEE CICC, Sep. 2005, pp. 503–506.

[9] C.-Y. Yang, C.-H. Chang, and W.-G. Wong, “A PLL-basedspread-spectrum clock generator with a ditherless fractional topology,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 1, pp. 51–59,Jan. 2009.

[10] B. van der Pol, “On oscillation hysteresis in a triode generator with twodegrees of freedom,” Philos. Mag., vol. 43, no. 256, pp. 700–719, Apr.1922.

[11] A. Goel and H. Hashemi, “Frequency switching in dual-resonance os-cillators,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 571–582,Mar. 2007.

[12] T. Endo and S.Mori, “Mode analysis of a multimode ladder oscillator,”IEEE Trans. Circuits Syst., vol. CAS-23, no. 2, pp. 100–113, Feb. 1976.

[13] T. Endo and S. Mori, “Mode analysis of a ring of a large number ofmutually coupled van der pol oscillators,” IEEE Trans. Circuits Syst.,vol. CAS-25, no. 1, pp. 7–18, Jan. 1976.

[14] A. Mirzaei, M. E. Heidari, R. Bagheri, S. Chehrazi, and A. A. Abidi,“The quadrature LC oscillator: A complete portrait based on injectionlocking,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1916–1932,Sep. 2007.

[15] A. Mirzaei, M. E. Heidari, R. Bagheri, and A. A. Abidi, “Multi-phaseinjection widens lock range of ring-oscillator-based frequency di-viders,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 656–671, Mar.2008.

Zuow-Zun Chen was born in Taipei, Taiwan, in1982. He received the B.S. degree in computerscience and information engineering and the M.S.degree in electrical engineering from NationalTaiwan University, Taipei, in 2005 and 2008, respec-tively.He is currently with the Graduate Institute of

Electronics Engineering, National Taiwan Univer-sity. His research interests are analog phase-lockedloops, frequency synthesizers, ring oscillators, andmixed-mode circuits.

Tai-Cheng Lee was born in Taiwan in 1970. He re-ceived the B.S. degree in electrical engineering fromNational Taiwan University, Taipei, Taiwan, in 1992,the M.S. degree in electrical engineering from Stan-ford University, Stanford, CA, in 1994, and the Ph.D.degree in electrical engineering from the Universityof California, Los Angeles, in 2001.He was with LSI Logic from 1994 to 1997 as a

Circuit Design Engineer. He was an Adjunct Assis-tant Professor with the Graduate Institute of Elec-tronics Engineering (GIEE), National Taiwan Uni-

versity, from 2001 to 2002. Since 2002, he has been with the Department ofElectrical Engineering and GIEE, National Taiwan University, where he is aProfessor. His main research interests are in high-speedmixed-signal and analogcircuit design, data converters, phase-locked-loop systems, and RF circuits.

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