4.8 - moisture sensitivity update · 4.8 moisture sensitivity update j-std-020/033/075 p.2. jedec /...

4.8 Moisture Sensitivity Update J-STD-020/033/075 P.1

JEDEC / JEITA Joint Meeting #14 in Vancouver September 2010

4.8 -

Moisture Sensitivity Update

Steve Martell (Sonoscan)



OutlineOutline

• J-STD-020D – Published August 2007 – Typos corrected 3/08 (Rev D.1)

• J-STD-075 – Published August 2008

• J-STD-033C – Balloted within JEDEC & IPC– Publish 2010 or early 2011

• Future Topics to be Considered



J-STD-020D.1J-STD-020D.1



J-STD-075J-STD-075



J-STD-075 MSL & PSLJ-STD-075 MSL & PSL



Process Sensitivity Level (PSL)Process Sensitivity Level (PSL)



Other Process Limitations (PSL)Other Process Limitations (PSL)



Labeling & Packing



J-STD-033C BallotedJ-STD-033C Balloted

• JEDEC and IPC Balloting in process– JEDEC balloting closed 9/8/10– IPC balloting will close on 9/23/10

• JEDEC reviewed comments this week• Next joint JEDEC/IPC meeting currently

scheduled for January– Plan for teleconference meeting between now

and January to review/resolve all comments



J-STD-033C Balloted Summary of Changes

J-STD-033C Balloted Summary of Changes

Reference J-STD-033B.1 J-STD-033C Forward, Purpose, Scope Forward, Purpose, Scope Expanded Scope 1.3 Assembly Processes Added 1.3.5 Aqueous Cleaning

2.2 2.2 Added Reference J-STD-075 3.3.2.2.1 3.3.2.2 Changed desiccant calculation

Removed formula U = 5 X 10-3 A 3.3.2.2.2 Added 3.3.2.2.2 Desiccant Handling and

Storage Figure 3-2 Figure 3-2 Modified HIC Figure

3.3.2.3 3.3.2.3 Wording additions/changes 3.3.3.1 3.3.3.1 Wording additions/changes

Figure 3-4 Figure 3-4 New Caution Label 3.3.4 3.3.4 Modified wording – see 3.3.5.3 3.3.5 Added Dry Pack Precautions

3.3.5.3 3.3.4 “Moisture Barrier Bag Sealing” - Modified wording – see 3.4

MBB Figures Added Figures 3-5, 3-6, 3-7



J-STD-033C Balloted Summary of Changes (cont’d)

J-STD-033C Balloted Summary of Changes (cont’d)

3.3.6 3.3.5 Added sentence 4 4 Added Note

Table 4-1, 4-2 Table 4-1, 4-2 Added temp tolerance Table 4-1 Table 4-1 Added sentence to Note 1

4.1.2 4.1.2 Removed last sentence 4.2.7.1 4.2.7.1 Changed “shall” to “should”

5 5 Changed wording 5.1.1 5.1.1 Added wording 5.3.2 5.3.2 Modified 2nd sentence and changed Note 6.2 6.2 Added Note

Editorial Changes throughout

Reference J-STD-033B.1 J-STD-033C



J-STD-033C Balloted Purpose & Scope

J-STD-033C Balloted Purpose & Scope



J-STD-033C Balloted Aqueous Cleaning & J-STD-075

J-STD-033C Balloted Aqueous Cleaning & J-STD-075

Definitions

References



J-STD-033C Balloted Desiccant Quantity Calculation

J-STD-033C Balloted Desiccant Quantity Calculation



J-STD-033C Balloted Desiccant Handling & Storage

J-STD-033C Balloted Desiccant Handling & Storage



J-STD-033C Balloted HIC

J-STD-033C Balloted HIC



J-STD-033C Balloted Dry Pack Precautions

J-STD-033C Balloted Dry Pack Precautions



J-STD-033C Balloted Drying & Bake Interruption




J-STD-033C Balloted Table 4-3 (Reset/Pause Floor Life)

J-STD-033C Balloted Table 4-3 (Reset/Pause Floor Life)



J-STD-033C Balloted Short Duration Exposure

J-STD-033C Balloted Short Duration Exposure



J-STD-033C Balloted Shelf Life

J-STD-033C Balloted Shelf Life



J-STD-033C Balloted Appendix A: TM for HICs

J-STD-033C Balloted Appendix A: TM for HICs



Future Topics for 033

For passive devices, appendices for bake drying times would be added. Coordinate with J-STD-075 Feedback from ECA

Pending Issue Status Task

The existing derating table in Section 7.1 does not apply to flip chip. Adding something stating that the document only covers wire bond packages was proposed. It was decided that this will wait until the next revision. Some material was presented by IBM on the floor time derating tables that they have measured. Agere then showed the existing table 7.1 and noted that the thickness makes all the difference—it is a critical number. The thinner you make it the shorter the time. Knowing the distance from the outside area of the chip to the first bump would help to revise the calculations. IBM agreed to make a few more soak evaluations to get some more data. A task group was created to work on flip chip derating. Bill Guthrie will lead it, and its members were Shook, Newman, McCullen and Susko. (Xuejun Fan (Intel) papers on this subject)

How to derate Flip Chip, Stacked Die and other types of packages and definitions of the various package types. Bring examples to show others the construction. (SRM to contact Robin, Keith & cc Jack)

JEDEC TG on Flip Chip (Ash)

Evaluate derating tables for substrate based packages. See above JEDEC TG on Flip Chip (Ash)

Alternative bakeout temperature between 40 and 90 C for faster bake times General request Jan 2009 60 to 70C proposalLook into adding ~70C (60 to 70C) bakeout condition to table with < 1% RH environment in the oven. Concern about 72C adhesive wetting issue for tape & reel carriers. Perhaps an alternative bakeout procedure for tape & reel or other low temperture carriers.

Discussed @ APEX 2009 IDC Data

Add/transfer packaging and labeling requirements from J-STD-075 Discussed at Sept 2010 JEDEC Meeting

Add to Rev 033D



Future Topics for 020Future Topics for 020Pending Issue Status TaskFlip Chip and CSP Failure Criteria & Soak Requirements OpenStacked Die Failure Criteria & Soak Requirements OpenHeat Spreader Failure Criteria & Soak Requirements OpenAdd Modules, Advanced Packages, SIP and/or SOC? (Different Classification Temperatures needed?)

Open (Elivra @ Qualcom presentation at June 2008 meeting)

Section 4.1 on rework temperature tolerances Discussed @ APEX 2007General Dynamics created an interposer concept so that you solder to copper instead of SAC board finish. It gives you to better planarity BGA than before. It was noted General Dynamics has a patent on this. This will be discussed at an iNEMI meeting on March 1, 2007. From a reliability standpoint, voids need to be addressed for this concept. (Module application?)

Discussed @ APEX 2007

Infineon showed some measurement results on warpage in high temperatures. Their conclusion was warpage measured at solidus temperature of the solder overestimates the effect and risk of solder joint formation. The Committee felt this information related to B-112, not J-STD-020.

Will be covered by B-112

In Table 5-1, accelerated equivalent was discussed. Which of the .4 or .48 eV should be used? The Committee felt this should be investigated for the next revision.

Discussed @ Jan 2007 (Intel used 0.4 for calulation to be conservative)

It was pointed out that there are notes before table 4-1 and after it. This is something that should be cleaned up in the future.

Discussed @ Sept 2006

Putting references to technical papers in J-STD-020 was discussed. The style manual does not allow references in standards. It was suggested to put these on JEDEC or IPC web sites, but getting the user to find these is the problem. In some cases the data is proprietary and this is not published. But when the data is published then it can be available. Data that was in minutes of meetings is also valuable but is not available unless you are a member. (Wikipedia listing for some data or list of references?)


Northrop noted that solder dipping parts to the body edge has been taking place in industry in high-rel applications. By doing this, there is a risk of damage to the part due to temperature shock. It was noted that solder dipping does not always mitigate tin whiskers. (Should not be a part of J-STD-020)

Covered by G12 standard - GEIA-STD-0006: Requirements for Using Solder Dip to Replace the Finish on Electronic Piece Parts



Future Topics for 020 cont’dFuture Topics for 020 cont’dpackages though. (Should not be a part of J STD 020)Temperature & Moisture sensitivity of PCBs, concerns about warpage, packaging and labeling (Alternative IPC working group D-35 (Group leader - Kemp), meeting @ Apex 2008 on Tuesday morning) (IPC-PE740 & HDBK 001 references)

No for J-STD-020, but IPC documents could reference J-STD-020/033 for certain procedures

Switch procedure for inspection (AM before Optical inspection) Discussed @ June 2007Socket mounted components to be included? Plus, Sockets themselves? (Add clause about removing socketed devices w/o MSL qualification should be removed before rework should be added to rework section)

Sockets covered by J-STD-075. SMD/socketed ICs are covered by J-STD-020 as any other component, if ICs are intended only for socket applications do not need MSL. Is this covered by current J-STD-020?

Review all notes for movement into body of document to make binding Discussed @ January 2008The document rev D 01 had been published on March 11, 2008. Qualcomm pointed outthat there was an error in this version in Table 5-2 for tp is wrong and needs to refer to time, not temperature.

Discussed @ June 2008 (Fixed already, but reconfirm) Need to modify *

on table 5-2The Committee did agree that some clarification was needed in J-STD-020. Note 3 in section 4 may not be clear enough. Use of alternative classification temperatures. Need to reference Tc versus Tables 4-1 & 4-2 throughout the document

Discussed @ June 2008

How to handle "interuptions" of the bake or conditioning of parts (Limits on time ovens or chambers are open or if interupted for other reasons) (15 minutes max or start over, HAST interupt procedure?)

E-mail inquiry Sept 2008

Concern about oxidation formation that could cause electrical testing issues with repeated baking of the package.

E-mail inquiry Nov 2008 Section 5.8 add sentence about oxidation concerns

Meaning of "Dry" package for dry bake times Discussed @ January 2009Reference J-STD-075 Discussed @ January 2009 Paul K.Revised scope to cover "temperature related stress only", also Discussed @ January 2009Bare Die for Reflow conditions only (Polymer ILDs) Discussed @ APEX 2009



Future Topics for 075Pending Issue Status TaskSome passive parts can not withstand the temperatures of J-STD-020 aside from the moisture levels. Aluminum capacitors have the greatest thermal limitations—both time and dwell. A maximum temperature of 240 degrees C and a short time duration of 10 sec or less for some. Polymer capacitors are next down the list in terms of limitations. The problem is that you can’t test the failures at the end of the line. The failures do not show up until 3-4 years later. In consumer electronics area, this may be within the acceptable lifetime—however, in other areas of electronic uses it may not.


The first step is to document the design limitations and then the designers will know what they can design into their part libraries. This has not been an issue with leaded designs. A label issue arises out of this. A simple warning label may be a solution, but there are five items that may be needed to be included—not just one. How you get the word out that there are issues with some devices was the idea. Using just two items: MSL and TSL might be enough.


The idea for passives is that appendices to J-STD-020 would be created with criteriaincluded.

Plan to keep J-STD-020 for SMD IC criteria only. Add criteria for passives to J-STD-075 eventually.

Do passive devices need to be put in MBBs? Covered by J-STD-075, that referes to J-STD-033 for labeling and packing.

Clause 9 prescribe 6 reflows instead of 3 reflows. Committee noted 6 reflows is not in use for components in industry today, only for unpopulated PCBs. The industry standard is maximum of 3 for components. TM 2.6.27 was referenced in the comment, but Committee noted this method was not for components, but for unpopulated PCBs.

Discussed @ Apex 2008

Clause 10, add sentence to end of para. “see IPC 7711 for guidance on rework.” Committee disagreed. This document is not for rework. It could be added at a later time, but is out of the scope of the existing document. This will be considered in a future revision.




Clause 11, 3rd bullet, corrosive flux, (ph 1-2) change to (M and H per J-STD-004). Committee agreed to remove (ph 1-2). Reference to J-STD-004 was left in. Committee wanted to consider this for the next revision, because it was a technical change and will require further review. Committee agreed in concept.


Add a new section to address selective soldering. Committee noted this will be considered for the next revision.


How to test and notify about "washing limitations" to meet 075 E-mail inquiry Dec 2008Request for alternative bakeout temperatures in addition to 125C due to temperature limits of component carriers (i.e. Tape & Reel, etc.)

E-mail inquiry Jan 2009

Consider Outstanding Technical Comments for Next Revision:Rework ProcessesFlux references to J-STD-004Inclusion of PTH “Selective Soldering” ProcessesClassification Simplification (fewer buckets?)Review Editorial Statement as to a “Reasonable” Process (Table 11-1, Note 1)Expand on Connector Commodity Information / ParticipationAdditional Commodities

Discussed @ January 2009

Paul K.

Future Topics for 075

Add failure criteria with input from ECA Curt mentioned at Sept 2010 JEDEC meeting

Paul K.

Transfer packaging and labeling requirements to J-STD-033D Curt mentioned at Sept 2010 JEDEC meeting

Paul K.



SummarySummary

• J-STDs 020D.1 & 075– looking at potential future changes

• J-STD-033C– Balloting within JEDEC & IPC– 2010 or early 2011 publication

• Future Considerations– J-STD-033– J-STD-020– J-STD-075

4.8 - moisture sensitivity update · 4.8 moisture sensitivity update j-std-020/033/075 p.2. jedec /...

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