OBJECTIVE:

Riddhi Sunitkumar Shah12B Gardner Ave., Lowell, MA 01854 | 781-266-7934 | shahriddhi65@yahoo.in

Seeking a Summer Internship in Computer Engineering in the area of Digital IC/ASIC chip Design and Verification

TECHNICAL SKILLS: VLSI designing tools: Cadence Virtuoso(Simulator Spectre), ModelSim Programming languages: C, C++, Perl, Verilog/VHDL( simulating, debugging, testing) Simulation tools: MATLAB, Visual Basic, PROTEUS ISIS Professional 7.0, Multisim Microprocessor languages: MPLAB, PCB Designing Windows Applications: MS PowerPoint, MS Excel, MS Word

EDUCAT I O N :Master of Science: Computer Engineering (VLSI Domain) May 2016University of Massachusetts-Lowell, MAOverall GPA: 3.2/4.0

Bachelor of Engineering: Electronics and Communication June 2013Gujarat Technological University, Ahmedabad, IndiaOverall GPA: 3.8/4.0

SELECTED RELEVANTACADE M I C P R O J ECT S : Synthesis and Simulation Techniques for FIFO Design, March – May 2015:

Technique: Asynchronous comparison of FIFO read and write pointers using Gray counters that take advantage of built-in binary ripple carry.

To implement high speed asynchronous FIFO and to analyze for static timing verification..

Design Verification and DFT for an embedded reconfigurable Flash ADC and Low power Vedic Multiplier in system-on-chip Applications, March - May 2015:

Designed to greatly reduce the size of the required test bench with reduction in the time and power consumption.

Test and verify the circuit using the BIST technique to get accurate output with minimum delay in power.

4 bit Arithmetic Logic Unit, Jan. 2015: Analyzed the results of simulation of Arithmetic Logic Unit using ModelSim

4bx4b SRAM with row and column decoder, April 2015: Designed SRAM using multi-divided data line and multi-divided word line technique, to operate

between the active mode and the data retention mode for power savings purpose. Results shows that data retention voltage is estimated by minimizing the standard leakage power and

verified from the graphs, this saves power by making the SRAM cells sleep instead of high voltage cells.

3 bit TIQ Flash ADC, Nov - Dec. 2014: To reduce the complexity of circuit and consumption of power using TIQ technique. This replaced

comparator with inverter and used the ROM type encoder for selecting the output from generator. 25% less power consumed. The challenges were reducing offset error, gain error to negligible.

Monitoring and Controlling of Greenhouse Technology with GSM modem, Dec.2012 - June 2013: Used PIC 16LF877A connecting with sensors, to get its temperature, light, water and soil information

coded using MPLAB and simulated circuit by PROTEUS. Except for predefined values parameters can be changed manually with keypad continuously. The

purpose to this project was to bring awareness of how hazardous open field farming in comparison to automatic governed Greenhouse Technology.

EX P ER IE NC E :Telecom Intern (Bharat Sanchar Nigam ltd. Technologies, Ahemadabad, India May – August 2013:

Performed a study on implementation of drive test for development of GSM Network. Collected dataset which includes signal intensity, signal quality, interference, dropped calls and

blocked calls, service level statistics neighboring cell information. Analyzed data represented a true picture of network conditions and can be used for decision making

in several areas such as Coverage and Capacity in the network.