Microprocessor and InterfacesMicroprocessorandInterfaces

MinimumMode

Minimum Mode InterfaceMinimumModeInterface

Whenthe Minimummodeoperationisselected,e t e u ode ope at o s se ected,the8086providesallcontrolsignalsneededto implementthememoryandI/Ointerface

Theminimum mode signal canbedivided into thefollowingbasicgroups

/ Address/Databus StatusControl Control

Interrupt DMADMA

Address/Data BusAddress/DataBus theselinesservetwofunctions.As anaddressbusis20bits

longandconsistsofsignallinesA0throughA19.A19representstheMSBandA0LSB.A20bitaddressgivesthe8086a1Mbytememoryaddressspace.Moreoverithas

i d d t I/O dd hi h i 64K b t ian independentI/Oaddressspacewhichis64Kbytesinlength

The 16 data bus lines D0throughD15areactuallylti l d ith dd li A0 th h A15 ti lmultiplexedwithaddresslinesA0throughA15respectively.

Bymultiplexedwemeanthatthebusworkasanaddressbusduringfirstmachinecycleandasadata busduringnextmachine cycles D15 is the MSB and D0 LSBmachinecycles.D15istheMSBandD0LSB

Whenactingasadatabus,theycarryread/writedataformemory,input/outputdataforI/O devices,andinterrupttype codes from an interrupt controllertypecodesfroman interruptcontroller

Status signalStatussignal ThefourmostsignificantaddresslinesA19throughA16arealsomultiplexedbutinthiscasewithstatussignalsS6throughS3.Thesestatusbitsareoutputonthebusatthesametime thatdataaretransferredovertheotherbuslines

Bit S4andS3togetherfroma2bitbinarycodethatidentifies which of the 8086 internal segment registersidentifieswhichofthe8086internalsegmentregistersareusedtogeneratethephysicaladdressthatwasoutputontheaddressbusduringthecurrentbuscycle

Code S4S3 = 00 identifies a register known as Code S4S3=00identifiesaregisterknownasextra segmentregisterasthesourceofthesegmentaddress

Status signalStatussignalS4 S3 Segment

Register0 0 Extra

0 1 Stack

1 0 Code

1 1 Data

Status line S5reflectsthestatusofanotherinternalcharacteristicofthe8086.Itisthelogiclevel oftheinternalenableflag.ThelaststatusbitS6isalwaysatthelogic0levely g

Control SignalsControlSignals

The control signals are provided to supportThecontrolsignalsareprovidedtosupportthe8086memoryI/O interfaces.Theycontrolfunctions such as when the bus is to carry afunctionssuchaswhenthebusistocarryavalidaddressinwhichdirectiondataaretobetransferred over the bus when valid writetransferredoverthebus,whenvalidwritedataareonthe busandwhentoputreaddataon the system busonthesystembus

Control SignalsControlSignals ALEisa pulseto logic1thatsignalsexternalcircuitrywhen

avalidaddresswordis onthebus.Thisaddressmustbelatchedinexternalcircuitryonthe1to0edgeofthepulseatALE

AnothercontrolsignalthatisproducedduringthebuscycleisBHE_bar bankhighenable.Logic0 onthisusedasamemoryenablesignalforthemostsignificantbytehalff th d t b D8 th h D1 Th li lof thedatabusD8throughD1.Theselinesalsoservesa

secondfunction,whichisastheS7statusline UsingtheM/IO_bar andDT/R_bar lines,the 8086 signals

hi h t f b l i i d i hi h di tiwhichtypeofbuscycleisin progressandinwhichdirectiondataaretobetransferredoverthebus

Control SignalsControlSignals The logic level of M/IO_bar tellsexternalcircuitry whetheramemoryorI/Otransferistakingplaceover thebus.Logic1atthisoutputsignalsa memoryoperationandlogic0anI/Ooperationy p g p

The direction of datatransferoverthebusissignaledbythelogicleveloutputatDT/R_bar.Whenthislineis logic 1 during the data transfer part of a bus cycle,is logic1duringthedatatransferpartofabus cycle,thebusisin thetransmitmode.Therefore,dataareeitherwrittenintomemoryoroutputtoanI/Odevice

On the other hand logic 0 at DT/R bar signals that the Onthe otherhand,logic0atDT/R_bar signalsthatthebusisinthereceivemode.This correspondstoreadingdatafrommemoryorinputofdatafromaninputport.

Control SignalsControlSignals ThesignalreadRD_bar andwriteWR_bar indicatesthatareadbuscycleorawritebus cycleisinprogress.The8086switchesWR_bar tologic0to signalexternaldevicethatvalidwriteoroutputdataareonthebusp

On theother hand,RD_bar indicates that the8086isperformingareadofdataofthe bus.Duringreadoperations, one other control signal is also supplied.operations,oneothercontrolsignalisalsosupplied.ThisisDEN_bar (data enable) andit signalsexternaldeviceswhentheyshouldputdataonthebus

There is one other control signal that is involved There is one other controlsignal thatisinvolvedwith thememoryandI/Ointerface.Thisisthe READYsignal

Control SignalsControlSignals

READY signal is used to insert wait states intoREADYsignalis used toinsertwaitstatesintothe buscyclesuchthatitis extendedbyanumber of clock periods This signalnumberofclockperiods.Thissignalis providedbyanexternalclockgeneratordevice and can be supplied by the memory ordeviceandcanbesuppliedbythememoryorI/Osubsystemtosignalthe8086whentheyare ready to permit the data transfer to bearereadyto permitthedatatransferto becompleted

Interrupt signalsInterruptsignals Thekeyinterruptinterfacesignalsareinterrupty p g prequest(INTR)andinterruptacknowledge(INTA_bar)

INTR is an input to the 8086 that can be used by INTR is an inputtothe 8086 that canbeusedbyanexternaldevicetosignalthatitneedtobeserviced

Logic1atINTRrepresentsanactiveinterruptrequest.Whenaninterruptrequesthas beenrecognized by the8086 it indicates this fact torecognizedbythe8086,itindicatesthisfacttoexternalcircuitwithpulsetologic0attheINTA_bar output

Interrupt signalsInterruptsignals

The TEST bar input is also related to the externalTheTEST_bar inputisalsorelatedtotheexternalinterruptinterface.ExecutionofaWAIT instructioncausesthe8086tocheckthelogiclevelattheTEST_bar input

If the logic 1 is found, the MPU suspendIfthe logic1isfound,the MPUsuspendoperation andgoesintotheidlestate.The8086no longerexecutesinstructions,insteaditgrepeatedlychecksthelogiclevelof theTEST_barinputwaitingforits transitionbacktologic0

Interrupt signalsInterruptsignals AsTEST_bar switchesto0,executionresumewiththenextinstructionintheprogram.Thisfeaturecanbeusedtosynchronizetheoperationofthe8086toaneventinexternalhardware

Therearetwomoreinputsintheinterruptinterface:thenonmaskable interruptNMIandtheresetinterruptRESETRESET

Onthe 0to1 transition ofNMIcontrolispassedto anonmaskable interruptserviceroutine.TheRESETinput is used to provide a hardware reset for the 8086inputisusedtoprovideahardwareresetforthe8086.SwitchingRESETtologic0initializesthe internalregisterofthe8086andinitiatesaresetserviceroutine

DMA Interface signalsDMAInterfacesignals

ThedirectmemoryaccessDMAinterfaceofthe8086yminimummodeconsistoftheHOLDandHLDAsignals

When an external device wantsto take controlofthet b it i l t th 8086 b it hi HOLD tsystembus,itsignalstothe8086byswitchingHOLDto

thelogic1level.At thecompletionofthecurrentbuscycle,the8086enterstheholdstate.In theholdstate,ysignallinesAD0throughAD15,A16/S3throughA19/S6,BHE_bar,M/IO_bar,DT/R_bar,RD_bar,WR_bar,DEN bar and INTR are all in the high Z state The 8086DEN_bar andINTRareallin thehighZstate.The8086signalsexternaldevicethatitis inthisstatebyswitchingits HLDAoutputtologic1level

MINIMUMMODE OPERATIONMINIMUMMODEOPERATION

Minimum Mode 8086 SystemMinimumMode8086System

Ina minimummode 8086 system,they ,microprocessor8086isoperatedinminimummodebystrappingitsMN/MX_bar pintologic1I thi d ll th t l i l i t b th Inthismode,allthecontrolsignalsaregivenoutbythemicroprocessorchipitself.Thereisasinglemicroprocessorintheminimummodesystemp y

Theremainingcomponentsinthesystemarelatches,transreceivers,clockgenerator,memoryandI/Odevices Some type of chip selection logic may bedevices.SometypeofchipselectionlogicmayberequiredforselectingmemoryorI/O devices,dependingupontheaddressmapofthesystem

Minimum Mode 8086 SystemMinimumMode8086System

Latchesare generally buffered output Dtypeflipg y p yp pflops like74LS373or8282.Theyareusedforseparatingthevalidaddressfromthemultiplexedaddress/datasignals and are controlled by the ALE signal generatedsignalsand arecontrolledbytheALEsignalgeneratedby8086

Transreceivers are the bidirectional buffersand sometimestheyarecalledasdataamplifiers.Theyarerequiredtoseparatethevaliddatafrom thetimemultiplexed address/data signalsmultiplexedaddress/datasignals

They arecontrolledbytwo signalsnamely, DEN_barandDT/R_bar

Minimum Mode 8086 SystemMinimumMode8086System The DEN bar signal indicates the direction of dat_ ga, i.e.from ortotheprocessor.Thesystemcontainsmemoryforthemonitorandusersprogram storageprogramstorage

Usually,EPROM areusedformonitorstorage,whileRAMforusersprogramstorage.Asystemmay containI/Odevices

The clock generator generates the clock fromthecrystal oscillator and then shapes it and divides tocrystaloscillatorandthenshapesitanddividestomakeitmoreprecisesothatitcanbeusedas anaccuratetimingreferenceforthesystem

ReadCycleTimingDiagramf dfor MinimumMode

Hold Response sequenceHoldResponsesequence

TheHOLDpinischeckedatleadingedgeofeachclockp g gpulse.Ifitis receivedactivebytheprocessorbeforeT4ofthepreviouscycleorduringT1stateofthecurrentcycle the CPU activates HLDA in the next clock cyclecycle,theCPUactivatesHLDA inthenextclockcycleandforsucceedingbuscycles,thebuswillbegiventoanotherrequestingmaster

Thecontrolof thebusisnotregainedby theprocessoruntiltherequestingmasterdoesnotdroptheHOLD pin low When the request is dropped by theHOLD pinlow.Whentherequestisdroppedbytherequestingmaster,theHLDAisdroppedbytheprocessorat thetrailingedgeofthenextclock

BusRequestandBusGrantTimingsdin MinimumModeSystem