5091 4931e low cost surface mount power limiters

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Low Cost Surface Mount

Power Limiters

Application Note 1050

AbstractMany receivers are often at r isk

of having th eir front ends

burned out by high power RF

and microwa ve st ray signals .

This paper presents practical

design t echniques for low cost

power limiters opera ting a t

frequencies below 2 G Hz. B oth

circuit t echniques a nd S urface

Mount D evices (SMD) diode

tra de-offs are covered. Meas ured

dat a on severa l different proto-

type limiters a re presented.

IntroductionMicrowave a nd RF receivers, a s

well as many instruments, are

susceptible to damage from

input signals having a mplitudes

wh ich exceed some dan ger level.

For some instruments, such a s

counters, th is da nger level ma y

be as high a s one wat t . The front

end of some receivers can be

destroyed or degraded by powerlevels substa ntia lly less than

one wa tt . Furthermore, the

dan ger ma y come from

signals w hich are out of the

normal operating ba nd of the

device. Thus, for example, a G P S

or mobile telephone receiver,

operating at L-B an d, could be

dama ged by a nearby X-Ba nd

airport radar or the C-Bandrad ar of a nearby ship.

Such sensit ive instruments a nd

receivers ar e t ra ditiona lly protected

by a power limiter circuit.

The limiter should ha ve the

following characteristics:

• I t sh ou ld p rov id e ver y low

insertion loss to in-ba nd

sma ll signals (the desired

signa ls) in order t o keep

receiver noise figure a s low a s possible.

• I t sh ou ld pr ov id e ver y h ig h

loss to incoming signa ls

which exceed the danger

threshold.

• I t sh ou ld b e ver y fa s t , pr ov id -

ing protection within

nanoseconds of the arrival of

a da maging signal .

• Unlike a fuse, it must surviveexposure to the high power

signal and i t must return to

its low loss (small signal)

behavior w ithin n an oseconds

a fter t he high power signal

has disappeared.

In the m icrowave frequency

ran ge, such limiters have

tra dit iona lly been designedar ound a special t ype of P IN

diode ca lled a limit er diode.

How ever, the price of such

diodes is prohibitively high for

consumer and commercial ap-

plica tions. This pa per will

describe the a pplica tion of a low

cost S MD P IN diode to the design

of a limiter circuit operating up

to 2 G Hz.

Limiter Diode Basics

The limiter diode is a specia ltype of PI N diode. A th in

epitaxia l I-lay er is formed on a

heavily N+ doped substra te,

aft er which P+ top contacts a re

a dded by diffus ion. Typical

limiter diodes have I-layer thick-

nesses betw een 2 µm and 7 µm,

with corresponding values of

breakd own v oltage. The diode is

mounted in shunt a cross the

tra nsmission line which leads t o

the receiver front end, and is

provided wit h a D C bias return,

as shown in Figure 1. For in-

coming signals w hich are below th e

threshold level in a mplitude, the

diode acts as a n ordina ry unbiased

PIN diode1, which is to say tha t

it appears to be a capacitor of

1Agilent Technologies Application Note922, “Applications of PIN Diodes”



2

relatively small value. When the

incident signal exceeds the

thr eshold pow er level, the

diode’s I -la yer is flooded w ithcarriers during t he posit ive half-

cycle of the incoming RF s igna l.

Most of these ca rriers persist

through th e negative ha lf cycle,

DC current begins to flow in the

loop formed by t he diode and t he

bias retur n choke, and the diode

biases itself to a low value of

resistance in a ma tt er of

na noseconds. U nder th e influ-

ence of th is self-genera ted bia s

current, th e diode’s junction

resistance falls to a very low value, shorting out the tra nsmis-

sion line. The limit er circuit t hen

acts a s a reflective switch,

reflecting th e large signal ba ck to

its source and protecting the

circuitry which is “downstrea m”

from the limiter. When the large

am plitude incoming signal ha s

disappeared, the car riers in the

diode’s I-region recombine in a

ma tt er of na noseconds, the

circulat ing bias current stops

a nd t he diode’s junction resis-ta nce once aga in becomes very

high, allowing sma ll signa ls to

pass.

Limiter Diode DesignTradeoffsSeveral t rad e-offs exist in t he

design a nd selection of epi P IN

diodes for limiter a pplica tions.

For example, diodes with thick I-

layers t urn on “lat e” (at high levels

of input power), while those wit hthin I -layers tur n on “early.”

However, those with thin I-layers

are easily damaged by high pow er,

since they la ck the breakdown

voltag e a nd therm al conductivity

of the thicker diodes. The b eha vior

of three different limit er diodes,

having I-layers of 2 to 15 µm, is

illustrated in Figure 2.

When a tra nsmission line is

shunted by a resistor (such as a

self-bias ing P IN diode), some ofth e incident power is reflected

ba ck to the source, some pas ses

the resistor and is received in

the load, an d some is dissipated

in th e res ist or (in the form of

heat ). The percent of in ciden t

power w hich is actually dissipated

in the shunt device is a function

of its resista nce, as shown in

Figur e 5. At a va lue of 25 Ω (in a

50 Ω syst em), this fraction reaches

a m a ximum of 50%. This 25 Ω

shunt resistance corresponds toan a ttenua tion of 6 dB . Thus, a

thick limiter diode which turns

on lat e (see Figure 2) ma y pas s

th rough th is (6 dB ) point of

maximum dissipation at a

sufficient ly high power level that

it w ill itself burn out (as well as

being too “slow” t o protect a

receiver front end). Thus, a diode

with a 2 µm I-layer thickness

may be too fragile to make a good

limiter w hile one wh ich is 15 µm

thick is too slow. Clea rly, there

is a na rrow ra nge of optimum I-layer thickness for an effective

limiter d iode.

In t he design of low curr ent, low

Rs P IN diodes for switching

applicat ions, th e use of a thin

epitaxia l I-lay er offers a low cost

approach to meeting these design

goals . Agilent Technologies’

HS MP -4820 surface mount P IN

diode wa s evalua ted in a series of

limiter configura tions. These

PIN diodes were found to per-form quit e well as limiters, as

described below.

Package ConsiderationsThe performa nce of the limit er is

governed by the characteristic of

the P IN diode, the package and

the circuit in w hich it is conta ined.

Continuous wa ve power handling

capability is set by the ma ximum

junction temperat ure and t he

therma l resistance betw een

junction and am bient. One major

contributor is the t hermal

resistance of the pa ckage

(θpackage) and th e kind of heat sink.

The maximum power dissipation

of the diode can be estimated by

using the following formula:

Tjmax - Ta

P d = ————

θj-a

θj-a = θchip + θsolder + θpackage +

θheatsink

j-a : junct ion to a mbient

P d : maximum power

dissipation

Tjmax: m a x im u m ju n ct ion

temperature

Ta : a mbient t empera ture

30

20

10

6

0

A T T E N U A T

I O N ,

d B

0 10 20 30 40 50INPUT POWER, dBm

2 µm

4 µm

15 µm

ATTENUATION vs. INPUT POWERFOR LIMITER DIODES OF

THREE I-LAYER THICKNESSES

Figure 2. Comparison of Three LimiterDiodes.

35 < Vbr < 70V

2µ < W < 7µ

Figure 1. Basic Limiter Circuit.



3

There a re lar ge differences in th e

value of package t hermal resis-

tance from one package type to

an other. For exam ple, thetherma l resistan ce of th e bolt

channel package (e.g., the

Agilent package outline 61) is ≈25%

of the va lue for the SOT-23 package.

Insertion loss, isolation and

ma ximum frequency ra nge are

not only determined by the

diode’s capacitance and resis-

ta nce. P ackage inductan ce (due

to bondwires a nd package leads)

a nd t he specific circuit la yout

degrade the high frequency per-forma nce of th e limiter as well.

The ideal limit er packa ge should

meet th e followin g ma jor re-

quirements:

• B roa dba nd

• L ow t her ma l r es is ta n ce

• E a sy t o a ssem ble

• Inexpensive

The bolt chan nel packa ge

(Agilent outline 61) is a n idea lpackage for broadba nd, high

frequency a nd high power

applicat ions. Interna l bondw ires

add the proper amount of series

inductance to resonate th e

junction ca pacita nce of the diode

chip, forming a low pass filter

wit h fc > 12 G H z. The limit er

chip in t he bolt channel package

can be functiona lly integrat ed

into a 50 Ω balanced strip line or

microstrip t ra nsmission line2

a nd can be used up to X-ba nd

applicat ions. I nsertion loss a nd

isolat ion a re specified a t 9.4 G Hz

in the data sheet .

The gold plated copper body and

the gold plat ed kovar leads of the

bolt chan nel package achieve an

excellent thermal conductivity

an d give high power ha ndling

capabilities as high a s 50Ω peak.

The Agilent bolt cha nnel limit er

5082-3071 is successfully used in

many milita ry systems like radars,

EW equipment, radios, telemetry

equipment a nd ma ny others. It ’s

an excellent limiter but t oo costly

for high volume commercial

applicat ions such as t he 1.5 GH z

Global P osit ioning System (GP S)

receivers. To achieve the price

ta rgets for consumer and com-

mercial applications semiconduc-

tor ma nufacturers ha ve to offersurface mount components such

as the Agilent Technologies

HS MP -382X SMD P IN diode

series, ava ilable in t he SOT-23

package.

The SOT-23 is a plastic package

wit h tin/lead plat ed lea ds suit-

a ble for va rious soldering pro-

cesses such a s w ave soldering,

infrared reflow soldering an d

va por pha se reflow soldering. In

high v olume low cost commercia l

applications, surface mounttechnology is w idely accepted.

The J ED EC sta ndard Surface

Mount P a ckages (SOT-23 and

SOT-143) ar e excellent pa ckag es

with r espect to aut omatic SMD

pick and place assembly and a re

therefore well accepted by t he

industry.

Many diode configurations, such

a s singles, series pairs, common

an ode an d cathode pairs an d

others, ar e availa ble in a singleSOT package for specific

applications. This enables the

design engineer to minimize his

circuit a nd ma nufacturing costs.

However, the disadva nta ge of

this pa ckage is th e inherently

long bondwire inside the pack-

age, and t he bent leads, as shown

in th e top of Figur e 3. This

bondwire (LB = 1.0 nH) with t he

Figure 3. Bondwire Configuration in the SOT-23 Package.

2Agilent Technologies Application Note957-2, “Reducing the Insertion Loss of aShunt PIN Diode”

,

,

BONDWIREDIODE LL = 0.5 nH

RS

LB = 1.0 nH

LL = 0.5 nH

STANDARD CONFIGURATION HSMP-3820,-3821

BONDWIREDIODE LL = 0.5 nH

RS

LB = 0

LL = 0.5 nH

STITCH BONDED CONFIGURATION HSMP-4820

LB = 0

LL = 0.5 nH



4

tw o bent leads (LL= 0.5 nH each)

creat e a tota l series inducta nce

of 2 nH . This high va lue of

para sit ic inducta nce will resultin a high reacta nce at frequen-

cies above a few hundr ed MHz.

The result, in a shun t-mounted

diode, is a reduced value of

isolat ion a s shown in Figure 4.

Another importa nt para sit ic is

the package capa cita nce, typi-

cally 0.08 pF betw een opposite

leads. It ha s a m inor impact on

isolation performa nce in com-

parison to the high inductance

over t he frequencies under

discussion.

The P IN d iode chips a re die

a tt a ched on t he Alloy 42 (Fe/Ni)

leadframe using conductive epoxy.

After wirebonding, a molding

process t akes place and in the

next step the leads become tin/

lead plat ed. Most of the heat

generated at the diode’s junction

due to high power signals can only

dissipate through the silicon, epoxy

and leadframe into the heatsink

or P CB . The therma l resistance,mea sured from th e diode junc-

tion to an infinite heat sink, is

a pproxima tely 500 °C/W. I t

should be kept in mind tha t t he

a pplicat ion-specific circuit lay out

and P CB mat er ia l wil l ra ise the

therma l resistance from diode

junction to am bient air . How-

ever, during informal t esting, the

HS MP -4820 diode has shown the

ability to sta nd off 8 to 10 wa tts

of CW input power a t 25°C w hen

used as a limiter. To calculat epower ha ndling at high tempera-

tures, derate th is value linear ly

from 10 wa tts a t 25°C t o zero

wa t t s a t 150°C. To ca lculat e the

approximat e pulse power ha n-

dling capability , multiply this

CW power rat ing by t he factor

shown in the curve given in

Figure 6, keeping in mind tha t

the pulse duty fa ctor must be

such that the avera ge incident

power must be less than h alf the

CW power ra ting. Note tha t a llof these therma l calculat ions a re

estimates.

Up to this point, the discussion

ha s focussed on two standa rd

packages, the bolt chann el (wit h

its su perior performa nce) a nd

the standard SOT-23 (with its

low cost). We will now turn to a

discussion of solutions t o the

problem of extending the limiter’s

bandw idth. All solutions use a

“st itch bonded” PI N diode in aSOT-23, a s sh own on th e bottom

of Fig ure 3. This special product

is a st anda rd sur face mount

diode with an addit ional

bondwire “stitch bonded” from

th e die’s bond pad t o the nor-

ma lly unconnected pa ckage lead.

Tw o bondw ires, electrica lly in

para llel, exhibit only half t he

inductance of a single bondwire.

How ever, beca use of th eir very

close proximity, the two parallelbondwires are coupled resulting

in a cancellation of the induc-

ta nce L B , as sh own in the sche-

ma tic at the bottom of Figure 3.

To examine t he effect of para sitics

upon limiter performa nce,

consider a H SMP -3820 SMD P IN

in a microstrip shunt applicat ion.

Two effects of para sitics reduce

the bandw idth of the limiter.

One is the para sit ic inducta nce of

the package, the other is theinductance of the via holes which

bring ground potential up from

the microstrip groundplane. The

package inductance is nearly

consta nt , t ightly controlled by

the diode manufa cturer due to

aut omatic wire bonders, where

the via hole inductance depends

on several factors such as the

P CB mat er ia l , meta l l iza t ion,

thickness a nd hole diameter.

In a shunt configura tion, leadan d bondwire inducta nce of the

surface mount pa ckage prevents

higher frequency signals from

being shorted by t he diode’s low

resista nce. The react a nce due to

the para sit ic inductan ce is much

higher (approximat ely 19 Ω a t

1.5 GH z) tha n the RF resista nce

Figure 4. Effect on Isolation of Excessive Parasitic Inductance.

-5

-10

-15

-20

-25

I S O L A T I O N , d B

0.5 1 3FREQUENCY, GHz

1.0 nH

0.6 nH

0.4 nH

0.8 nH

ISOLATION OF A

SHUNT INDUCTOR

Figure 5. Power Absorbed in aLimiter Diode.

0.5

0.4

0.3

0.2

0.1

0

F R A C T I O N A L P O W E R D I S S I P A T E D

1 10 100 1000

SHUNT RESISTANCE, Ω

25 Ω

FRACTIONAL POWER DISSIPATED IN ASHUNT RESISTOR, 50Ω SYSTEM

Figure 6. Power Multiplier ForOperation With Short Pulses.

200

100

10

1

P O W E R M U L T I P L I E R

0.1 1 10 100 1,000 10,000

PULSE WIDTH, µsec

LIMITER DIODE POWER MULTIPLIER



5

Figure 8. Cross Section of a CoPlanar Waveguide.

GROUND PLANE

CENTER CONDUCTOR

GROUND PLANE

Figure 7. Plan View of a CoPlanar Waveguide With SOT-23 Shunt Diode.

(a pproxima tely 1 Ω). This

behavior is illustra ted in m ore

deta il in Figur e 4. This set of

curves shows isolat ion fordifferent values of inductance

versus frequency for an ideal

diode with Rs = 0 Ω. I t can easily

be seen tha t the sta ndard

H S MP -3820, with its 2 nH lead

inducta nce, can only be recom-

mended as a limiter at frequencies

below 500 MHz.

Transmission LineConsiderationsWhen a SMD is mounted in

shunt in a microstrip line, some

complicat ion is int roduced.

P lat ed-through via holes must be

used to bring ground up to the

top surfa ce of th e board. Not

only do these via holes introduce

some additional expense, but

they also insert a sma ll amount

of par asit ic inducta nce which

a ppea rs (electrically) betw een

the SMD an d ground, reducing

the a mount of available isola-tion. This is trea ted in more

deta il in the follow ing section.

CoPlanar Waveguide (CPW) is a

type of transmission line in

wh ich some of these problems

are eliminated. The following

trea tm ent of CP W is taken from

Wau gh an d Waugh3.

The configurat ion of CP W is

shown in Figures 7 (plan view)

a nd 8 (cross section). CoP lan a r

Waveguide is a tra nsmission lineha ving ground an d center con-

ductor on the sa me plan e of a

circuit boar d. The underside of a

CP W boar d is blank, with no

copper tr a ces a nd no ground-

plane. Transmission line imped-

an ce is set by the dimensions

shown in Figure 8. Note tha t

both t he linewidth and gapwidth

control Zo. In order to calculat e

the chara cterist ic impedan cefrom these dimensions, one ca n

use a computer progra m such a s

AppCAD 4 or MWTLC5. Howev-

er, a simplification is possible.

In order to a llow a SOT-23 diode

to strad dle the CP W as shown in

Figure 7, the sum of linewidth

plus 2 t imes ga pwidth (dimen-

sion 2b) must be maint ained a

const a nt eq ua l to 0.055 inch.

When th is design rest riction is

a pplied, t he computa tion of char-

acteristic impedance is reduced tothe simple graph given in F igure 9

(shown for two different board

materials).

Like microstrip, CPW is sensitive

to effects from the top and bott om

covers of the housing in wh ich

the board is mounted, as w ell as

coupling between transmission

lines. See Figur e 10. Some good

rules of thumb w hen using CP W

a re as follows: If D > 2b, Zo i s

independent of substra te t hick-ness. Keep S 1 > 3b. If H 1 > 4b

and H 2 > 3b, the covers ca n be

ignored in all calcula tions of Zo.

Mainta in S 2 > 5b to avoid cou-

pling betw een a djacent lines.

In order t o obta in good perfor-

mance from a circuit realized in

CP W, the potential of the

groundpla nes on either side of

the center conductor must be

kept equa l at a ll points a long the

line. This is illustra ted in Figur e

11, in which it is shown tha t

3R. W. Waugh and R. M. Waugh, “A ShuntPIN Diode T/R Switch for PCN Applica-tions” .4Agilent Technologies, “RF and Microwave

AppCAD,” Agilent part number HAPP-0001.5Daniel Swanson, “A Transmission Line

Calculation Program,” RF Design, August,1991, pp 66-67.

2b

2at

METALLIZATION

DIELECTRIC SUBSTRATE

εr



6

Figure 11. Maintaining Groundplanesat Equal Potentials.

, , ,

, , ,

, , ,

, ,

, ,

, ,

, , , ,

, , , ,

, , , ,

CONDUCTIVE BRIDGE

Figure 10. CPW Mounted in a Housing.

100

90

80

70

60

50

40

30

20

C H A R A C T E

R I S T I C I M P E D A N C E , Ω

0.015 0.025 0.035 0.045

LINE WIDTH, INCHGAPWIDTH + LINEWIDTH = CONSTANT (0.055 INCH)

HT-2 BOARD, εr ≈ 2.45

FR-4 BOARD, εr ≈ 2.6

DATA FROM MWTLC PROGRAM

BOARD IS 0.032" THICK WITH 1/2 oz.

COPPER CONDUCTOR

Figure 9. Characteristic Impedance of a CPW Line.

conductive brid ges, spa ced every

λ/4 t o λ/2, will ma inta in ground

planes at t he same potentia l.

Shun t stubs or transm ission line

intersections in CP W can lead t o

problems. Refer to Figur e 12.

Current s flowing a long the

ground planes ar e equal (in

phase) at plane I , but unequa l at

plan e II because of the longer

length of the path t aken by

I 1. A conductive bridge, as

shown in Figur e 13, solves the

problem. If one is using surfa ce

mount technology, an intercon-

necting line on th e backside ofthe board, with tw o via h oles

connecting it to the two ground-

plan es, reduces pick a nd pla ce

operat ions a nd gives the same

electrical results a s t he topside

conductive bridge.

At frequencies higher tha n t hosereported h ere, similar problems

can occur at bends in tra nsmis-

sion lines. Conductive bridges

interconnecting the ground

planes are required, or one can

maintain the ground plane intact

an d bridge the line as sh own in

Figur e 14.

Fina lly, the question of a t ran si-

t ion between CP W an d micro-

strip must be discussed, since

an y C P W component w ill eventu-ally ha ve to interface with a

convent ional microstrip circuit.

In F igure 15 such a tra nsit ion is

shown. This transit ion works

well to frequencies as h igh a s

3 GHz .

Several of the circuits were

realized in CP W, fit ted with

SMA connectors (E .F. J ohnson

142-0701-801) which are de-

signed for use wit h C P W.

The circuits w ere fabrica ted on

HT-2 PCB (Printed Circuit

B oard) ma teria l. HT-2 is a new

P CB ma terial offered by Agilent

Technologies’ P rint ed Circuit

B oard Division. B as ed upon

cyana te ester resin chemistry, itha s superior therma l and

mecha nica l properties when

compared to conventional FR-4.

Dielectric constant is better

controlled, a nd somewha t lower

in value.

Loss ta ngent of HT-2 is lower tha n

tha t of FR-4, resulting in a boar d

ma terial w hich is practical to use

at microwa ve frequencies. In both

microstrip and CPW circuits on

0.032" ma teria l, losses a re about 0.6dB/λ through 6 GH z. The chara cter-

istics of HT-2 ar e compa red t o

those of FR-4 in Figures 16 and 17.

Single Diode TestCircuitsThroughout the sections that

follow, the terms “insertion loss”

and “isolation” will be used. While

both a pply to the a ttenua tion

produced by a shunt mounted

limiter diode and its a ssociat edcircuitry, it is un derstood t ha t

“insertion loss” refers to the

undesirable loss under sma ll signal

condit ions, when the diode’s

junction resistance is very high.

“Isolation,” on th e other ha nd, w ill

be used to describe the protective

at tenua tion provided by the diode

an d circuit un der the applicat ion of

high power signa ls, when Rj is low .

The most obvious w a y in w hich

, , , , ,

, , , , , , ,

2b

DIELECTRIC SUBSTRATE

2a

S1 S2

εr

UPPER LID

LOWER LID

εo

H1

D

H2

t

εo



7

, , ,

, , ,

, , ,

, , ,

, , ,

, , ,

G2

G1

I1

I2

I1 = I2 AT I

I1 ≠ I2 AT IIZ

I II

, , ,

, , ,

, , ,

, , ,

, , ,

, , ,

CONDUCTIVE BRIDGE

, ,

, ,

, ,

, ,

, ,

,

,

Figure 12. Uncompensated Shunt Stubin CPW.

Figure 13. Compensated Shunt Stub inCPW.

, ,

, ,

, ,

0.050 INCH

OVERLAP

0.060 INCH WIDE MICROSTRIP

CONDUCTOR

0.043 INCH WIDE CPW

CONDUCTOR

0.030 INCH DIAMETER PLATED THROUGH VIA HOLE

TOP SIDE (CPW) GROUNDPLANE

UNDERSIDE (MICROSTRIP) GROUND

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.1

ε r ,

R E L A T I V E D I E L E C T R I C

C O N S T A N T

0.001 0.01 0.1 1 10 20

FREQUENCY, GHz

FR-4

HT-2

RELATIVE DIELECTRIC CONSTANT

Figure 16. Comparison of DielectricConstant.

Figure 15. Microstrip to CPW Transition.

Figure 14. Compensated CPW Bend.



8

to mount a SOT-23 packaged

limiter diode in shunt across a

microstrip line is shown in

Figure 18. Tw o leads of theSOT-23 package a re mount ed in

par a llel on th e 50 Ω transmission

line and t he third lead is sol-

dered on th e ground pad as

shown. Using th e st itch-bonded

HSMP-4820, this approach sim-

ply ta kes a dvanta ge of the a ddi-

tional para llel bondwire which

reduces th e package inducta nce

to L p = 0.75nH. Adding the via

hole inducta nce of ≈0.3 nH

resultin g from t he use of 0.032"

thick HT-2 substrate, the totalpara sit ic inducta nce is 1.05 nH .

Referring t o Figure 4, isolat ion of

Figure 17. Comparison of LossTangent.

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

t a n δ ,

L O

S S T A N G E N T

0 2 4 6 8 10 12 14 16 18 20

FREQUENCY, GHz

FR-4

HT-2

LOSS TANGENT

Figure 18. Shunt Mounted SOT-23 Limiter Diode.

Figure 20. Detail of Small SignalInsertion Loss of the Shunt MountedLimiter.

Figure 19. Small Signal Insertion Lossof the Shunt Mounted Limiter.

0

1

2

3

4

5

6

7

8

9

10

I N S E R T I O N L O S S , d B

0.1 1.1 2.1 3.1 4.1 5.1

FREQUENCY, GHz

S21

S11

this limiter is estimated t o be

about 9 dB in the G P S frequency

range, a value of protection

wh ich will not be consideredsufficient in m an y a pplicat ions.

Moreover, under sma ll signal

opera ting condit ions, the 50 Ωmicrostrip transmission line is

shunted by a series L-C combina-

tion of 1 nH a nd 0.8 pF. A quick

analysis on AppCAD 4 shows tha t

this combination forms a reso-

nant circuit a t ≈5 GHz, a very

undesirable characteristic (see

Figur e 19). Ev en a t low er

frequencies, such as those used

in GP S systems, the losses a reuna ccepta blably high as can be

seen from the AppCAD analsis

shown in Figur e 20. How ever

the next section describes a more

efficient circuit a pproa ch, yield-

ing higher values of isolat ion a ndlower insert ion loss, w hich does not

entail a ny a dditional expense.

This im proved design a pproa ch

integrat es the bondwire induc-

tance into the 50 Ω microstrip

tra nsmission line by cutt ing a

gap in the line and bridging the

gap w ith lead #1 and #2 of the

stit ch bonded limiter diode. Lea d

#3 must be grounded as shown in

Figure 21. The result is a circuit

0

0.2

0.4

0.6

0.8

1.0


0.1 1.1 2.1 3.1

FREQUENCY, GHz

S21

O.25 nH

0.8 pF

0.5 nH

0.3 nH

HSMP-4820

PAD CONNECTED TO

GROUND BY TWO

VIA HOLES

50 Ω MICROSTRIP LINES

EQUIVALENT CIRCUITCIRCUIT LAYOUT



t a nce (L = L L + LV = 0.5 nH +

0.3 nH ) becomes th e domina nt

factor in total shunt impedan ce.

This t otal shun t inductance of0.8 nH is less than the 1.05 nH

of the first circuit approach.

Reference to Figure 4 will sh ow

tha t a 2 dB improvement in

isolation results.

A test circuit was built to verify

the simulations by actual mea-

surements. Sma ll signal mea-

surements such a s insertion loss

were made with a sca lar network

analyzer. The high power

measurement t est setup for 1GH z and 1.5 GH z tests is shown

in Figure 22. Limit er diodes

sha re many of their cha ra cteris-

tics wit h st ep recovery diodes.

Therefore, under high power

condit ions the limiter diode

genera tes a comb of harm onic

outputs. Specifically the second

harmonic output power level can

be close to tha t of the funda men-

ta l. Therefore a low pass filter is

necessa ry t o reduce th e second

ha rmonic at the power meter toget a proper rea ding. To prevent

dam age to the power amplifier by

high power reflections a circula-

tor was used to terminate the

reflections. Notice that the

limiter circuit D C return is

provided by an external bia s

network.

Small signal insertion and return

loss for the im proved circuit of

Figure 21 were meas ured over

frequency a t low power levels(-10 dBm ) and display ed in

Figure 23. This an d all other

insertion loss measurements

were ma de with respect to a

50 Ω reference line of th e sam e

physical length a s the limiter

test circuit. Ins ertion loss of th e

9

which, under sma ll signa l

operat ing conditions, looks like a

low pa ss filter structure with a

higher cutoff frequency tha nobserved in first approach. As

described in AN 957-22, this

helps to reduce the small signa l

insertion loss in the pass ba nd.

Un der high power signal condi-

tions, the resistance of the diode

is reduced to an ohm or so.

Un der these conditions, the lead

inductance plus via hole induc-

Figure 21. Improved Shunt Mounting Technique.

Figure 22. Apparatus Used For High Power Measurements.Figure 23. Small Signal Performance,Improved Limiter Circuit.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

I N S E R T I O N L O S S ,

d B

0

5

10

15

20 R E T U R N L O S S ,

d B

0.5 0.9 1.3 1.7 2.1 2.5

FREQUENCY, GHz

RETURN LOSS

INSERTION LOSS

O.5 nH

0.8 pF

0.5 nH

0.3 nH

HSMP-4820

PAD CONNECTED TO

GROUND BY TWO

VIA HOLES

50 Ω MICROSTRIP LINES

EQUIVALENT CIRCUITCIRCUIT LAYOUT

O.5 nH

AGILENT 8481A

SENSOR

AGILENT 8481A

SENSOR

D.U.T.

20 dB

-20 dB

3 dB

AGILENT 438A

POWER

METER



10

improved limiter circuit is 0.1 dB

all the wa y up to 1.7 GHz a nd

increases t o about 0.35 dB at 2.5

G Hz. In the G P S band (1.5 GH z)return loss is better tha n 20 dB .

These measured results agree

well with the simulat ed values.

Limiter isolation performance

under high power conditions wa s

simulated by small signal

measurements using a n exter-

na lly applied DC bias t o reduce

th e diode junction resista nce Rjto its minimum va lue. The

results a re shown in Figure 24.

At 1.5 GHz the reading of isolationis 11.5 dB, w hich is close to th e

value of 11 dB calculat ed using

Figure 4. The effect of the para sitic

inductance can be seen in the de-

crease in isolat ion from 21 dB a t

500 MHz to 9 dB a t 2.5 G Hz.

Finally, the improved limiter

wa s tested under high rea l

power conditions at 1 G Hz a nd

1.5 G Hz. The ma ximum applied

CW power wa s 10 wa t ts a t

1 GHz and 1 wa t t a t the higher

frequency. Results are shown inFigure 25; note tha t t he thresh-

old level is in th e ra nge of

P in ≈ 8 dB m. Above this thresh-

old level the limiting effect ta kes

place an d reaches its ma ximum

isolat ion of 17 dB at 35 dB m input

power at 1 GH z. However, at 1.5

G Hz t he limiter reaches a

ma ximum ins ertion loss of 10 dB

a t 27 dB m input power. The

different cha ra cterist ics of the 1

G Hz a nd 1.5 G Hz curves corre-spond t o the var iat ion in exter-

na lly biased isolat ion a s shown

in Figu re 24.

Figure 26 shows the la rge signal

transfer curve of P out versus

P in , the sam e data of Figure 25

displayed in a different format .

From it one can easily see that

the circuit ma inta ins output leak-

age power to less than 100 mW

for input power levels of 1 wa tt

a t 1.5 G Hz and up to 5 wa t t a t 1G Hz input power.

Up to this point , the tests a nd

measurements described ha ve

highlighted the performance of

the st it ch bonded P IN diode

mounted in microstrip tra nsmis-

sion lines. As described above, a

ma jor cont ribut or to the lack of

isolation performance is the via

hole inducta nce to ground. This

fact led us to consider CoPla na r

Wa veguide technology, bypa ss-ing the problem of parasitic via

hole inductance.

B ased on the sam e idea of inte-

gra ting the lead inducta nce into

a 50 Ω t ra nsmission line to form

a low pass filter structure, a co-

plana r wa veguide test circuit

Figure 24. Isolation With ExternallyApplied DC Bias, Improved Limiter.

5

10

15

25

I S O L A T I O N ,

d B

0.5 0.9 1.3 1.7 2.1 2.5

FREQUENCY, GHz

20

INSERTION LOSS

18

16

14

12

10

8

6

4

2

0

I S O L A T I O N ,

d B

0 5 10 15 20 25 30 35 40

CW POWER IN, dBm

IMPROVED MICROSTRIP LIMITER

MEASURED WITH EXTERNALBIAS RETURN

1.0 GHz

1.5 GHz

Figure 25. Large Signal Isolation of theImproved Limiter.

30

25

20

15

10

5

0

C W P

O W E R O U T , d B m

0 5 10 15 20 25 30 35 40

CW POWER IN, dBm

1.0 GHz

1.5 GHz

IMPROVED MICROSTRIPLIMITER

MEASURED WITH EXTERNAL BIASRETURN

Figure 26. Large Signal Transfer Curveof the Improved Limiter.

shown in Figure 27 wa s fabri-

cated using HT-2 substrate

ma teria l. As can be seen from

the equivalent circuit in Figure27, the elimina tion of via hole

inductance reduces the t otal

para sit ic inducta nce to 0.5 nH,

offering t he possibility of higher

isolation than the improved micro-

strip limiter described above.

Insertion loss a t low input power

levels wa s measured on the CP W

test circuit , with t he results a s

shown in Figur e 28. Ins ertion

P IN diode is mounted with the

tw o interconnected leads st rad -dling the tra nsmission line, as

loss is quite good below 1 G Hz

an d rolls off badly a round 1.3

G Hz. High input power levels

were simulat ed by externa lly

biasing t he diode to display

isolation performance versus

frequency (Figur e 29). Com-

pared to the microstrip approach

an improvement of 4 dB is demon-

stra ted, as expected. Neverthe-

less th is version is m ore compli-

cated to fabricate due to the con-ductive bridges. Also the inser-

tion loss roll off is a nother

disadva nta ge which will become

a noise figure problem a bove 1.5

G Hz in receiver front ends.



11

Figure 27. CoPlanar Waveguide Limiter Circuit.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7


0

5

10

15

20 R E T U R N L O S S , d B

0.5 0.9 1.3 1.7 2.1 2.5

FREQUENCY, GHz

RETURN LOSS

INSERTION LOSS

5

10

15

25


0.5 0.9 1.3 1.7 2.1 2.5

FREQUENCY, GHz

20

INSERTION LOSS

Figure 28. Small Signal Performance, CPWLimiter.

Figure 29. Isolation With ExternallyApplied DC Bias, CPW Limiter.

In t he next section a more con-

venient an d lower cost coplana r

wa ve guide approach will be

presented. The stitch bonded

P IN diode is mounted with the

tw o interconnected leads st rad -

dling the tra nsmission line, asshown in Figure 30, eliminating

the conductive bridges. The

package inductance to ground is

reduced to 0.75 nH . U nfortu-

na tely, the low pa ss filter struc-

ture is lost in t his mounting.

Low input power mea surements

show a n excellent insertion loss

performa nce below 1 GH z, with a

ba d roll off above 1.3 G H z.

Isolation performa nce was

simulated by forward biasing the

diode. At 1.5 G Hz t he isolat ion is

ar ound 13dB, 1.5dB better tha n

the improved microstrip ap-

proach of Figure 21. Next,

measurements w ere ma de of thelimiting performance under

high pow er condit ions. At 1 G H z

the m aximum achieved isolation

wa s around 17 dB and t he

ma ximum isolat ion at 1.5 GH z is

close to 13 dB - the best result w e

achieved w ith a single limiter

diode. The improvemen t of 3 dB

compa red to t he improved

microstrip design ca n be ex-

plained by the low t otal para sit ic

inductance to ground. Output

power leaka ge (Figur e 31) is well

below 15 dB m for frequencies up to

1.5 GH z a nd input power levels up

to 25 dB m. Only above 5 wat t input

power will the leakage be higher

tha n 100 mW at 1 GHz.

Transmission Lines andλ/4 SpacingI f a shunt a t tenuat ing element

produces X dB of isolat ion, tw o of

them spa ced very closely t o-

gether (compared t o a w ave-

length) will produce X + 3 dB of

isolat ion. However, if they are

spaced λ/4 (a qu a rt er w a velength)

apa rt, the pair will produce a ppro-

0.5 nH

0.8 pF

0.5 nH

EQUIVALENT CIRCUIT

CIRCUIT LAYOUT

0.5 nH

UPPER GROUNDPLANE

LOWER GROUNDPLANE

CENTER CONDUCTOR

HSMP-4820

CPW LIMITER WITHDIODE AND TWO

GROUNDPLANE BRIDGES



13

Figure 36. AppCAD Network Description.

Figure 35. Analysis of CPW Line.

ximately 2X + 6 dB of isolat ion.

Moreover, this enhancement

occurs over a substa ntia l band-

width , w ith lit t le loss of isolat ionover most of a n octa ve. Thus,

two limiter diodes spaced λ/4

apa rt should demonstra te much

higher levels of protection th a n a

single diode. Tha t th is is indeed

th e ca se will be seen in the next

section.

While a 90° segment of line isnot large a t 1.5 GH z (being a bout

1.25 inches long), it can be prohi-

bit ively la rge at lower frequen-

cies. In t hese cases, one ca n sub-

stitut e the lumped element

equivalent to a λ/4 lin e w hich is

shown in Figure 32.

Two Diode Test CircuitsIn F igure 7 a st itch-bonded

HSMP-4820 PIN diode is shown

mounted on a CP W line, stra d-

dling the upper a nd lower

groundpla nes. D iscussed ear lier

in the paper, this limiter pro-

duced about 12 dB of isolation at

1.5 G H z (see Figur e 31). Tw o

such limiters, separat ed by λ/4,

could rea sonably be expected t o

exhibit approximat ely 12 + 12 +

6 = 30 dB of isolat ion. In fact ,

the AppCAD a na lysis shown inFigures 33 and 34 predict an

isolation of 29 dB from two shunt

inductors of 0.7 nH, separated by

90° at 1.5 G Hz . A test circuit

wa s fabricated on a 2.0" length of

CP W, using tw o diodes separa ted

by 0.680" of line. As can be seen

from the AppCAD analysis of

Figure 35, this physical length

corresponds t o an electrical

length of 50° at 1.5 G Hz. When

the circuit shown in Figur e 33 is

modified to reduce the separation

between shunt inductors t o 50°,

the result is as shown in Figure

37. P redicted isolat ion is 28 dB ,

a sa crifice of only 1 dB of isola-

tion in exchan ge for a 50%

savings in space.

When sma ll signal mea sure-

ments w ere made on this circuit ,

the results were as shown in

Figures 38 a nd 39. Retur n loss

wa s a ccepta ble at frequencies upto 1.7 GHz, and insertion loss

wa s reasonable (less than 0.5 dB )

to 1.5 G Hz . When the diodes

were externa lly biased at 25 mA

each, measured isolation (Figure

39) was 32 dB, slightly higher

tha n predicted.

The experimental board was

then high power tested a t 1.0

and 1.5 GHz, a s shown in Fig-

ures 40 a nd 41. Att enua tion vs.

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4.20

45.000 MIL

5.000

32.000680.000

WIDTH

HEIGHTGAPεr

NOTE: NO GROUNDPLANE

INPUT

Zo:

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2.44

48.57 DEG

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14

Figure 42. Some Members of the HSMP-382X Family.

Figure 37. AppCAD Performance

Calculation.Figure 38. Small Signal Performance,Zero Bias, Two Diode Limiter.

20

25

30

351.0 1.5 2.0

FREQUENCY, GHz

S21

I S O L A T I O N ,

d B

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7


0

5

10

15

20 R E T U R N L O S S ,

d B

0.5 0.9 1.3 1.7 2.1 2.5

FREQUENCY, GHz

RETURN LOSS

INSERTION LOSS

30

25

20

15

10

5

0

C W

P O W E R O U T ,

d B m

0 5 10 15 20 25 30 35 40

CW POWER IN, dBm

1.0 GHz

1.5 GHz

MEASURED WITH EXTERNAL BIASRETURN

TWO DIODE LIMITER USING CoPLANAR

WAVEGUIDE STITCH-BONDED SOT-23 DIODE

24

0


0 5 10 15 20 25 30 35 40

CW POWER IN, dBm

22

20

18

16

14

12

10

8

6

4

2

MEASURED WITH EXTERNAL

BIAS RETURN

1.0 GHz

1.5 GHz

Figure 39. Small Signal Performance,+50mA Bias, Two Diode Limiter..

Figure 40. Attenuation vs. Pin, TwoDiode Limiter Using CoPlanarWaveguide SOT-23 Diode.

Figure 41 Pout vs.Pin, Two DiodeLimiter.

25

30

35

40


0.5 0.9 1.3 1.7 2.1 2.5

FREQUENCY, GHz

INSERTION LOSS

15

20

,

,

BONDWIREDIODE

STANDARD

CONFIGURATION

HSMP-3820,-3821

BONDWIREDIODE

STITCH BONDED

CONFIGURATION

HSMP-4820

BONDWIREDIODE

COMMON CATHODE

CONFIGURATIONHSMP-3824

DIODE

COMMON ANODE

CONFIGURATION

HSMP-3823



32

24

16

8

0

I S O L A T I O N ,

d B

0 10 20 30 40

CW POWER IN, dBm

1.5 GHz

1.0 GHz

HSMP-3823 AND HSMP-3824, SEPARATED BY

18mm (0.700 INCH) OF CoPLANAR WAVEGUIDE

32

24

16

8

0

C W

P O W E R O U T ,

d B m

0 5 10 15 20 25 30 35 40

CW POWER IN, dBm

1.0 GHz

1.5 GHz

HSMP-3823 AND HSMP-3824, SEPARATED BY18mm (0.700 INCH) OF CoPLANAR WAVEGUIDE

Figure 43. Four Diode Limiter. Figure 44. Small Signal Performance,Four Diode Limiter.

HSMP-3823 HSMP-3824

Figure 45. Loss vs. Pin, Four DiodeLimiter.

Figure 46. Po vs. Pin, Four DiodeLimiter.

Figure 47 Comparison of Two and FourDiode Limiters.

15

32

24

16

8

0

I S O L A T I O N ,

d B

0 10 20 30 40

CW POWER IN, dBm

COMPARISON OF TWO DIODE AND FOUR DIODE

LIMITERS. DATA AT 1.0 GHz

FOUR DIODE LIMITER

TWO DIODELIMITER

(WITH EXTERNALBIAS RETURN)

input power is shown in Figure

40. U nlike the single diode

limiter, performa nce at 1.0 GH z

is mar kedly different from tha tat 1.5 G Hz. B ecause the diodes

a re only 33° apa r t a t 1 .0 GHz ,

there is less enhancement due to

diode separ at ion, a nd t he result

is a lower level of a t tenua tion

than measured a t 1.5 GHz

(where the separation is 50° ).Interestingly enough, one can

see the tw o diodes working in

cascade in th e 1.0 GH z curve.

Around P in = + 24 d B m , t he

at tenua tion begins to show signs

of leveling off. How ever, wh enP in ≈ + 27 dBm, t he RF power

leaking past the first diode

(about + 16 dB m) begins to “turn

on” the second diode, and the

curve of at t enuation begins t o

climb once again.

Figure 41 is a transfer curve of

P out vs. P in , one which shows

the sam e data as F igure 40, but

in a more meaningful way. From

it one can easily see tha t t his

circuit mainta ins output leakage

power w ell below + 20 dB m for

input power levels up to 10

wa tt s. This is extremely useful

performance for a power limiter.

Four Diode Test CircuitIn the two diode limiter described

a bove, both diodes are of the

same polarity (anode grounded,

cathode connected t o the tra ns-

mission line center conductor)

an d both use a common groundreturn to complete their bias

loops. Thus , th e “front ” diode

turns on first , almost rea ching

its full va lue of isolat ion before

leakage past it is sufficient to

turn on the “back” diode. If

diodes of opposite polarit y w ere

ava ilable, each could serve as th e

ground return for the other,

elimina ting th e need for an

externa l choke and forcing both

diodes to turn on at the sam e

point in the t ran sfer curve.

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

I N S E R T I O N

L O S S ,

d B

0

5

10

15

20

R E T U R N L O S S ,

d B

0.01 0.41 0.81 1.21 1.61 2.01

FREQUENCY, GHz

RETURN LOSS

INSERTION LOSS



Un fortuna tely, only one polarity

is ava ilable for the P IN diode

chip used in th e HS MP -4820.

However, diode pairs a re ava il-able in both polar it ies, as sh own

in Figure 42. Of course, a pair

such as th e HS MP -3823 an d the

HS MP -3824 ha ve tw o diodes in

RF para llel when they are mount-

ed stradd ling a CP W (as sh own

in Figu re 7). The good new s is

tha t t his cuts the effective value

of Rs in half, improving isolation.

The bad n ews is th at it doubles

the effective capa cita nce from

cent er conductor t o ground,

lowering the upper limit of thepractical frequency ra nge.

A four diode limiter w a s con-

structed as shown in F igure 43.

Spacing between the front a nd

rear diode pairs was 0.700 inch.

Sma ll signal, zero bias insertion

loss a nd return loss are shown in

Figure 44. Insertion loss is about 0.7

dB at 1.0 GH z, a ma rginally high

va lue of loss. At 1.5 G H z (see

the ma rker on Figure 44), the

loss is 1.3 dB, t oo high t o be ofpractical value. Clearly, the high

capacitance result ing from the

use of tw o diodes in par a llel has

restricted this circuit to opera t ion

at relat ively low frequencies.

Return loss is reasonable out to

1.6 GHz or so. No sma ll signa l

isolat ion wit h forwa rd biased

diodes wa s obtained, since the

diode arra ngement made it im-

possible to apply a n external D C

current t o all four diodes simul-

ta neously. Figure 45 gives the

insertion loss vs. input pow er for

the netw ork. The effect of having

two diodes in parallel in each

loca tion can be seen in th e very

high level (30 dB) of isolation

wh ich is a chieved. The fa ct tha t

the forwa rd diode pair is biasing

the rear pa ir lead s to a very steepslope of attenuation vs. P in .

While this can be seen from a

careful comparison of Figures 17

and 40, it can be more easily

seen from the plots in F igure 47.

In F igure 46, the tra nsfer curve

of the four diode limiter is g iven.

Output leakage barely exceeds

+ 10 dB m for input power levels up

to 10 wat ts, ma king t his circuit

suita ble for t he protection of very

sensitive r eceivers.

ConclusionsSensit ive receiver front-ends in

commercial applications such as

G lobal P osit ioning Syst ems

(G P S) can be protected a gainst

excessive RF a nd m icrowave

pow er levels up to 8 to 10 wa tt s

through th e use of a limiter

circuit and special surface mount

plastic package PI N diode.

Sin gle limiter diode circuits for

L-B an d a pplicat ions, wit h inser-

tion loss on t he order of 0.1 dB

an d a rea sonable leakage power

of 100 mW for input signals of 1

watt , have been demonstrated

using the “st itch bonded” HS MP -

4820 on microstrip tra nsmis sion

line. A type of tra nsmis sion line

new t o the commercial ma rket,

CoPla na r Waveguide, has been

shown to eliminate para sit ic

inductance caused by via holes to

ground, extending the ban d-

widt h of limiter circuits a ndreducing high power leakage.

Tw o and four diode limiter

circuits were demonstra ted

providing isolat ion a s high a s 30

dB for UH F applicat ions.

It m ust be noted that good limiter

performa nce is highly dependent

upon the th ickness of th e I-lay er

a nd t he lifetime of the diode.These characteristics are not

tight ly contr olled in the produc-

tion of low cost, high v olume

switching PIN diodes. Therefore,

the user must ta ke one of severa l

precaut ions t o insure tha t diodes

do not va ry in th eir limiter chara c-

terist ics from one lot t o the next.

First , one can t est sa mple diodes

from several lots, buying all of

each lot w hich meets t he limiter

performa nce para meters. Sec-

ond, one can ask t he man ufac-turer to guara ntee limiter

performance, transferring the

burden of testing t o him. Obvi-

ously, the first a lternat ive is the

cheapest while the second is the

most convenient.

It ha s been shown previously

tha t diode capa cita nce is a m ajor

cont ribut or to the n oise figure of

a r eceiver which is protected by a

limiter. Careful process control

an d testing provides for t ightcont rol of the P IN diode capa ci-

tance and a l lows a maximum

va lue to be gua ra nt eed. This

permits the design engineer t o

specify his receiver for min imum

noise figure.

Of course, limiters do not help to

improve the signa l reception of

the syst em, but t hey do protect a

receiver from severe E MF con-

dit ions. For the manufa cturer of

commercial systems, this could

present a sa les adva ntage as well

as a performa nce benefit . Long

used exclusively to protect

expensive electronic warfare

equipment, low cost limiters a re

now a vaila ble for commercial

applications.

w w w . s e m i c o n d u c t o r . a g i l en t . c om

Data subject to change.

Copyright © 1999 Agilent Technologies, Inc.

5091-4931E (11/99)

5091 4931e low cost surface mount power limiters

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