5d_3 timing model red for hirarcy timing analysis

8/10/2019 5D_3 timing model red for hirarcy timing analysis

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Timing Model Reduction for

Hierarchical Timing Analysis

Shuo Zhou

SynopsysNovember 7, 2006


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Outline

Static Timing Analysis in Design Flow

Hierarchical timing analysis

Proposed Techniques Iterative timing model reduction algorithm

based on a biclique-star replacement

technique.

Experimental Results

Conclusions


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Static Timing Analysis in Design Flow

Static Timer is integrated in each stage. Need efficient static timer.

Design Flow

Floorplaning

Synthesis

Placement&Routing

Static TimingAnalysis


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Hierarchical Timing Analysis Hierarchical timing analysis is essential for

hierarchical design.

Consider circuits inside the blocks to be fixed.

Complexity O(n): n is #edges in timing models.

gates

PartitionDesigninto Blocks

Characterize Blocks

into Timin Models

gates

gates


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Problem Statement

Timing model minimization for

hierarchical timing analysis:

Given a hierarchical block, constructan abstract timing model with minimal

number of edges that covers the

longest and shortest path delays of

each pair of input and output in the

block.


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Previous Works

Transform timing graph [Visweswariah

ICCAD99, Moon DAC02]. Perform serial/parallel edge merging.

Represent delay matrix with minimal number of

edges. Optimal realization of a distance matrix

[Hakimi Quart. Appl. Math. 22 (1964), Chung

http://www.math.ucsd.edu/fan]. Biclique-star replacement for bicliques with

unit edge delay [Feder Symp. on Theoretical

Aspects of Computer Science (2003)].


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Terminologies: Bipartite Timing Model

G = {B, D, E} Input set B, output set D, and edge set E

Longest and shortest delays.


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1

67

3

5

2

3

9

10

11

78

Bipartite timing model

4

1 2

2

1

1

1

1

2

3

4

2

3

5

6

7

8

9

10

11

Timing graph

1

1

1

1 2

path: 1->4->5->7->8->10


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Delay matrix

Element on row i col j is delay from input i to

output j, for disconnected input i and output j.

Row i implies input delay vector = {di,j| di,jfrominput i.}

1

67

3

5

2

3

4

5

6

78

Bipartite timing model

4

I1

I2

OutputsO4

I3

O5 O6

3 7 8

6 7

4 5

Delay matrix

Inp

uts


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Star

Gs= (Bs, Ds, s, Es)

Bsinput set, Dsoutput set, center vertex s.

Edges (i,s) and (s,j).

31

34

2

3

s 5

6

Star1

44

1


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Biclique-Star Replacement

Basic idea: match various input delay

vectors to a pattern and cover each inputdelay vector by one edge plus the pattern.


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1

45

2

6

2

3

4

5

6

3

43

4 5

Biclique #edge = 9

1

2

2

3

4

1

2

3

s

4

5

6

0

star #edge = 6

Replace

dij= dis+dsj

I1

I2

OutputsO4

I3

O5 O6

2 3 43 4 5

4 5 6

0 +1 +

OutputsO4

2 +

O5 O6

2 3 42 3 4

2 3 4

Pattern=Input

vectors


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Delay Vector Subtraction

Input delay vector subtraction Sub(Ia, Ib) Distance vector V(Ia,Ib) = {j

Ia,Ib=da,jdb,j| j

[1..c]}

Input vectors Ia, Ibshare a pattern if all jIa,Ib

are equal.

V (I2,I1)=

Sub(I2,I1)

1 1 1

O4 O5 O6I1

I2

2 3 4

3 4 5


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Biclique Expansion for Replacements

Choose an input delay vector as the patternvector.

Expand the biclique of the pattern vector bycovering as many as possible input vectors.

Replace the biclique by a star.

Biclique Expansion (G, Ia, Gc)

I. Add edges (a,j) to biclique Gc;

II. For each input vector Ii

1. Vector subtraction Sub(Ii,Ia);2. If all j

Ii,Ia= 0Ii,Ia add edges (i, j) to Gc.

Biclique-star Replacement (Gc,Ia,Gs)

I. Add inputs, outputs, center vertex s, and edges (i,s), (s,j) to GsII. da,s= 0, ds,j= Ia,j;

III. For each edge (i,s) in Gs

1. di,s= 0Ii,Ia;

d # d 8


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1

45

2

7

2

3

4

5

6

34

3

45

#edge = 9

1

2

34

1

2

3

s

4

5

6

0

#edge = 8

I1

0I2,I1

7

45

Replace

2 2 3

I3 4 5 7

2 3 4I1

V(I3,I1) =

Sub(I3,I1)

O4 O5 O6step 2

V (I2,I1) =

Sub(I2,I1)

1 1 1

O4O5 O6I1

I2

2 3 4

3 4 5

step 1

0I2,I1


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Dont Care Edges

Edge (i,j) is a dont care edge in a biclique

star replacement if path delay di,s+ ds,j< di,j.

Replace

Biclique

Dont Care Edge

1 2

73

4

5

6

34

45

Star

2

2

3

4

1

3

s

4

5

6

0

7


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Biclique Expansion with Dont Cares

Choice: try each in distance vector as di,s. For d3,s=

di,jis coveredif di,s+ ds,j= di,j, i.e., j= .

di,jis a dont care edgeif

j>

. Output j has to be removedif j< .


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#edges covered

increases by 2

2 2 3

I3 4 5 7

2 3 4I1

V(I3,I1) =

O4O5O6

2

2

3

4

1

3

s

4

5

6

0

#edges covered

decreases by 1

3

4

1

3

s

6

0 2

3

4

5


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Biclique Expansion and Replacement with

Dont CaresBiclique Expansion with Dont Cares (G, Ia, Gc)

I. Add edges (a,j) to Gc;II. For each input vector Ii

1. Vector subtraction Sub(Ii,Ip);

2. For each jin the distance vector

For each kin distance vector

if k

= j

#covered++;else if k< j #removed +=edges to output k;

3. If maximum (#covered - #removed of j)> 1;

For each kin distance vector

if kj Add edge (i,k) to Gc;

else remove output k and edges to k.

Replacement with Dont Cares (Gc, Ia, Gs)

I. Add inputs, outputs, center vertex s, and edges to Gs

II. da,s= 0, ds,j= Ia,j;

III. For each edge (i,s) in Gs

1. di,s= min(Ii,Ia

).


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Replace

1

45

2

7

2

3

4

5

6

34

3

45

#edge = 9 #edge = 7

Dont Care Edge

12

2

34

1

2

3

s

4

5

6

0

I1Min

7

V (I2,I1)=

Sub(I2,I1)

1 1 1

O4O5 O6

I1I2

2 3 43 4 5

step 1

2 2 3

I3 4 5 72 3 4I1

V(I3,I1) =

Sub(I3,I1)

O4O5 O6step 2

Bi tit Ti i M d l R d ti


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Bipartite Timing Model Reduction

Biclique Search

Reduction RatioEvaluationratio = #edges_covered/(r+c)

Biclique-star

Replacement

Reduction > 1 Re-evaluation

Star Graph toBipartite Graph


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Split s1,s2

RecoverStars

6

1

2

3

4

s2'

s1'

s1

s2

9

8

7

5

bipartite graph

s1

1

2

3

5

6

s2

9

7

8

4

star timing model

Star Graph to Bipartite Graph

Transformation


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Correctness

G: the bipartite timing model before thereduction.

G': the timing model after the reduction.

Edge delay di,jof any connected input i andoutput j in G is covered by the longest pathdelay d

i,j

' from input i to output j in G' after thereduction.


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Experimental Results

Test cases

Block 1: 8499 inputs, 16885 outputs, and138,360 edges

Block 2: 4260 inputs, 7728 outputs and

103,414 edges EG-- #edges in original timing graph of theblock.

EB--#edges in bipartite timing model.

Em--#edges after timing model reduction.

Reduction rG= (EGEm)/ EG.

Reduction rB= (EBEm)/ EB.


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Block1 EG= 138,360, EB = 262,491

Err_bound

(ns)

Em rG rB

0 249,032 -80.0% 5.1%

0.1 41,696 69.9% 84.1%

1.0 36,980 73.3% 85.9%10.0 35,981 74.0% 86.3%

100.0 36,169 73.9% 86.2%

|di,jdi,j|


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Block2 EG= 103,414, EB= 465,190

Err_bound(ns)

Em rG rB

0 397,384 -284.3% 14.6%

0.01 49,613 52.0% 89.3%0.10 29,477 71.5% 93.7%

1.0 21,192 79.5% 95.4%

10.0 20,262 80.4% 95.6%Buffer 1 delay = 0.74ns.


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Conclusions

We propose a biclique-star replacement

technique and develop an iterative timing

model reduction algorithm based the

proposed technique. By allowing reasonable error bounds, the

experimental results show that the proposed

algorithm can effectively reduce the numberof edges in the timing model.


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Thanks!


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5d_3 timing model red for hirarcy timing analysis

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