5.low power circuit

8/2/2019 5.Low Power Circuit

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5 Low-power CMOS Circuits


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Circuit level choices

Different approaches and topologies

Static versus dynamic

Pass-gate versus normal CMOS

Asynchronous versus synchronous


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The coming thing in transistors

Polysilicon gate will be replaced by metal Silicon dioxide gate insulation will be

replaced by material with higher dielectricconstant Silicon substrate will be replaced by

strained silicon Single gate will be replaced by double gateand basic transistor structure will change


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Putting a strain in silicon to speed

up transistors The first step in making strained silicon is to

replace some of the atoms in the top layer of thesilicon wafer with germanium atoms.

Because germanium atoms are bigger than siliconatoms, the distance between atoms in the silicon-germanium layer increases.

Next, a layer of silicon is grown on top of thesilicon-germanium. The crystal structure in this top layer of silicon is

strained as it stretches to line up with the silicon-

germanium layer below.


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90-nm

Intel is charging into the nanoscale era withits new 90-nm manufacturing process.

In this scale, the transistors will have gatelengths of only 50 nm.

The silicon dioxide insulation, barely

visible beneath the gate, is only about 5atomic layers thick.


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SIA (Semiconductor Industry

Association) According to the SIAs roadmap, high

performance ICs will contain by 2016 more

than 8.8 billion transistors in an are 280 nm2 Typical feature sizes, which are also

referred to as linewidths, will shrink to 22

nm.


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Intel will take products to 32nm and beyond.

Intel is looking at a variety of technologies

including high-k/metal gate, 3-D transistors,and III-V materials, even carbon nanotubes,and semiconductor nanowires as high-

mobility materials for future high-speed andlow-power transistor applications and futureinterconnect applications (SoC, NoC).


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To address the leakage problems that come withshrinking transistors, Intel has identified a newhigh-k material, to replace the transistor's silicondioxide gate dielectric, and new metals to replacethe polysilicon gate electrode of NMOS andPMOS transistors.

These new materials, along with the right processrecipe, reduce gate leakage to less than 4% ofwhat it was for the previous process generation,while delivering record transistor performance.


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Intel is investigating 3-D transistors thathave a gate that controls the flow of current

from 3 sides.


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5.2 Circuit Design Style

Fully complementary CMOS logic hasexcellent properties in many areas, such as

ease of design, low-power dissipation, lowsensitivity to noise and process variations,and scalability.

However, the logic family suffers fromlower performance, especially for largefanin gates.


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Differential Cascode Voltage Switch Logic


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5.2.2.1 Domino Logic

The output of a gate is sometimes precharged onlyto discharge in the evaluation phase.

Therefore, the signal activity at the output can behigh. Increased signal activity along with the extraload that the clock line has to drive is primarilyresponsible for high power dissipation in domino

compared to static CMOS circuits.


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5.2.2.2 Differential Current

Switch Logic (DCSL) Here Q and Q discharge towards ground

through T6, T7 and T10. The discharge of Q

and Q is not symmetrical because thenMOS tree assures that one of the outputs,say Q, has a stronger path to ground.

The cross-coupled inverter functions as asense amplifier and boots the output voltagedifferential in the right direction.


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The presence of transistors T5 and T8 iswhat differentiates this gate from other

DCVS logic gates.


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SPICE simulations show that internal nodevoltage swings for DCSL are of the order of

1 V with a supply voltage of 5 V. A completion signal may be generated bytaking a NAND of the two outputs(precharged high).

The power advantage is primarily becauseof the very low internal voltage swings.


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Lower clock load & Done signal


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Precharge low DCSL

The circuit enters the evaluate mode withthe CLK going low.

Since evaluation starts only after the outputshave crossed Vtn, the gate propagation delaydegrades.


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Limiting the discharge voltage to

Vtn lowers the power dissipation


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Gate operation starts with CLK high, T9 onand nodes Q and Q equalized.

Hence Q and Q discharges to a voltage thatis Vtn or lower, through transistors T6 andT7.


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SSDL (sample set differential logic)

CVSL (cascade voltage switch logic)


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ECDL (emitter coupled differential logic)


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5.3 Leakage current in deep

submicrometer transistors The off-state leakage in long-channel devices is

dominated by drain-well and well-substrate

reverse-bias pn junctions. For short-channel transistors, the off-state currentis influenced by threshold voltage, channelphysical dimensions, channel/surface doping

profile, drain/source junction depths, gate oxidethickness, the supply voltage, the drain and thegate voltages.


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5.3.1.1 pn Reverse-Bias Current

A reverse-bias pn-junction leakage I1 hastwo main components: one is the minority-

carrier drift near the edge of the depletionregion and the other is due to electron-holepair generation in the depletion region of

the reverse-bias junction.


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I1 PN Reverse-Bias Current

I2 Weak Inversion

I3 Drain-Induced Barrier-Lowering Effect I4 Gate-Induced Drain Leakage

I5 Punchthrough

I6 Narrow-Width Effect I7 Gate Oxide Tunneling

I8 Hot-Carrier Injection


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Comparison of process

technologiesm VDD Tox() VT Leff Ioff

(pA/m)

1.0 5 200 0.80 0.000410.8 5 150 0.60 0.55 0.058

0.6 3.3 80 0.58 0.35 0.15

0.35 2.5 60 0.47 0.25 8.9

0.25 1.8 45 0.43 0.15 24

0.18 1.6 30 0.40 0.10 86


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Drain-induced barrier-lowering

effect Drain-induced barrier lowering (DIBL) occurswhen the depletion region of the drain interactswith the source near the channel surface to lowerthe source potential barrier.

The source then injects carriers into the channelsurface without the gate playing a role.

Higher surface and channel doping and shallowsource/drain junction depths reduce the DISLleakage current mechanism.

DIBL can be measured at constant VG as the

change in ID for a change in VD.


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Gate-Induced Drain Leakage

Gate induced drain leakage current arises in thehigh electric field under the gate/drain overlap

region causing deep depletion. GIDL occurs at low VG and high VD bias andgenerates carriers into the substrate and drain fromsurface traps or band-to-band tunneling.

Thinner tox, higher VDD, and LDD (lightly dopeddrain) structures enhance the electric-field-dependent GIDL.


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Punchthrough

Punchthrough occurs when the drain andsource depletion region approach each other

and electrically touch deep in the channel. Punchthrough is regarded as a subsurface

version of DIBL.


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Minimum and maximum leakage

currentcircuit min maxHSPICE GA Diff(%) HSPCIE GA Diff(%)

3-inputNAND

0.022 0.021 4.5 0.492 0.485 1.4

Full adder 1.818 1.909 5.0 2.220 2.281 2.7

2-bitMultiplier

1.842 1.894 2.8 3.049 3.055 0.2


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5.4 Deep Submicrometer Device

Design Issues


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b1 long channel


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In order to make the device work properly,dVth/dL cannot be too large. This will

determine the minimum channel length Lmin.


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Drain-Induced Barrier Lowering


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5.5 Key to Minimizing short-

channel-effect (SCE)


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The small SCE of this transistor is because ofthe smaller depletion depth and junction depth.


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The effective junction depth and the depletionwidth are reduced to half of that of a bulk

MOSFET.


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5.6 Low-Voltage Circuit Design

Techniques


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5.6.3 Multiple Threshold Voltage

Different threshold voltage can bedeveloped by multiple Vth implantation

during the fabrication, by changing thesubstrate and source bias (body effect), bycontrolling the back gate of double-gate

SOI devices.


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When the leakage current is higher than acertain value, the Self-Sub-Bias will be

triggered and will reduce the substrate biasof all the other nMOSFETs, which in turnwill increase the threshold voltage and

reduce the leakage current.


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MTCMOS Multithreshold CMOS uses both high- and low-threshold voltage MOSFETs in a single chip and a sleep

control scheme is introduced for efficient power management.


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The gate and substrate of the

transistors are tied together.


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Because of the body effect, the threshold voltage ofMOSFETs can be changed dynamically during thedifferent mode of operation.

In the active mode, the circuit switches from low to highwith a higher speed because of the low-Vth PMOS. In the standby mode, the static leakage current is decided

by the subthreshold current of the high-Vth nMOS and issmaller.

The supply voltage of DTMOS is limited by the diodebuilt-in potential. The pn-junction diode between sourceand body should not be forward biased. So this techniqueis only suitable for ultra-low-voltage (0.6-V and below)circuits.


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DGDT SOI MOSFETs combine the advantages of DTMOSsand Fully depleted (FD) SOI MOSFETs without the

limitation of the supply voltage.


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The back-gate oxide of DGDT SOIMOSFETs is thick enough to make the

threshold voltage of the back gate largerthan the supply voltage.

The front gate is a conducting gate while

the back gate acts as a controlling gate forthe front gate.


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DGDT shows better subthreshold

characteristics than FD


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The thinner the silicon layer thickness, the smaller is thethreshold voltage. Thinning tob can improve the controllability

of the back gate to the front gate, which increases the

threshold voltage variation range.


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Comparison of Ion/Iofffor different FD SOIMOSFETs and DGDT SOI MOSFETs

Vth Ion/w at 1V(10-5 A/m)

Ioff/w at 1V(10-11 A/m)

Ion/ Ioffat 1V(106)

FDSOI NMOS 0.35 6.12 1.33 4.6

FDSOI PMOS(Vgbs = -1V)

-0.13 -5.54 -6800 0.0008

FDSOI PMOS(Vgb = 0V)

-0.36 -3.46 -0.735 4.7

DGDT SOINMOS

0.13-0.35 10.02 1.33 7.53

DGST SOIPMOS

-0.13-0.36 -5.55 -0.735 7.55


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Good noise margin

Switched source impedance


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Switched source impedanceA switch source impedance is set at the source oftransistor MN. Ss is turned on during the activemode and turned off during the standby mode.


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The sleep control scheme is achieved by a modified DTMOS.The body of high Vth is connected to the gates through a

reverse-biased MOS Diode (MD)


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In sleep mode (VGS = 0V), the drain-current of thevariable high-Vth MOSFET equals that of theconventional MOSFET because the body voltage

is equal to the source voltage of 0V. In active mode (VGS < 0V), the drain-current of

the variable high-Vth MOSFET increases becausethe threshold voltage is reduced due to the body-

voltage reduction. At the supply voltage of 0.5V, the variable high-

Vth MOSFET increases the drain conductance toabout three times that of the conventional

MOSFET.


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5.6.4 Multiple Threshold CMOS

Based on Path Criticality Figure 5.41a is the original single-Vth circuit,where the supply voltage is 1 V and the

threshold voltage is 0.2 V. Figure 5.41 b-dshow the dual-Vth circuits with highthreshold voltages of 0.25, 0.395, and 0.46

V, respectively. The low Vth is 0.2 Vdd.


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Active power dissipations of single-Vth anddual-Vth circuits at different frequencies.


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Optimal high threshold and static

power saving


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Since power dissipation decreasesquadratically with the scaling of supplyvoltage, while the delay is proportional toVdd/(VddVth)2, it is possible to use highsupply voltage in the critical paths of adesign to achieve the required performance

while the off-critical paths of the design uselower supply voltage to achieve low-powerdissipation.

5.8 Multiple Supply Voltages


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Data flow graph


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Lowering dynamic power

Reducing VDD has a quadratic effect Has a negative effect on performance especially as VDD

approaches 2VT Lowering CL

Improves performance as well Keep transistors minimum size (keeps intrinsic capacitance,

gate and diffusion, small) Transistors should be sized only when CL is dominated by

extrinsic capacitance Reducing the switching activity, f01 = P 01 * f

A function of signal statistics and clock rate Impacted by logic and architecture design decisions


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TSMC processes leakage and VtCL018

G

CL018

LP

CL018ULP

CL018

HS

CL015

HS

CL013

HS

Vdd 1.8 1.8 1.8 2 1.5 1.2

Tox 42 42 42 42 29 24Idsat(A/m) 600/200 500/180 320/130 780/360 860/370 920/400

Ioff(pA/m) 20 1.60 0.15 300 1,800 13,000

Lgatem 0.16 0.16 0.18 0.13 0.11 0.08Vt 0.42 0.63 0.73 0.40 0.29 0.25

FET (GHz) 30 22 14 43 52 80

B i i i l f l


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Basic principles of low power

design P = CLVDD2f01 + tscVDDI peakf01 + VDDI leakage Reduce switching (supply) voltage

Quadratic effect dramatic savings Negative effect on performance

Reduce capacitance Reduce switching frequency

Switching activity Clock rate

Reduce glitching Reduce short circuit currents (slope engineering)

Reduce leakage currents


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Impacts of copper interconnect

Wire delay is proportional to its R (resistance)times C (capacitance), thus reducing C reducessignal delay, improves signal integrity and lowers

power consumption Unfortunately as processes shrink, wires get

shorter (reducing C) but they get closer together(increasing C) and narrower (increasing R). So RC

wire delay increases and capacitive coupling getsworse. Copper has about 40% lower resistivity than

aluminum, so copper wires can be thinner

(reducing C) without increasing R


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New technologies - SOI

Scaling of bulk CMOS below 0.13 micron isextremely difficult due to short-channel effects As transistor channel length shrinks, parasitic factors

become dominate Loss of gate control (and transistor gain)

High gate-overlap capacitance

Subthreshold leakage

Tunneling Silicon on Insulator (SOI)

5.low power circuit

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