6-3 testing an mcm for high energy physics experiments...1999 international test conference testing...

1999 International Test Conference1999 International Test Conference

Testing an MCM for High Energy Physics Experiments: a case studyTesting an MCM for High Energy Testing an MCM for High Energy

Physics Experiments: a case studyPhysics Experiments: a case study

Politecnico di Torino, Dip. Automatica e InformaticaPolitecnico di Torino, Dip. Automatica e InformaticaTorino, ItalyTorino, Italy

Alfredo BensoAlfredo Benso Silvia ChiusanoSilvia ChiusanoPaolo PrinettoPaolo Prinetto

CaenCaen MicroelettronicaMicroelettronica -- ViareggioViareggio, Italy, Italy

Simone Simone GiovannettiGiovannetti Riccardo MarianiRiccardo MarianiSilvano MottoSilvano Motto

PurposePurpose

To present the different test strategies To present the different test strategies adopted in the design of an MCM for high adopted in the design of an MCM for high energy physics experimentsenergy physics experiments

OutlineOutline

The ECAL systemThe ECAL system

Testing the MCMTesting the MCM

Test StrategiesTest Strategies

Test Access MechanismsTest Access Mechanisms

ConclusionsConclusions

The ECAL SystemThe ECAL SystemThe ECAL System

.................10 modules / super-module

= 8 super modules

80,000 Optical Fibers

40 towers / module= 80 modules.................

5 MCMs / tower= 3,200 towers.................

5 Input Optical Fibers / MCM = 16,000 MCMs.................

Tower (Board) levelTower (Board) level5 Optical Inputs5 Optical Inputs

FPGAFPGAFPGA

MCMMCMMCM MCMMCMMCM MCMMCMMCM MCMMCMMCMMCMMCMMCM

Spare LogicSpare LogicSpare Logic

FPGAFPGAFPGA

MCMMCMMCM

MCMMCMMCM

MCMMCMMCM

MCMMCMMCM

MCMMCMMCM


MCM levelMCM level

MCM

LIN-PIPE ASIC

LIN PIPE DER

LVL2LVL2ASICASIC

ADDERADDERASICASIC

LVL1LVL1ASICASIC

LIN-PIPE ASIC

LIN PIPE DER

LIN-PIPE ASIC

LIN PIPE DER

LIN-PIPE ASIC

LIN PIPE DER

LIN-PIPE ASIC

LINLIN PIPEPIPE DERDER

Hierarchy

Crate

Board

MCM

Die

EOP Bootstrap In-field In-fieldoff-line on-line

Driving ConstraintsDriving ConstraintsBIST

&DFT

Testing the MCMTesting the MCMTesting the MCM

LifeCycle

Test strategyTest strategyTest strategy

The complete test strategy can be The complete test strategy can be summarized in the following phases:summarized in the following phases:

Identity checkIdentity checkBoardBoard--level interconnect testlevel interconnect testMCMMCM--level interconnect testlevel interconnect testMCMMCM--level structural testlevel structural testChipChip--level testlevel testOnOn--line testline test

Boundary ScanBoundary ScanBoundary ScanBoundary Scan

Boundary ScanBoundary Scan

Circular BISTCircular BIST

OffOff--line BISTline BISTOnOn--line BISTline BIST


Reusable BS logic for both Board and MCMReusable BS logic for both Board and MCM--level interconnect test level interconnect test [Jarwala,[Jarwala,‘‘97]97]

MCM

BoardBoard--level configurationlevel configurationMCM

MCMMCM--level configurationlevel configuration


The complete test strategy can beThe complete test strategy can besummarized in the following phases:summarized in the following phases:

Identity checkIdentity checkBoard-level interconnect testBoard-level interconnect testMCM-level interconnect testMCM-level interconnect testMCM-level structural testMCM-level structural testChip-level testChip-level testOn-line testOn-line test




Off-line BISTOff-line BISTOn-line BISTOn-line BIST








MCM

LIN-PIPE ASIC

LIN PIPE DERLVL2ASICLIN-PIPE ASIC

LIN PIPE DER

LIN-PIPE ASIC

LIN PIPE DER

LIN-PIPE ASIC

LIN PIPE DER

LIN-PIPE ASIC

LIN PIPE DER

RAMRAM

ArithArith PIPEPIPE EvEv. . BufBuf

Serial Serial InterfaceInterface

Control Control LogicLogic


LINLIN PiDEPiDE LPDLPD

RAMRAM

ArithArith PIPEPIPE EvEv. . BufBuf

LINLIN PiDEPiDE

TTPPGG

BIST BIST CTRLCTRL

==TTPPGG Control Control

LogicLogicSerial Serial

InterfaceInterface

LPDLPD

Memory BIST structuresMemory BIST structures









ArithArith PIPEPIPE EvEv. . BufBufTTPPGG

BIST BIST CTRLCTRL



InterfaceInterface

Memory BIST phase #1Memory BIST phase #1


RAMRAM









ArithArith EvEv. . BufBufTTPPGG

BIST BIST CTRLCTRL



InterfaceInterface



RAMRAM

PIPEPIPE









ArithArithTTPPGG

BIST BIST CTRLCTRL



InterfaceInterface



RAMRAM

PIPEPIPE EvEv. . BufBuf









Circular BIST structuresCircular BIST structures

Flip-flop

⊕Flip-flop

Normal Input

0

S0 S1








All the All the FFsFFs transformed in CBIST cells transformed in CBIST cells and connected in a single CBIST chainand connected in a single CBIST chain

MCM

LIN-PIPE ASIC

LIN PIPE DER

LVL2LVL2ASICASICLIN-PIPE ASIC

LIN PIPE DER

LIN-PIPE ASIC

LIN PIPE DER

LIN-PIPE ASIC

LIN PIPE DER

LIN-PIPE ASIC

LIN PIPE DER

LPD chip redundancy exploited for LPD chip redundancy exploited for signature checkingsignature checking

CBIST Flip flop

= Signature comparator

Ref. in Ref. out=LPD

= LPD= LPD

CBIST Signature Checking

= LPD

Circular BIST test flowCircular BIST test flow

InitializationInitialization phasephase: the CBIST chains are : the CBIST chains are initialized with all initialized with all ““00””

BIST phaseBIST phase: a given # of clock cycles is : a given # of clock cycles is appliedapplied

Signature checking phaseSignature checking phase: the contents of : the contents of the CBIST chains are comparedthe CBIST chains are compared

CBIST second phaseCBIST second phase: the flow is repeated : the flow is repeated initializing the CBIST chains with all initializing the CBIST chains with all ““11””

CBIST Fault CoverageCBIST Fault Coverage

0,0010,0020,0030,0040,0050,0060,0070,0080,0090,00

100,00

1 2001 4001 6001 8001 10001 12001 14001

Clock cycles

FC %

CBIST second phase

Preliminary experimental resultsPreliminary experimental results

Test area overhead:Test area overhead:

10% 10% -- 15% with not optimized CBIST cells15% with not optimized CBIST cells4% 4% -- 5% with optimized CBIST cells5% with optimized CBIST cells

CBIST Fault Coverage:CBIST Fault Coverage:

93% with 10,000 cycles93% with 10,000 cycles

OnOn--line memory BISTline memory BIST

Detects transient faults Detects transient faults (e.g., SEU) (e.g., SEU)

RAMData in

Data Out

Data out

PG

kWAdd (7:0)

Data In

K+1

K+1

8

PG

K

RAdd (7:0)

Error

8k

=

1

1

1

Based on information Based on information redundancy (parity bit)redundancy (parity bit)

Covers faults in the Covers faults in the addressing logic, as welladdressing logic, as well








OnOn--line arithmetic checksline arithmetic checks

Based on arithmetic codesBased on arithmetic codes

Detects faults in the results of the computationDetects faults in the results of the computation

RegisteredRegisteredALUALU

Unit /3Unit /3 ==

/3/3/3/3

Error flag








Test Access MechanismsTest Access MechanismsTest Access Mechanisms

Board level:Board level:

FPGAFPGA already present on board. already present on board. It controls the It controls the TAM of each MTAM of each MCMCM

FPGAFPGAFPGA



Test Access MechanismsTest Access Mechanisms

MCM level:MCM level:

FPGAFPGAFPGA


MCMMCM

BIST CtrlBIST Ctrl


SerialSerialInterfaceInterface

a a Serial InterfaceSerial Interface (directly controlling a (directly controlling a Test Access Register)Test Access Register)

TAPTAP

TAPTAP (through custom BS instructions)(through custom BS instructions)

ConclusionsConclusionsConclusions

High fault coverage of both High fault coverage of both permanentpermanent and and transienttransient faultsfaults through different BIST and through different BIST and DFT techniquesDFT techniques

Optimized use of the chip redundancy to Optimized use of the chip redundancy to implement an effective implement an effective CBIST schemeCBIST scheme

Different Different Test Access MechanismsTest Access Mechanismsimplemented to increase flexibility.implemented to increase flexibility.

6-3 testing an mcm for high energy physics experiments...1999 international test conference testing...

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