6 february 2014 design at the top of the semiconductor foodchain: how manufacturing challenges...

April 10, 2023

www.c2s2.org

Design at the Top of the Semiconductor Foodchain:

How Manufacturing Challenges Below

90nm Impact Circuits & Systems

Design at the Top of the Semiconductor Foodchain:

How Manufacturing Challenges Below

90nm Impact Circuits & Systems

Rob A. Rutenbar Director, MARCO Center for Circuit & System Solutions

Professor of ECE, Carnegie [email protected]

April 10, 2023 Slide 2

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About This TalkAbout This Talk

Some background on the MARCO FCRP program What all these acronyms are… …and why you might want to know about them

A brief look at work in the C2S2 “Circuits” Center How mfg challenges at highly scaled nodes percolate up to the foodchain What causes circuit designers nightmares, and what we’re doing about it.


http://www.c2s2.org

www.c2s2.org

C2S2, MARCO, FCRP, etc:A Little Bit of Background and ContextC2S2, MARCO, FCRP, etc:A Little Bit of Background and Context

MARCO


http://www.c2s2.org

www.c2s2.org

The focus center program is designed to create a nationwide multi-university network of research centers that will keep the United States and U.S. semiconductor firms at the front of the global microelectronics revolution.”

FCRP: Focus Center Research ProgramFCRP: Focus Center Research Program

Vision: National research centers in semiconductor technology Multiple-university teams & large-scale efforts (~$10M/center/year) Long-range research horizon Focus on discovery: where evolutionary R&D may not find solutions

Craig R. Barrett President and CEO, Intel; (Former) Chair, Semiconductor Technology Council


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www.c2s2.org

Focus Center Research Program: TimelineFocus Center Research Program: TimelineFirst centers chartered in 1999; five centers in operation todayTotal program currently ~$25M/year

1999 2001 2003 2004Aug

recompete

restart

“Systems”

“Interconnect”

“Circuits”

“Devices”

“Materials”


http://www.c2s2.org

www.c2s2.org

MARCO: Microelectronics Advanced Research Corp.MARCO: Microelectronics Advanced Research Corp.

MARCO coordinates FCRP Centers, funding, industry/govt interfaces

Centers

Funding

MARCOGoverning

CouncilManagement

Universities . . .~30 schools

US DOD


http://www.c2s2.org

www.c2s2.org

systems

structures

materials

physics

FCRP Centers: Designed To Target Entire “Semiconductor Foodchain”FCRP Centers: Designed To Target Entire “Semiconductor Foodchain”

physicsphysics

structuresstructures

materialsmaterials

devicesdevices

circuitscircuits

logic / architecturelogic / architecture

system softwaresystem software

application HW/SWapplication HW/SW

integrated productsintegrated products

Pushing CMOS to its limits—and beyond

Containing the growing cost of complexity

Driving down cost of design & verification

Containing latency & power of interconnect

Overcoming the tyranny of KT/q


http://www.c2s2.org

www.c2s2.org

systemssystems


materialsmaterials

physicsphysicsphysicsphysics


materialsmaterials




C2S2: Center for Circuit & System SolutionsC2S2: Center for Circuit & System Solutions

C2S2 core competency: Circuits Technology scaling impacts Analog, digital, RF, MEMS ckts Some photonics, too Assoc. design tools & methodologies

Logistics CMU is lead school Now 12 universities ~47** faculty, 67 grad students

devicesdevices

circuitscircuits



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www.c2s2.org

The C2S2 Research TeamThe C2S2 Research Team

Executive team

Research team

Rob RutenbarCMU, Director

Bob BrodersenBerkeley

Mark HorowitzStanford

Wen-Mei HwuIllinois

Larry PileggiCMU

Teresa MengStanford

Charles SodiniMIT

U. WashingtonStanford

U.C. BerkeleyU.C. San Diego

UCLA

Columbia U.Cornell U.MITCarnegie Mellon (Lead)U IllinoisGeorgia TechU Florida

Art DavidsonCMU, Exec Dir


http://www.c2s2.org

www.c2s2.org

devicesdevices

circuitscircuits


systemssystems


materialsmaterials



materialsmaterials




C2S2: Doing Circuits in Highly Scaled TechnologiesC2S2: Doing Circuits in Highly Scaled Technologies

How will we do circuit design with tomorrow’s different, difficult devices?

‘95 ‘00 ‘05 ‘10 ‘15 ‘20

1m

100nm

10nm

1nm

Gate Length

drawn

physical

Coping with scaling


http://www.c2s2.org

www.c2s2.org

…and, how do we deal withthe “conscientious objectors”…?

…and, how do we deal withthe “conscientious objectors”…?


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www.c2s2.org

systemssystems


materialsmaterials



materialsmaterials




C2S2: Doing “Reluctant” Circuits at Scaled NodesC2S2: Doing “Reluctant” Circuits at Scaled Nodes

How will we approach circuits that don’t want to scale?

Circuits that prefer—for $$, or for performance—a different technology platform?

10nm10nm

-+

devicesdevices

circuitscircuits

logic / architecturelogic / architecture(nm)

V

V

V

V

Vdigital

analog rangeITRS-03 Vsupply


http://www.c2s2.org

www.c2s2.org

About This TalkAbout This Talk

Some background on the MARCO FCRP program What all these acronyms are… …and why you might want to know about them

A brief look at work in the C2S2 “Circuits” Center How mfg challenges at highly scaled nodes percolate up to the foodchain What causes circuit designers nightmares, and what we’re doing about it.

BOXBOX

BOX


http://www.c2s2.org

www.c2s2.org

Two Different Scaling-Related ProblemsTwo Different Scaling-Related Problems

What about delay?

Past expectation Next process node is faster We rely on this for new designs

New problems Yes, it’s faster… Chip-scale, size of logic hurts Speed of light is a big limiter

What about mfg variability?

Past expectation Next process node is worse

…but we’re smart, we’ll manage

New problems It’s a lot worse than the last node Cannot pretend it’s deterministic Cannot just look at a few “corners”


http://www.c2s2.org

www.c2s2.org

View from the “Top” – Circuits & SystemsView from the “Top” – Circuits & Systems

Fundamental circuits

Basic blocks Vin+ Vin-M2

Vss

Vdd

M9

M11

M7

M5

M8

M10

M4

Vout+Vout–

M17 M16 M15 M14

M6

M19

M1

Vcm

Vout+

M3

Vb2

M12M13

Vb1

M18

Vb3

Architectures

Materials & structures

Systems

Devices & wires

What’s happening with circuits & systemswith CAD & methodologyto help design inscaled technologies?


http://www.c2s2.org

www.c2s2.org

Let’s Look at Delay…Let’s Look at Delay…

Unfortunate fact: despite a century of physics funding

… “c” has not budged —not even 1 m/s !

~6 ps~6 ps

~6 ps~6 ps


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www.c2s2.org

Delay: Two Different Flavors for WiresDelay: Two Different Flavors for Wires

Global wires~ constant length

Local wires~ constant complexity,span constant # gates

scale

Local wiresGet shorter with scaling

Global wiresDon’t get shorter with scaling(that’s why they’re global…)


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www.c2s2.org

Delay: Global Wire TrendsDelay: Global Wire Trends

Optimally buffered global wires that span 5mm (roughly ¼ die)

30x-40x delay penalty over nine process generations

Cannot contract global communications (they're global…)

Mid-layer metals30x delay increase

Upper-layer metals40x delay increase

CourtesyMark Horowitz& Ron Ho, Stanford


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www.c2s2.org

0.01

0.10

1.00

85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02

intel 386

intel 486

intel pentium

intel pentium 2

intel pentium 3

intel pentium 4

intel itanium

Alpha 21064

Alpha 21164

Alpha 21264

Sparc

SuperSparc

Sparc64

Mips

HP PA

Power PC

AMD K6

AMD K7

Consequence: More MHz Not Necessarily Better AnymoreConsequence: More MHz Not Necessarily Better Anymore

This is SpecInt/MHz, a measure of CPU performance / clock speed

Curve is flattening, more MHzisn’t paying off anymore…

Courtesy Mark Horowitz, Stanford


http://www.c2s2.org

www.c2s2.org

Consequence: 1 Chip 1 CPU Going ForwardConsequence: 1 Chip 1 CPU Going Forward

Recent big Intel news:

No more single-core CPUs

Two high-profile designs abruptly canceled

Future is multiple CPUs on a single chip

“Intel Corp. has cancelled its single-core processor development efforts… and will move to dual-

core designs across the mobile, desktop, and

server markets…”


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www.c2s2.org

Idea: More CPUs Instead of More MHzIdea: More CPUs Instead of More MHz

CPU

Global wiresBad even with bufferingor multi-cycle delays

Local wiresStill OK, still manageable

scale

Make most of the wires localCan still clock a small CPU fastUse parallelism smarter

CPU CPU CPU CPU

CPU CPU CPU CPU

Memory


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www.c2s2.org

Next Problem: Manufacturing VariabilityNext Problem: Manufacturing Variability

Problems in mirror arecloser than they appear


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www.c2s2.org

Manufacturing Variability: A Little HistoryManufacturing Variability: A Little History

Historically, how have we coped? By hiding as much as possible

Behind logic/memory libraries

Behind circuit and shapes rules

Behind design methodologies

Library abstractionsQualification & characterization

Design rules…

DigitalHDL

LogicalSynthesis

PhysicalSynthesis


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www.c2s2.org

At Nanoscale: Predictability (Chip Variability)-

1At Nanoscale: Predictability (Chip Variability)-

1

ASIC library abstraction broken:doesn’t “hide” the details anymore

as we scale below ~65nm

Defocuseffect

Defocuseffect

Exposure variation Resist effect

(shrinks)(grows)

Local printability problems

Cu thickness distrib

Cu thickness histogram

Global effects

Demise of context-freelayout design rules

Correlated randomvariations hit ckt level


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www.c2s2.org

So, How Do We Cope With Growing Variability?So, How Do We Cope With Growing Variability?

Three broad kinds of solutions

Model it accurately, manage it early, inside CAD tools

Minimize it aggressively, via smarter ASIC chip architectures

Measure it on the fly, calibrate for it—like analog has had to do


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www.c2s2.org

“Model It”: Pulling Statistics Up into CAD“Model It”: Pulling Statistics Up into CAD

Statistical interconnect delay analysis R, L, C parameters are statistical

Based on mfg variations in BEOL fab R, L, C parameters are correlated

Correlations are both local and global

Want distribution of delay at outputs

Statistical static timing analysis Gate delays are statistical

Signal arrival times are statistical

Gates and signals are correlated

Correlations are both local and global

Want distribution of delay at output


http://www.c2s2.org

www.c2s2.org

Key Ideas: Direct Manipulation of the StatisticsKey Ideas: Direct Manipulation of the Statistics Wrong way: Monte Carlo trials

with existing CAD analysis tools Cannot afford time to run 1000s of

randomly parameterized samples

Right way: pull the statistics up directly into the analysis engines Represent key circuit/interconnect

quantities in a statistical form

1

2

N

/ N


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www.c2s2.org

Example: Interval-Valued Interconnect ModelsExample: Interval-Valued Interconnect Models

Each parameteris a range, nota scalar now

1. Represent all statistical quantities as correlated intervals

zeros poles

2. Recast the numerical ‘recipes’ for linear model order reduction to use intervals instead of scalars

Delay

%

4. Transform back to delay distrib

Root loci “histograms”

Pole/zero complex plane

3. Result is interval poles/zeros


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www.c2s2.org

Ex: 123-elem RLC Wire, 5%-Global 30%-Local VariationEx: 123-elem RLC Wire, 5%-Global 30%-Local Variation

Courtesy James D. Ma, CMU

8th order reduction, 4 dominant polesMonte Carlo results

8th order reduction, 4 dominant polesInterval-valued predictions

Plots show perspective view of complex plane (bottom & right axes)with pole histograms shown shaded blue (left axis, 10,000 interconnect samples)


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Delay PDF and CDF of the Same Example Delay PDF and CDF of the Same Example

Very early research result—but accuracy is promising, and speedup is currently ~20X over simplistic Monte Carlo

Courtesy James D. Ma, CMU

PDF: RLCline AWE

0.0%

5.0%

10.0%

15.0%

20.0%

25.0%

30.0%

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

delay (*40ps)

full_MC

AApoles/residues_MC

CDF: RLC line AWE

0.0%

20.0%

40.0%

60.0%

80.0%

100.0%

120.0%

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

delay (*40ps)

full_MCAApoles/residues_MC

PDF of Interconnect Delay CDF of Interconnect Delay

Full Monte Carlo

Interval-valued predictor

Interval-valued predictor

Full Monte Carlo


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www.c2s2.org

“Minimize It” Attack: Make Variability Small…“Minimize It” Attack: Make Variability Small…

Starting from basic mfg processes, from shapes-level layout, thru circuits, thru logic, thru interconnect arch: extremely regular Tries to minimize impact of short, medium, long range mfg variations Of course, it also breaks all our design tools and flows, too…

Or, maybe this pattern…?A “regular fabric” for tomorrowYesterday’s designs


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Example: CMU VPGA ArchitectureExample: CMU VPGA Architecture

Via Patterned Gate Array Uses only 4 masks to define total

application-specific interconnect Logic tiles, and the interconnect,

are totally regularized chip-wide Like “gate array” but better, and

informed by ~20 years of FPGAs

Example: Replace FPGA switchblock of 36-120

devices with 8 mask-config vias

Goal Minimize variations (eg, CMP) at all

length scales on chip

Make logic and interconnect very predictable for designers

Cu thickness distribution


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www.c2s2.org

Example: Manufacturability of VPGA BEOLExample: Manufacturability of VPGA BEOL

Reduced CMP effects Copper dishing < 40Å Post-CMP Copper

thickness variation is less than 2-3%

Highly promising as a manufacturable ASIC replacement structure

M4 Density of CMU VPGA FPU

Courtesy Duane Boning (MIT) & Larry Pileggi (CMU)

Cu Dishing (M4) Final Post-CMP Cu Thickness (M4)

Plated Thickness (M4) Oxide Erosion (M4)


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www.c2s2.org

“Measure It”: Circuits to Measure & Adapt“Measure It”: Circuits to Measure & Adapt

With scaling, not only are transistors getting worse, … but the neighborhoods they live in getting noisier

What we worry about Behavior of chip-scale interconnects like clock and power distribution Ability to predict worst-case behavior for robust design Ability to understand data-driven noise problems, and to reduce them

Big idea Some things you can just design for “up front” Increasingly, we may need to add circuits that measure & adapt on the fly


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www.c2s2.org

Ex: Supply Noise Measurement CircuitsEx: Supply Noise Measurement Circuits To measure autocorrelation, just need

2 samplers with fine timing control. Sampling switches are only component

required to have high bandwidth. High-resolution, on-chip ADC’s to minimize

additional noise and allow measurement circuits to hook up to scan chain.

Vdd

Vdd

2 SamplersSampler Timing

Generator

A/D Converters

Digital Outputsfor post-processing

VCO-based ADC VCO acts as V-to-f, clock edge count gives

digital estimate of f. Averaging improves noise tolerance. Calibration relaxes linearity and offset

requirements.

VddQ

+

-

Buffer

VCO

Samp

Counter

Cnt_clk

Vdd

VddA

Samp

VddQ

Samp

VddQ

Sel_Vdd

VddQ

VddQ

Sel_VddA


http://www.c2s2.org

www.c2s2.org

Result: 10Gb/s Rambus Link MeasurementResult: 10Gb/s Rambus Link Measurement Rambus 0.13 design

Demonstration of concept Noise floor < 300V rms Measured Vdd and VddAnalog

Measurements verify cyclostationarity: 1GHz noise at t2 – but not at t1! Link runs at 1GHz for this data-rate;

high link activity at t2, relatively quiet at t1.

10MHz 100MHz 1GHz 10GHz-100

-80

-60

-40

-20

0

Frequency

PS

D (

dB

V)


-80

-60

-40

-20

0

Frequency

PS

D (

dB

V)

Noise floor Noise floor

Vdd

noise V

ddA noise

Noise injected from ASIC core


-60

-50

-40

-30

-20

-10

Frequency

PS

D (

dB

V)


-60

-50

-40

-30

-20

-10

Frequency

PS

D (

dB

V)

PSD(t1) PSD(t2)

This is still 130nm—but we think idea holds as we scale aggressivelyWe also put some of these ckts on a next-gen Itanium™ chip

(Courtesy E. Alon, V. Stojanovic, Mark Horowitz, Stanford)


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www.c2s2.org

Analog Too: Calibrate & Adapt (…or Die)Analog Too: Calibrate & Adapt (…or Die) Example: Massively parallel ADCs

Thousands of small ADCs DSP combines data adaptively Ignore (give low weight) to faulty ckts

Idea: Massive time-interleaving Relaxes speed req’t of each path Allows device bias in the optimum

power efficiency/gain region… …at the knee of weak inversion.

In design: 12b 600 MS/s self-calibrated ADC in 0.18 m, 128 channels – 100mW

Next: 8b 20GS/s with 1000 channels

Looks promising as a scalable ADCarchitecture for below 90nm

(Courtesy H-S Lee, MIT)


http://www.c2s2.org

www.c2s2.org

Summary: FCRP Innovating Across Whole FoodchainSummary: FCRP Innovating Across Whole Foodchain

Exotic interconnect

Novel devices

Radical architectures

Radical new ckts / tools


http://www.c2s2.org

www.c2s2.org

A Lot More Work To Do At “Top” of FoodchainA Lot More Work To Do At “Top” of Foodchain

(No shortage of problems, even up here, in the clouds)

New system architectures For CPUs and for ASICs, to overcome wire delay & mfg variation limitations

New circuits & design methodologies CAD tools that understand and optimize statistical models of interconnect Circuits that measure interconnect problems and try to adapt to them


http://www.c2s2.org

www.c2s2.org

AcknowledgementsAcknowledgements

Many participants in the MARCO Focus Center for Circuit & System Solutions (C2S2) provided material for this talk

I want to acknowledge them here

More info on all these projects at

www.fcrp.org

www.c2s2.org

Carnegie Mellon Prof. Larry Pileggi Prof. Andrzej Strojwas James D. Ma

MIT Prof. Duane Boning Prof. H.-S. Harry Lee

Stanford Prof. Mark Horowitz E. Alon Ron Ho V. Stojanovic

6 february 2014 design at the top of the semiconductor foodchain: how manufacturing challenges...

Documents

scaling slide

supply slide

context slide

corners slide

exec dir slide

tyranny of ktq slide

c2s2 circuits center

reluctant circuits