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1

A Modified Three-phase Four Wire UPQCTopology with Reduced DC-link Voltage Rating

Srinivas Bhaskar Karanki, Nagesh Geddada, Student Member, IEEE, Mahesh K. Mishra, Senior Member, IEEE,B. Kalyan Kumar, Member, IEEE

Abstract—The Unified Power Quality Conditioner (UPQC) is acustom power device, which mitigates voltage and current relatedpower quality issues in the power distribution systems. In thispaper, an UPQC topology for applications with non-stiff sourceis proposed. The proposed topology enables UPQC to have areduced DC-link voltage without compromising its compensationcapability. This proposed topology also helps to match the DC-link voltage requirement of the shunt and series active filtersof the UPQC. The topology uses a capacitor in series with theinterfacing inductor of the shunt active filter and the systemneutral is connected to the negative terminal of the DC-linkvoltage to avoid the requirement of the fourth leg in the VoltageSource Inverter (VSI) of the shunt active filter. The averageswitching frequency of the switches in the VSI also reduces,consequently the switching losses in the inverters reduce. Detaileddesign aspects of the series capacitor and VSI parameters havebeen discussed in the paper. A simulation study of the proposedtopology has been carried out using PSCAD simulator and theresults are presented. Experimental studies are carried out onthree-phase UPQC prototype to verify the proposed topology.

Index Terms—Average switching frequency, DC-link Voltage,UPQC, Hybrid topology, Non-stiff source.

I. INTRODUCTION

With the advancement of power electronics and digitalcontrol technology, the renewable energy sources are increas-ingly being connected to the distribution systems. On theother hand, with the proliferation of the power electronicsdevices, non-linear loads and unbalanced loads have degradedthe power quality (PQ) in the power distribution network[1]. Custom power devices have been proposed for enhancingthe quality and reliability of electrical power. Unified PowerQuality Conditioner (UPQC) is a versatile custom powerdevice which consists of two inverters connected back-to-back and deals with both load current and supply voltageimperfections. UPQC can simultaneously perform as shuntand series active power filters. The series part of the UPQCis known as Dynamic Voltage Restorer (DVR). It is used tomaintain balanced, distortion free nominal voltage at the load.The shunt part of the UPQC is known as Distribution STATicCompensator (DSTATCOM) and it is used to compensateload reactive power, harmonics and balance the load currents

Copyright (c) 2009 IEEE. Personal use of this material is permitted.However, permission to use this material for any other purposes must beobtained from the IEEE by sending a request to [email protected].

This work is supported by Department of science and Technology, Indiaunder the project grant SR/S3/EECE/048/2008.

The authors are with the Department of Electrical Engineering, IndianInstitute of Technology Madras, Chennai-36, India.

Email: [email protected], [email protected], [email protected], [email protected].

thereby making the source current balanced and distortion freewith unity power factor.

Voltage rating of DC-link capacitor largely influences thecompensation performance of an active filter [2]. In generalthe DC-link voltage for the shunt active filter has much highervalue than the peak value of the line to neutral voltage. Thisis done in order to ensure a proper compensation at the peakof the source voltage. In [3], the authors mentioned aboutthe current distortion limit and loss of control limit, whichstates that the DC-link voltage should be greater than or equalto√

6 times the phase voltage of the system for distortionfree compensation. When the DC-link voltage is less than thislimit, there is insufficient resultant voltage to drive the currentsthrough the inductances so as to track the reference currents.The primary condition for reactive power compensation is thatthe magnitude of reference DC-bus capacitor voltage shouldbe higher than the peak voltage at the point of commoncoupling (PCC) [4]. Due to the above mentioned criteria,many researchers have used a higher value of DC capacitorvoltage based on applications [5]–[13]. Similarly, for seriesactive filter the DC-link voltage is maintained at a value equalto the peak of the line to line voltage of the system for propercompensation [14]–[18].

In case of the UPQC, the DC-link voltage requirement forthe shunt and series active filters is not the same. Thus, itis challenging task to have a common DC-link of appropri-ate rating in order to achieve satisfactory shunt and seriescompensation. The shunt active filter requires higher DC-link voltage when compared to the series active filter forproper compensation. In order to have a proper compensationfor both series and shunt active filter, the researchers areleft with no choice rather than to select common DC-linkvoltage based on shunt active filter requirement. This willresult in over rating of the series active filter as it requiresless DC-link voltage compared to shunt active filter. Due tothis criterion, in literature, a higher DC-link voltage based onthe UPQC topology has been suggested [19]–[22]. With thehigh value of DC-link capacitor, the Voltage Source Inverters(VSIs) become bulky and the switches used in the VSI alsoneed to be rated for higher value of voltage and current.This in turn increases the entire cost and size of the VSI.To reduce the DC-link voltage storage capacity, few attemptswere made in literature. In [23], [24], a hybrid filter hasbeen discussed for motor drive applications. The filter isconnected in parallel with diode rectifier and tuned at 7thharmonic frequency. Although an elegant work, the design isspecific to the motor drive application and the reactive power



2

compensation is not considered, which is an important aspectin UPQC applications.

In case of the three-phase four wire system, neutral clampedtopology is used for UPQC [25], [26]. This topology enablesthe independent control of each leg of both the shunt andseries inverters, but it requires capacitor voltage balancing[27]. In [21], four leg VSI topology for shunt active filterhas been proposed for three-phase four wire system. Thistopology avoids the voltage balancing of the capacitor, butthe independent control of the inverter legs is not possible. Toovercome the problems associated with the four leg topology,in [28], [29], the authors proposed a T-connected transformerand three-phase VSC based DSTATCOM. However, this topol-ogy increases the cost and bulkiness of the UPQC because ofthe presence of extra transformer.

In this paper, an UPQC topology with reduced DC-linkvoltage is proposed. The topology consists of capacitor inseries with the interfacing inductor of the shunt active filter.The series capacitor enables reduction in DC-link voltagerequirement of the shunt active filter and simultaneouslycompensating the reactive power required by the load, soas to maintain unity power factor, without compromising itsperformance. This allows us to match the DC-link voltagerequirements of the series and shunt active filters with a com-mon DC-link capacitor. Further, in this topology the systemneutral is connected to the negative terminal of the DC bus.This will avoid the requirement of the fourth leg in VSI ofthe shunt active filter and enables independent control of eachleg of the shunt VSI with single DC capacitor. The simulationstudies are carried out using PSCAD simulator and detailedresults are presented in the paper. A prototype of three-phaseUPQC is developed in the laboratory to verify the proposedconcept and the detailed results are presented in this paper.

II. CONVENTIONAL AND PROPOSED TOPOLOGIES OFUPQC

In this section, the conventional and proposed topologyof the UPQC are discussed in detail. Figure 1 shows thepower circuit of the neutral clamped VSI topology basedUPQC which is considered as the conventional topology inthis study. Even though this topology requires two DC storagedevices, each leg of the VSI can be controlled independentlyand tracking is smooth with less number of switches whencompared to other VSI topologies [27]. In this figure, vsa, vsb

and vsc are source voltages of phases a, b and c, respectively.Similarly, vta, vtb and vtc are terminal voltages . The voltagesvdvra, vdvrb and vdvrc are injected by the series active filter.The three-phase source currents are represented by isa, isb

and isc, load currents are represented by ila, ilb and ilc.The shunt active filter currents are denoted by ifa, ifb, ifc

and iln represents the current in the neutral leg. Ls and Rs

represent the feeder inductance and resistance, respectively.The interfacing inductance and resistance of the shunt activefilter are represented by Lf and Rf respectively and theinterfacing inductance and filter capacitor of the series activefilter are represented by Lse and Cse respectively. The loadconstituted of both linear and nonlinear loads as shown in this

figure. The DC-link capacitors and voltages across them arerepresented by Cdc1 = Cdc2 = Cdc and Vdc1 = Vdc2 = Vdc,respectively and the total DC-link voltage is represented byVdbus (Vdc1 +Vdc2 = 2Vdc). In this conventional topology, thevoltage across each common DC-link capacitor is chosen as1.6 times the peak value of the source voltages as given in[27].

Figure 2 represents the equivalent circuit of the proposedVSI topology for UPQC compensated system. In this topologythe system neutral has been connected to the negative terminalof the DC bus along with the capacitor Cf in series with theinterfacing inductance of the shunt active filter. This topologyis referred to as modified topology. The passive capacitorCf has the capability to supply a part of the reactive powerrequired by the load and the active filter will compensatethe balance reactive power and the harmonics present in theload. The addition of capacitor in series with the interfacinginductor of the shunt active filter will significantly reduce theDC-link voltage requirement and consequently reduces theaverage switching frequency of the switches. This conceptwill be illustrated with analytic description in the followingsection. The reduction in the DC-link voltage requirement ofthe shunt active filter enables us to the match the DC-linkvoltage requirement with the series active filter. This topologyavoids the over rating of the series active filter of the UPQCcompensation system. The design of the series capacitor Cf

and the other VSI parameters have significant effect on theperformance of the compensator. These are given in the nextsection. This topology uses a single DC capacitor unlike theneutral clamped topology and consequently avoids the needof balancing the DC-link voltages. Each leg of the invertercan be controlled independently in shunt active filter. Unlikethe topologies mentioned in the literature [21], [25], [26], [30],this topology does not require the fourth leg in the shunt activefilter for three-phase four wire system. The performance of thistopology will be explained in detailed in the following section.

III. DESIGN OF VSI PARAMETERS

The parameters of the VSI need to be designed carefullyfor better tracking performance. The important parametersthat need to be taken into consideration while designingconventional VSI are Vdc, Cdc, Lf , Lse, Cse and switchingfrequency (fsw). The design details of the VSI parameters forthe shunt and series active filter are given in [31], [32]. Basedon the following equations the parameters of the VSIs arechosen for study.

A. Design of shunt active filter VSI parameters

Consider the active filter is connected to an X kVA systemand deals with 0.5X kVA and 2X kVA handling capabilityunder transient conditions for n cycles. During transient, withan increase in system kVA load, the voltage across eachDC-link capacitor (Vdc) decreases and vice versa. Allowinga maximum of 25% variation in Vdc during transient, thedifferential energy (∆Ec) across Cdc is give by

∆Ec =[Cdc(1.125Vdc)2 − (0.875Vdc)2]

2(1)



3

vsa

vsbN

PCC

Linear load

Non-linear loadRf

Lf

Rf

Lf

Rf

Lf

Sc

S'c

Sa

S'a

Sb

S'b

Vdc

Rs Ls

Rs Ls

Rs Ls

Rla Llailaisa

Rlb Llbilbisb

Rlc Llcilcisc

Rnl

Lnl

vsc

ifbifa ifc

Vdc

'n

n

dcC

dcC

lav

lbv

lcv

Scc

S'cc

Saa

S'aa

Sbb

S'bb

lni

fni

sni Cse Cse Cse

tvdvrav

dvrbv

dvrcv

Lse Lse Lse

Fig. 1. Equivalent circuit of neutral clamped VSI topology based UPQC.

vsa

vsbN

PCC

Linear load

Non-linear loadRf

Lf

Rf

Lf

Rf

Lf

Sc

S'c

Sa

S'a

Sb

S'b

Vdbus

Rs Ls

Rs Ls

Rs Ls

Rla Llailaisa

Rlb Llbilbisb

Rlc Llcilcisc

Rnl

Lnl

vsc

ifbifa ifc

n

dcC

lav

lbv

lcv

Scc

S'cc

Saa

S'aa

Sbb

S'bb

lni

fni

sni Cse Cse Cse

tvdvrav

dvrbv

dvrcv

Lse Lse Lse

Cf Cf Cf

Rsw Rsw Rsw

Fig. 2. Equivalent circuit of proposed VSI topology for UPQC compensated system (Modified Topology).

The change in system energy (∆Es) for a load change from2X kVA to 0.5X kVA is

∆Es = (2X −X/2)nT. (2)

Equating 1 and 2, the DC-link capacitor value is given by

Cdc =2(2X −X/2)nT

(1.125Vdc)2 − (0.875Vdc)2. (3)

where, Vm is the peak value of the source voltage, X is thekVA rating of the system, n is number of cycles and T timeperiod of each cycle. An empirical study has been carried outfor various values of interfacing inductance values with thevariation of the DC-link voltage in [31], with Vdc = mVm

and it is found that m = 1.6 gives fairly good switchingperformance of the VSI. The approximate relationship betweenm and minimum (fswmin), maximum switching frequency(fswmax) is obtained by analysis of the VSI in [31] and this isgiven below. For switching frequency variation approximatelyfrom 6 kHz to 10 kHz, the value of m is 1.58, which is taken

as 1.6 in the study.

m =1√

1− fswmin/fswmax

(4)

Based on this, the shunt interfacing inductance has beenderived taking into consideration of the maximum switchingfrequency and is given below [31]

Lf =mVm

4h1fswmax(5)

where

h1 =

√k1

k2

(2m2 − 1)4m2

fswmax. (6)

Where, h1 is the hysteresis band limit, k1 and k2 are propor-tionality constants.

B. Design of series active filter VSI parametersIn order to make the series active filter system a first order

system, a resistor is added in series with the filter capacitor,referred as switching band resistor (Rsw) [32].



4

The rms value of the capacitor current can be expressedas Ise=

√I2inv − I2

l . Iinv is the series inverter current ratingand Il is the load current. The capacitor branch current isdivided into two components - a fundamental current Ise1,corresponding to the fundamental reference voltage (Vref1)and a switching frequency current Isw, corresponding to theband voltage (Vsw). The DVR voltage and the current of thecapacitor are given by,

Vdvr =√V 2

ref1 + V 2sw

Ise =√I2se1 + I2

sw

Vsw = IswRsw =h2√

3

Vref1 = Ise1Xse1 =Ise1

2πf1Cse

(7)

where h2 is the hysteresis band voltage.The resistance (Rsw) and the capacitance (Cse) values are

expressed in terms of band voltage vsw and rated referencesvoltage (Vref1) respectively and are given by

Rsw =h2

Isw

√3

Cse =Ise1

Vref12πf1

(8)

The interfacing inductor Lse has been designed based onthe switching frequency of the series active filter and is givenby

Lse =(Vbus)Rsw

4fswmaxh2(9)

where Vbus is the total DC-link voltage across both the DC-link capacitors.

A design example is illustrated for a rated voltage of 230 Vline to neutral and the DC-link voltage reference (Vdcref ) ofthe conventional VSI topology has been taken as 1.6 Vm foreach capacitor [27], [31]. The hysteresis band (h1) is taken as0.5 A. From equation (5) the interfacing inductance (Lf ) iscomputed to be 26 mH. The base kVA rating of the systemis taken as 5 kVA. Using equation (3), Cdc is computed andfound to be 2200 µF. The rated series VSI voltage is chosen as50% of the rated voltage i.e. the maximun injection capacityof the series active filter is 115 V . The hystersis band (h2)for series active filter is taken as 3% of the rated voltage i.e6.9 V . The maximun switching frequency of the IGBT basedinverter is taken as 10 kHz. The series active filter currentrating is choosen as 8 A and the rated load current as 7 A.Using the equations (7) to (9), the filter capaciotr Cse, the bandresistor Rsw and interfacing inductance Lse are calcluated tobe 80 µF, 1.5 Ω and 5 mH respectively. The system parametersare given in Table I for the conventional VSI topology.

C. Design of Cf for the proposed VSI topology

The design of the Cf depends upon the value to whichthe DC-link voltage is reduced. In general, loads with only

TABLE ISYSTEM PARAMETERS

System Quantities ValuesSystem voltages 230 V (line to neutral), 50 HzFeeder impedance Zs = 1 + j3.141 ΩLinear Load Zla = 34 + j47.5 Ω, Zlb = 81 + j39.6 Ω,

Zlc = 31.5 + j70.9 ΩNon-linear Load three-phase full bridge rectifier load

feeding a R-L load of 150 Ω-300 mHShunt VSI parameters Cdc = 2200 µF, Lf = 26 mH, Rf = 1 Ω

Vdbus = 2 × Vdc = 1040 V (Conventional),Vdbus = 560 V(Proposed)

Series VSI parameters Cse=80 µF, Lse= 5 mHRsw = 1.5 Ω

Series interfacing 1:1, 100 V and 700 V AtransformerPI controller gains Kp = 6, Ki = 5.5Hysteresis band h1 = ± 0.5 A, h2= ± 6.9 V

non linear components of currents are very rare and most ofthe electrical loads are combination of the linear inductiveand non-linear loads. Under these conditions the proposedtopology will work efficiently. The design of the value ofCf is carried out at the maximum load current, i.e., with theminimum load impedance to ensure that the designed Cf willperform satisfactorily at all other loading conditions. If Smax

is the maximum kVA rating of a system and Vbase is the basevoltage of the system, then the minimum impedance in thesystem is given as

Zmin =V 2

base

Smax= |Rl + jXl| (say). (10)

In order to achieve the unity power factor, the shunt activefilter current needs to supply the required reactive componentof the load current i.e., the fundamental imaginary part of thefilter current should be equal to the imaginary part of the loadcurrent. The filter current and load current in a particular phaseare given below

Ifilter =Vinv1 − Vl1

Rf + j(Xlf −Xcf )(11)

I load =Vl1

Rl + jXl(12)

where, Xlf = 2πfLf , Xl = 2πfLl, Xcf =1/ 2πfCf and f isthe supply frequency of fundamental voltage.

Neglecting the interfacing resistance and equating the imag-inary parts of the the above equations gives (13)

Vl1Xl

R2l +X2

l

=Vinv1 − Vl1

(Xlf −Xcf )2(Xlf −Xcf ) (13)

where, Vinv1 and Vl1 are the line to neutral rms voltage of theinverter and the PCC voltage at the fundamental frequencyrespectively. The fundamental component of inverter voltagein terms of DC-link voltage is described in [33], is given asbelow

Vinv1 =0.612Vdc

2√

3. (14)

In general, if the filter current (If ) flows from the inverterterminal to the PCC, the voltage at the inverter terminal should



5

be at a higher potential. Due to this reason, in conventionalVSI topologies, the DC-link voltage is maintained higher thanthe voltage at the PCC. Equations (15) and (16) give theKVL along the filter branch for conventional topology andthe proposed modified topology respectively.

uVdc − vl = Lfdifdt

+Rf if (15)

(uVdc −1Cf

∫ifdt)− vl = Lf

difdt

+Rf if

(uVdc − vcf )− vl = Lfdifdt

+Rf if

(16)

Where, u attains values of 1 or -1 depending on the switchingof the inverter.

In (16), the fundamental voltage across the capacitor (vcf1)adds to the inverter terminal voltage (uVdc) when the load isinductive in nature. This is because, when the load is inductivein nature, the fundamental of the filter current leads the voltageat the PCC by 90o for reactive power compensation and thusthe fundamental voltage across the capacitor again lags thefundamental filter current by 90o. Therefore, the fundamentalvoltage across the capacitor will be in phase opposition to thevoltage at the PCC. Thus, the fundamental voltage across thecapacitor adds to the inverter terminal voltage. This allows usto rate the DC-link voltage at lower value than conventionaldesign. The designer has a choice to choose the value of DC-link voltage to be reduced, such that the LC filter in the activefilter leg of each phase offers minimum impedance to thefundamental frequency and higher impedance for switchingfrequency components.

In the modified topology along with the series capacitorin the shunt active filter, the system neutral is connectedto the negative terminal of the DC bus capacitor. This willintroduce a positive DC voltage component in the inverteroutput voltage. This is because, when the top switch is ’ON’,+Vdbus appears at the inverter output and 0 V appears whenthe bottom switch is ’ON’. Thus the inverter output voltagewill have DC voltage component along with the AC voltage.The DC voltage is blocked by the series capacitor and thusthe voltage across the series capacitor will be having twocomponents, one is the AC component, which will be inphase opposition to the PCC voltage and the other is the DCcomponent. Whereas, in case of the conventional topology theinverter output voltage varies between +Vdc when top switchis ’ON’and −Vdc when the bottom switch ’ON’. Similarlywhen a four leg topology is used for shunt active filter with asingle DC capacitor, the inverter output voltage varies between+Vdbus and −Vdbus. Therefore, these topologies does notcontain any DC component in the inverter output voltage.

The modified topology contains only one DC capacitor asthe neutral is directly connected to the negative terminal ofthe DC bus, thus it avoids the need of balancing of capacitorvoltages, which is a major disadvantage of the neutral clampedtopology [6], [34]. Since the neutral wire is directly connectedto the negative terminal of the DC bus, the necessity offourth leg in the inverter is avoided. In case of the four legbased VSI topology, independent control is not possible. In

the modified topology, the three legs of the shunt active filterare independently controlled and this results in the automatictracking of the neutral current. Thus, the modified topologyhas the advantage of both the neutral clamped topology andfour leg inverter topology.

From the system parameters mentioned in Table I, phase-aload impedance is chosen as Zmin. The DC bus voltage ischosen to be 560 V for the modified topology, such that itmatches with the DC-link voltage requirement of the seriesactive filter (peak of the line to line voltage). Using equation(13), the value of the the capacitor (Cf ) is obtained to be 65µF.

IV. GENERATION OF REFERENCE COMPENSATORCURRENTS UNDER UNBALANCED AND DISTORTED

VOLTAGES

In this work, the load currents are unbalanced and dis-torted, these currents flow through the feeder impedanceand make the voltage at terminal unbalanced and distorted.The series active filter makes the voltages at PCC balancedand sinusoidal. However, the voltages still contains switchingfrequency components and they contains some distortions. Ifthese terminal voltages are used for generating the shunt filtercurrent references, the shunt algorithm results in erroneouscompensation [35]. To remove this limitation of the algorithm,fundamental positive sequence voltages v+

la1(t), v+lb1(t) and

v+lc1(t) of the PCC voltages are extracted and are used in

control algorithm for shunt active filter [35]. The expressionsfor reference compensator currents are given in (17). In thisequation, Plavg is the average load power, Ploss denotes theswitching losses and ohmic losses in actual compensator and itis generated using a capacitor voltage PI controller. The termPlavg is obtained using a moving average filter of one cyclewindow of time T in seconds. The term ϕ is the desired phaseangle between the source voltage and current.

i∗fa = ila − i∗sa = ila −v+

la1 + γ(v+lb1 − v

+lc1)

∆+1

(Plavg + Ploss)

i∗fb = ilb − i∗sb = ilb −v+

lb1 + γ(v+lc1 − v

+la1)

∆+1

(Plavg + Ploss)

i∗fc = ilc − i∗sc = ila −v+

lc1 + γ(v+la1 − v

+lb1)

∆+1

(Plavg + Ploss)

(17)

where,

∆ =∑

j=a,b,c

(v+lj1)2, γ = tanϕ/

√3

The above algorithm gives balanced source currents aftercompensation irrespective of unbalanced and distorted supply.

The reference voltages for series active filter are given as

v∗dvri = v∗li − vti

i = a, b, c(18)

where v∗li represents the desired load voltages in three-phasesand v∗dvri represents the reference series active filter voltages.



6

Once the reference quantities and the actual quantities areobtained from the measurements, the switching commandsfor the VSI switches are generated using hysteresis bandcurrent control method [36]. Hysteresis current controllerscheme is based on a feedback loop, generally with two-levelcomparators. The switching commands are issued wheneverthe error limit exceeds a specified tolerance band ’±h’. Unlikethe predictive controllers, the hysteresis controller has theadvantage of peak current limiting capacity apart from othermerits such as extremely good dynamic performance, simplic-ity in implementation and independence from load parametervariations. The disadvantage with this hysteresis method is thatthe converter switching frequency is highly dependent on theAC voltage and varies with it. The switching control law forshunt active filter is given as

If ifa ≥ i∗fa+ h1 then bottom switch is turned ON whereastop switch is turned OFF (Sa = 0, S

′

a = 1)If ifa ≤ i∗fa- h1 then top switch is turned ON whereas

bottom switch is turned OFF (Sa = 1, S′

a = 0)similarly the switching commands for series active filter is

given asIf vdvra ≥ v∗dvra+ h2 then bottom switch is turned ON

whereas top switch is turned OFF (Saa = 0, S′

aa = 1)If vdvra ≤ v∗dvra- h2 then top switch is turned ON whereas

bottom switch is turned OFF (Saa = 1, S′

aa = 0)The control circuitry for both the topologies is same and

is shown in Fig. 3. Only six switching commands are to begenerated. These six signals along with the complementarysignals will control all the 12 switches of the two inverters.

*dvr abcv

dvr abcv

as*f abci

f abci

Positive sequence extraction

Power calculation using moving

average filter (MAF)

Reference current generation using

eqn. (17)

Inverter gating circuit

PIcontroller

lossP lavgP

bscs

aasbbsccs

*dc busV

dc busV l abcv

l abci

*l abcv

t abcvHysteresis controller

l abcv

Fig. 3. Control block diagram for UPQC.

V. SIMULATION RESULTS

In order to validate the proposed topology, simulation iscarried out using graphic-driven simulation software PSCAD.The same system parameters which are given Table I withadditional Cf for a desired DC-link voltage are used to carryout simulation studies. The simulation results for both theconventional topology and the proposed modified topologyare presented in this section for better understanding andcomparison between both the topologies.

The load currents and terminal (PCC) voltages beforecompensation are shown in Fig. 4. The load currents areunbalanced and distorted as shown in Fig. 4(a), the terminalvoltages are also unbalanced and distorted because these load

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-10.0

-5.0

0.0

5.0

10.0

Cur

rent

(A

)

Time (s)

lailbi lci

lni

(a)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-400

-300

-200

-100

0

100

200

300

400

Vol

tage

(V

)

Time (s)

tav tbv tcv

(b)

Fig. 4. Simulation results before compensation (a) Load currents (b) Terminalvoltages.

currents flow through the feeder impedance in the system asshown in Fig. 4(b). Figure 5 gives the simulation results of theUPQC using conventional VSI topology. The DC-link voltagesacross the top and bottom DC-link capacitors are shown in Fig.5(a). Using PI controller the voltage across both DC capacitorsare maintained constant to a reference value of 520 V asshown in the figure. The source currents after compensationare balanced and sinusoidal as shown in Fig. 5(b). The voltageacross the interfacing inductor in phase-a is shown in Fig. 5(c).The peak to peak voltage across the inductor is 1040 V. Thethree-phase shunt compensator currents are depicted in Fig.5(d). Figure 5(e) represents the compensation performance ofthe series active filter. A sag of 50% is considered in all phasesof the the terminal voltages for 5 cycles, which start from1.9 seconds and ends at 2.0 seconds. The compensated DVRvoltages and load voltages after compensation are shown in thesame figure. The load voltages are maintained to the desiredvoltage using series active filter.

The simulation results with the modified topology are shownin Fig. 6 and Fig. 7. In this topology The value of the capacitor(Cf ) in the shunt active filter branch is chosen to be 65µF and total DC bus voltage is maintained at 560 V . Thevoltage across the series capacitor in phase-a (vcfa) and thephase-a load voltage (vla) are shown in Fig. 6(a). From thisfigure it is clear that the voltage across the capacitor is inphase opposition to the terminal voltage. According to (16),the voltage across the capacitor adds to the DC-link voltageand injects the required compensation currents into the PCC.The inverter output voltage in leg-a is shown in Fig. 6(b).The inverter output voltage varies between 0 V and +Vdbus,which will introduce a DC component along with the ACcomponents. Fast Fourier Transformer (FFT) for the voltageacross the series capacitor (vcfa) and inverter output voltage(vinva) has been applied. The rms value of the fundamentaland the DC components are shown in Fig. 6(c) for both vcfa

and vinva. The same DC component will be reflected across



7

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

0

200

400

600

0

200

400

600

Vol

tage

(V

)

Time (s)

1dcV

2dcV

(a)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-10.0

-5.0

0.0

5.0

10.0

Cur

rent

(A

)

Time (s)

sai sbi sci

sni

(b)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-900

-600

-300

0

300

600

900

Vol

tage

(V

)

Time (s)

indav

(c)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-10.0

-5.0

0.0

5.0

10.0

-10.0

-5.0

0.0

5.0

10.0

-10.0

-5.0

0.0

5.0

10.0

Cur

rent

(A

)

Time (s)

fai

fbi

fci

(d)

1.860 1.880 1.900 1.920 1.940 1.960 1.980 2.000 2.020 2.040

-500

-250

0

250

500

-300

-150

0

150

300

-500

-250

0

250

500

Vol

tage

(V

)

Time (s)

tav tbv tcv

dvrav dvrbv dvrcv

lav lbv lcv

(e)

Fig. 5. Simulation results using conventional topology (a) DC capacitorvoltages (top and bottom) (b) Source currents after compensation (c) Voltageacross the interfacing inductor in phase-a of the shunt active filter (d) Shuntactive filter currents (e) Terminal voltages with sag, DVR injected voltagesand load voltages after compensation.

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-400

-300

-200

-100

0

100

200

300

400

500

Vol

tage

(V

)

Time (s)

cfavlav

(a)

1.9800 1.9850 1.9900 1.9950 2.0000

0

100

200

300

400

500

600

Vol

tage

(V

)

Time (s)

invav

(b)

0.0 1.0 2.0 3.0 4.0 5.0

0

100

200

300

0

100

200

300

Vol

tage

(V

)Time (s)

cfavcfafundv

cfadcv

invdcv

invfundvinvav

(c)

Fig. 6. Simulation results with modified topology (a) Voltage across seriescapacitor and load voltage in phase - a (b) Inverter output voltage in leg - aof shunt active filter (c) FFT of the voltage across series capacitor and inverteroutput voltage.

the series capacitor voltage (vcfa) as shown in the Fig. 6(c).The DC bus voltage (Vdbus) is shown in Fig. 7(a). The

source currents after compensation using modified topologyare shown in Fig. 7(b). The load voltages are maintained tothe desired voltage using series active filter. The voltage acrossthe inductor is shown in Fig. 7(c), the peak to peak voltage is560 V, which is far lesser than the voltage across the inductorusing conventional topology. As the voltage across inductor ishigh in case of conventional topology , the rate of rise of filtercurrent dif

dt will be higher than that of modified topology. Thiswill allow the filter current to hit the hysteresis boundaries ata faster rate and increases the switching, whereas in modifiedtopology the number of switchings will be less. Thus, theaverage switching frequency of the switches in the proposedtopology will be less as compared to conventional topology.Since the average switching is less, the switching loss willalso decrease in modified topology. Figure 7(e) represents thecompensation performance of the series active filter. The shuntcompensator currents are displayed in Fig. 7(d), which areidentical to the currents obtained using conventional topology.A sag of 50% is considered in all phases of the the terminalvoltages for 5 cycles, which start from 1.9 seconds and ends at2.0 seconds. The compensated DVR voltages and load voltagesafter compensation are shown in the same figure.

One more advantage of having less voltage across theinductor is that the hysteresis band violation will be less. This



8

TABLE IITHD OF SOURCE CURRENTS AND TERMINAL VOLTAGES

THD (%) Without Conventional ModifiedCompensation Topology Topology

isa 9.2 2.96 1.59isb 11.7 3.20 2.19isc 12.75 2.55 1.31vla 5.99 1.48 1.12vlb 5.86 1.59 1.24vlc 6.17 2.10 1.58

TABLE IIIAVERAGE SWITCHING FREQUENCY OF THE INVERTER SWITCHES (KHZ)

Leg Shunt active filter Series active filterConventional Modified Conventional ModifiedTopology Topology Topology Topology

a 3.96 3.10 8.10 6.80b 4.12 2.44 8.30 7.20c 3.95 2.98 8.40 7.40

will improve the quality of compensation and Total HarmonicDistortion (THD) reduces in the proposed topology. Similarly,the switching in the series active filter also reduces marginallyas the DC-link voltage is reduced. The THD of the sourcecurrents and load voltages before and after compensation inall the three-phases are given in Table II. Table III givesthe average switching frequency in each leg of the inverter.This clearly shows the modified topology performance isbetter than the conventional topology with a less DC-linkvoltage, reduction in switching operation and regular trackingof reference compensator currents.

VI. EXPERIMENTAL STUDIES

The efficacy of the proposed scheme is verified with ex-perimental studies. A DSP-based prototype of the three-phaseUPQC has been developed in the laboratory. The systemparameters UPQC are the same as given in Table I, with thesource voltage rms value of 100 V. The experimental set upuses the SEMIKRON build two pulse inverters for realizingthe series filter voltages and shunt filter currents. Two DSPsTMS320F2812 are used to process the data in digital domain.The signal and logic level consist of Hall effect voltageand current transducers, signal conditioning and protectioncircuits along with isolated DC power supplies. The three-phase power quantities (voltages and currents) are converted tolow level voltage signals using Hall effect voltage and currenttransducers. In the experimental set-up, the voltage is scaleddown from ±500 V range to ±5 V range and a current of±10 A in the power network is converted to ±5 V usingthe Hall effect voltage and current transducers respectively.These signals are further conditioned using signal conditioningcircuit and given to the DSPs. The DSPs also receive a signalfrom the synchronizing circuit to realize reference quantitiesin time domain. The DSP is connected to the host computerthrough a parallel port. C codes are written in the DSP usingcode composer studio, CCS V3.3. The control algorithm inthe DSP generates switching pulses to the VSI. The switchingcommands generated by the DSPs are issued through itsgeneral purpose input and output port. These pulses are then

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

0

100

200

300

400

500

600

Vol

tage

(V

)

Time (s)

dbusV

(a)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-10.0

-5.0

0.0

5.0

10.0

Time (s)

Vol

tage

(V

)

sai sbi sci

sni

(b)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-400

-300

-200

-100

0

100

200

300

400

Time (s)

Vol

tage

(V

)

indav

(c)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-10.0

-5.0

0.0

5.0

10.0

-10.0

-5.0

0.0

5.0

10.0

-10.0

-5.0

0.0

5.0

10.0

Cur

rent

(A

)

Time (s)

fai

fbi

fci

(d)

1.860 1.880 1.900 1.920 1.940 1.960 1.980 2.000 2.020 2.040

-500

-250

0

250

500

-300

-150

0

150

300

-500

-250

0

250

500

Vol

tage

(V

)

Time (s)

tav tbv tcv

dvrav dvrbv dvrcv

lav lbv lcv

(e)

Fig. 7. Simulation results using modified topology (a) DC capacitor voltages(b) Source currents after compensation (c) Voltage across the interfacinginductor in phase-a of the shunt active filter (d) Shunt active filter currents(e) Terminal voltages with sag, DVR injected voltages and load voltages aftercompensation.



9

lai

lbi

lci

lni

10 A/div

4 A/div

(a)

tav

tbv

tcv

152 V/div

(b)

Fig. 8. Experimental results (a) Load currents before compensation (b)Terminal voltages before compensation.

passed through the blanking circuit to include a dead time inorder to prevent short circuit of the capacitor through switchesin the same VSI leg. The blanking circuit also receives STOPsignals from the protection circuit to ensure safe operationof the set-up, in case of any abnormality in the system. Theblanking circuit output pulses are given to the VSI throughthe driver circuit. ELGAR SW5500M SmartWave AC powersource is used to generate the required voltage wave shapesto conduct experimental studies.

In this experimental studies, both the conventional and pro-posed topologies are developed and experiments are performedfor comparison. For the conventional topology, the DC-linkvoltage for each capacitor is maintained to 225 V (1.6 vm).The DC-link voltage for each capacitor is taken as 125 V forthe modified topology, such that the series capacitor value is65 µF same as simulation studies from equation (13). Theload currents and the terminal voltages before compensationare shown in Fig. 8. The source and load currents are samebefore compensation and they are distorted and unbalanced.The terminal voltages are also distorted because of the feederimpedance. The THD of the source currents and terminalvoltages before compensation are given in Table IV.

TABLE IVTHD OF SOURCE CURRENTS AND TERMINAL VOLTAGES

THD (%) Without Conventional ModifiedCompensation Topology Topology

isa 10.85 4.45 3.45isb 13.47 3.75 2.80isc 14.68 3.20 2.70vla 5.25 3.05 2.60vlb 5.74 3.95 3.60vlc 5.64 3.10 2.70

The experimental results with the conventional topology areshown in Figs. 9(a)-9(e). The three-phase source voltages with50% sag and the DC bus voltage are shown in Fig. 9(a). PI

dbusV

sav

sbv

scv

500 V/div

200 V/div

(a)

dvrav

dvrbv

dvrcv

200 V/div

(b)

lav

lbv

lcv

sav

200 V/div

(c)

fai

fbi

fci

4 A/div

(d)

sai

sbi

sci

sni

10 A/div

4 A/div

(e)

Fig. 9. Experimental results using conventional topology (a) DC bus voltage(Vdbus) and source voltages with 50% sag (b) Series active filter injectedvoltages (c) Load voltages after compensation (d) Shunt filter currents (e)Source currents after compensation.

controller is used to maintain the DC-link voltage at 225 Vacross each capacitor for the source voltage rms value of 100V. The series active filter injected voltages are given in Fig.9(b). The load voltages after compensation are shown in Fig.9(c) along with the phase-a source voltage. The sag in thesource voltages are mitigated by the series active filter injectedvotlages and the load voltages are maintained to the desiredvoltage. The filter currents which are injected into the PCC tomake the source currents balanced and sinusoidal are shown in



10

Fig. 9(d). The source currents after compensation are shownin Fig. 9(e). The source currents are balanced and sinusoidal,though the switching frequency components are still present.

The load voltage and the voltage across the the seriescapacitor in phase-a for the neutral clamped topology withseries capacitor is shown in Fig. 10(a). Both the voltages arein phase opposition with respect to each other as explainedearlier. The same waveforms for the modified topology areshown in Fig. 10(b) and it can be observed that the voltageacross the series capacitor contains the DC component and alsoin phase opposition to the load voltage (vla). The performanceof these two topologies will be same except the voltages acrossthe series capacitor and inverter output voltage differ, so theresults for the modified topology are discussed in this paper.

vcfa

lav(50 V/div)

(100 V/div)

(a)

cfav

lav

100 V/div

200 V/div

(b)

Fig. 10. Load voltage and voltage across series capacitor in phase - a (a)Neutral clamped topology (b) Modified topology.

The experimental results with the proposed modified topol-ogy are shown in Figs. 11 and 12. The compensation perfor-mance of the UPQC in phase-a with the modified topology isshown in Fig. 11. The figure clearly shows the simultaneousperformance of the shunt and series active filter of the UPQCby compensating the load current and maintaining the loadvoltage to the desired value during voltage sag duration.

sav

lav

sai

lai

200 V/div

10 A/div

Fig. 11. Compensation performance of the UPQC in phase-a using modifiedtopology.

The DC-link voltage across the DC capacitor is maintainedat 250 V as mentioned earlier. The source voltages with sagand the DC bus voltage are shown in Fig. 12(a). The series

dbusV

sav

sbv

scv

500 V/div

200 V/div

(a)

dvrav

dvrbv

dvrcv

200 V/div

(b)

lav

lbv

lcv

sav

200 V/div

(c)

fai

fbi

fci

4 A/div

(d)

sai

sbi

sci

sni

10 A/div

(e)

Fig. 12. Experimental results using modified topology (a) DC bus voltage(Vdbus) and source voltages with 50% sag (b) Series active filter injectedvoltages (c) Load voltages after compensation (d) Shunt filter currents (e)Source currents after compensation.

active filter injected voltages are represented in Fig. 12(b). Theload voltages after compensation are shown in Fig. 12(c), theyare balanced and sinusoidal. The sag in the source voltagesare mitigated by the series active filter injected voltages with areduced DC-link voltage. The shunt filter currents are shown inFig. 12(d). The source currents after compensation are shownin Fig. 12(e), they are balanced and sinusoidal.

The voltage across the interfacing inductor in phase-ais shown in Fig. 13, the peak to peak voltage across the



11

indav

200 V/div

(a)

indav

200 V/div

(b)

Fig. 13. Voltage across the interfacing inductor in phase-a (a) Neutralclamped topology (b) Modified topology.

interfacing inductor in the proposed topology is 140 V whichis less than the conventional topology voltage of 250 V. Asthe voltage across inductor is high in case of conventionaltopology , the rate of rise of filter current dif

dt will be higherthan that of proposed topology. This will allow the filtercurrent to hit the hysteresis boundaries at a faster rate andincreases the switching, whereas in proposed topology thenumber of switchings will be less. Thus, the average switchingfrequency of the switches in the proposed topology will beless as compared to conventional topology. Since the averageswitching is less, the switching loss will also decrease inproposed topology. One more advantage of having less voltageacross the inductor is that the hysteresis band violation willbe less. This will improve the quality of compensation andTotal Harmonic Distortion (THD) will be less in the proposedtopology. The THD comparison of the source currents andthe terminal voltages after compensation are given in TableIV. The average switching frequencies are compared in TableV. From the table it is clear that the average switchingfrequency of the shunt and series inverters with proposedtopology has been reduced. The switching losses in the inverterhas been calculated using the procedure given in [37]. Thepercentage reduction in switching power losses by usingproposed topology are 53% and 56% for shunt and seriesactive filters respectively. From the experimental results, themodified topology gives a reduced THD’s both in the sourcecurrents and terminal voltages with a reduced DC-link voltagealong with reduction in average switching frequencies.

VII. CONCLUSIONS

A modified UPQC topology for three-phase four wiresystem has been proposed in this paper, which has the ca-pability to compensate the load at a lower DC-link voltageunder non-stiff source. Design of the filter parameters forthe series and shunt active filters are explained in detail.

TABLE VAVERAGE SWITCHING FREQUENCY OF THE INVERTER SWITCHES (KHZ)

Leg Shunt active filter Series active filterConventional Modified Conventional Modified

Topology Topology Topology Topologya 1.80 1.35 4.5 3.90b 1.95 1.60 4.65 4.05c 2.25 1.8 4.80 4.15

The proposed method is validated through simulation andexperimental studies in a three-phase distribution system withneutral clamped UPQC topology (conventional). The proposedmodified topology gives the advantages of both the conven-tional neutral clamped topology and the four leg topology.Detailed comparative studies are made for the conventionaland modified topologies. From the study, it is found thatthe modified topology has less average switching frequency,less THDs in the source currents and load voltages withreduced DC-link voltage as compared to the conventionalUPQC topology.

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[1] M. Bollen, Understanding Power Quality Problems : Voltage Sags andInterruptions. IEEE press, New York, 1999.

[2] S. V. R. Kumar and S. S. Nagaraju, “Simulation of DSTATCOM andDVR in Power Systems ,” ARPN Journal of Engineering and AppliedScience, vol. 2, no. 3, pp. 7–13, 2007.

[3] B. T. Ooi, J. C. Salmon, J. W. Dixon, and A. B. Kulkarni, “A three-phase controlled-current PWM converter with leading power factor,”IEEE Transactions on Industry Applications, vol. IA-23, no. 1, pp. 78–84, 1987.

[4] Y. Ye, M. Kazerani, and V. Quintana, “Modeling, control and implemen-tation of three-phase PWM converters,” IEEE Transactions on PowerElectronics, vol. 18, no. 3, pp. 857 – 864, May 2003.

[5] R. Gupta, A. Ghosh, and A. Joshi, “Multiband hysteresis modulation andswitching characterization for sliding-mode-controlled cascaded multi-level inverter,” IEEE Transactions on Industrial Electronics, vol. 57,no. 7, pp. 2344 –2353, July 2010.

[6] S. Srikanthan and Mahesh K. Mishra, “DC capacitor voltage equaliza-tion in neutral clamped inverters for DSTATCOM application,” IEEETransactions on Industrial Electronics, vol. 57, no. 8, pp. 2768 –2775,Aug. 2010.

[7] R. Gupta, A. Ghosh, and A. Joshi, “Switching characterization ofcascaded multilevel-inverter-controlled systems,” IEEE Transactions onIndustrial Electronics, vol. 55, no. 3, pp. 1047 –1058, March 2008.

[8] B. Singh and J. Solanki, “Load compensation for diesel generator-basedisolated generation system employing DSTATCOM,” IEEE Transactionson Industrial Electronics, vol. 47, no. 1, pp. 238 –244, Jan.-Feb. 2011.

[9] R. Gupta, A. Ghosh, and A. Joshi, “Characteristic analysis for multisam-pled digital implementation of fixed-switching-frequency closed-loopmodulation of voltage-source inverter,” IEEE Transactions on IndustrialElectronics, vol. 56, no. 7, pp. 2382 –2392, July 2009.

[10] B. Singh and J. Solanki, “A comparison of control algorithms forDSTATCOM,” IEEE Transactions on Industrial Electronics, vol. 56,no. 7, pp. 2738 –2745, July 2009.

[11] S. Rahmani, N. Mendalek, and K. Al-Haddad, “Experimental design ofa nonlinear control technique for three-phase shunt active power filter,”IEEE Transactions on Industrial Electronics, vol. 57, no. 10, pp. 3364–3375, Oct. 2010.

[12] V. Corasaniti, M. Barbieri, P. Arnera, and M. Valla, “Hybrid active filterfor reactive and harmonics compensation in a distribution network,”IEEE Transactions on Industrial Electronics, vol. 56, no. 3, pp. 670–677, March 2009.

[13] M. Milane Montero, E. Romero-Cadaval, and F. Barrero-Gonza andlez,“Hybrid multi converter conditioner topology for high-power applica-tions,” IEEE Transactions on Industrial Electronics, vol. 58, no. 6, pp.2283 –2292, June 2011.



12

[14] J. Nielsen, M. Newman, H. Nielsen, and F. Blaabjerg, “Control andtesting of a dynamic voltage restorer (DVR) at medium voltage level,”IEEE Transactions on Power Electronics, vol. 19, no. 3, pp. 806–813,2004.

[15] Y. W. Li, P. C. Loh, F. Blaabjerg, and D. Vilathgamuwa, “Investigationand improvement of transient response of DVR at medium voltage level,”IEEE Transactions on Industry Applications, vol. 43, no. 5, pp. 1309–1319, Sept.-Oct. 2007.

[16] Y. W. Li, D. Mahinda Vilathgamuwa, F. Blaabjerg, and P. C. Loh, “Arobust control scheme for medium-voltage-level DVR implementation,”IEEE Transactions on Industrial Electronics, vol. 54, no. 4, pp. 2249–2261, Aug. 2007.

[17] J. Barros and J. Silva, “Multilevel optimal predictive dynamic voltagerestorer,” IEEE Transactions on Industrial Electronics, vol. 57, no. 8,pp. 2747 –2760, Aug. 2010.

[18] D. Vilathgamuwa, H. Wijekoon, and S. Choi, “A novel technique tocompensate voltage sags in multiline distribution system - the interlinedynamic voltage restorer,” IEEE Transactions on Industrial Electronics,vol. 53, no. 5, pp. 1603 –1611, Oct. 2006.

[19] M. Kesler and E. Ozdemir, “Synchronous-reference-frame-based controlmethod for UPQC under unbalanced and distorted load conditions,”IEEE Transactions on Industrial Electronics, vol. 58, no. 9, pp. 3967–3975, Sept. 2011.

[20] K. H. Kwan, Y. C. Chu, and P. L. So, “Model-based Hinfty control ofa unified power quality conditioner,” IEEE Transactions on IndustrialElectronics, vol. 56, no. 7, pp. 2493 –2504, July 2009.

[21] V. Khadkikar and A. Chandra, “A novel structure for three-phase four-wire distribution system utilizing unified power quality conditioner(UPQC),” IEEE Transactions on Industry Applications, vol. 45, no. 5,pp. 1897 –1902, Sept.-Oct. 2009.

[22] ——, “A new control philosophy for a unified power quality conditioner(UPQC) to coordinate load-reactive power demand between shunt andseries inverters,” IEEE Transactions on Power Delivery, vol. 23, no. 4,pp. 2522 –2534, Oct. 2008.

[23] H. Akagi and R. Kondo, “A transformer less hybrid active filter usinga three-level pulse width modulation (PWM) converter for a medium-voltage motor drive,” IEEE Transactions on Power Electronics, vol. 25,no. 6, pp. 1365 –1374, June 2010.

[24] H. Jou, K. Wu, J. Wu, C. Li, and M. Huang, “Novel power convertertopology for threephase four-wire hybrid power filter,” IET PowerElectronics, vol. 1, no. 1, pp. 164–173, 2008.

[25] T. Zhili, L. Xun, C. Jian, K. Yong, and D. Shanxu, “A direct controlstrategy for UPQC in three-phase four-wire system,” in Power Electron-ics and Motion Control Conference, 2006. IPEMC 2006. CES/IEEE 5thInternational, vol. 2, Aug. 2006, pp. 1 –5.

[26] M. Brenna, R. Faranda, and E. Tironi, “A new proposal for power qualityand custom power improvement: Open UPQC,” IEEE Transactions onPower Delivery,, vol. 24, no. 4, pp. 2107 –2116, Oct. 2009.

[27] V. George and Mahesh K. Mishra, “DSTATCOM topologies for threephase high power applications,” Int. J. Power Electronics, vol. 2, no. 2,pp. 107–124, 2010.

[28] Y. Pal, A. Swarup, and B. Singh, “A comparative analysis of three-phase four-wire UPQC topologies,” in Power Electronics, Drives andEnergy Systems (PEDES) 2010 Power India, 2010 Joint InternationalConference on, Dec. 2010, pp. 1 –6.

[29] B. Singh, P. Jayaprakash, and D. Kothari, “A T-connected transformerand three-leg VSC based DSTATCOM for power quality improvement,”IEEE Transactions on Power Electronics,, vol. 23, no. 6, pp. 2710 –2718, Nov. 2008.

[30] T. Zhili, L. Xun, C. Jian, K. Yong, and Z. Yang, “A new controlstrategy of UPQC in three-phase four-wire system,” in Power ElectronicsSpecialists Conference, 2007. PESC 2007. IEEE, June 2007, pp. 1060–1065.

[31] Mahesh K. Mishra and K. Karthikeyan, “Design and analysis of voltagesource inverter for active compensators to compensate unbalanced andnon-linear loads,” in International Power Engineering Conference, 2007,IPEC 2007., 2007, pp. 649 –654.

[32] S. Sasitharan and M. Mishra, “Design of passive filter components forswitching band controlled DVR,” in TENCON 2008 - 2008 IEEE Region10 Conference, Nov. 2008, pp. 1 –6.

[33] N. Mohan, Undeland, and W. Robbins., Power electronics: converters,applications, and design. Wiley, 2003.

[34] R. Stala, “Application of balancing circuit for dc-link voltages balance ina single-phase diode-clamped inverter with two three-level legs,” IEEETransactions on Industrial Electronics, vol. 58, no. 9, pp. 4185 –4195,Sept. 2011.

[35] U. K. Rao, Mahesh K. Mishra, and A. Ghosh, “Control strategies forload compensation using instantaneous symmetrical component theoryunder different supply voltages,” IEEE Transactions on Power Delivery,vol. 23, no. 4, pp. 2310 –2317, 2008.

[36] D. M. Brod and D. W. Novotny, “Current control of VSI-PWM invert-ers,” IEEE Transactions on Industry Applications, vol. IA-21, no. 3, pp.562 –570, May 1985.

[37] S. Pattanaik and K. Mahapatra, “Power loss estimation for PWM andsoft-switching inverter using RDCLI,” in International MultiConferenceof Engineers and Computer Scientists, 2010, pp. 1401–1406.

Srinivas Bhaskar Karanki received his B. Tech.degree from Acharya Nagarjuna University, Guntur,India in 2007. He has completed his Ph.D. in Electri-cal Engineering Department from IIT Madras, Indiain 2012.

His areas of interest include power quality, powerelectronic devices, and power electronics applica-tions in power systems.

Nagesh G (S’11) received his Bachelor of Tech-nology degree from J.N.T.U Kakinada, India, in2004, the M.S. degree from the Indian Institute oftechnology Madras in 2009 and presently pursuingPh.D. in Indian Institute of Technology Madras,Chennai, India.

His areas of interests include custom power de-vices, power electronics applications to power sys-tems and control systems.

Mahesh K. Mishra (S’00-M’02-SM’10) receivedthe B.Tech. degree from the College of Technology,Pantnagar, India in 1991, the M.E. degree from theUniversity of Roorkee, Roorkee, India, in 1993, andthe Ph.D. degree in electrical engineering from theIndian Institute of Technology, Kanpur, India, in2002.

He has teaching and research experience of about20 years. For about ten years, he was with the Elec-trical Engineering Department, Visvesvaraya Na-

tional Institute of Technology, Nagpur, India. Currently, he is a Professor inthe Electrical Engineering Department, Indian Institute of Technology Madras,Chennai. His interests are in the areas of power distribution systems, powerelectronics, and control systems.

Dr. Mahesh is life member of the Indian Society of Technical Education(ISTE).

B. Kalyan Kumar (M’07) received his Bachelorof Technology from J.N.T.U Hyderabad, India. Hereceived his master and doctoral degree from IndianInstitute of Technology kanpur in the year 2003 and2007 respectively.

He is at present working as Assistant Professorin Indian Institute of Technology Madras, India.His areas of interests includes power quality, powersystem dynamics and FACTS.

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