64/80-pin high-performance, 64-kbyte enhanced flash ... · 2003-2013 microchip technology inc....

PIC18F6525/6621/8525/862164/80-Pin High-Performance, 64-Kbyte Enhanced Flash

Microcontrollers with A/D

High Performance RISC CPU:• Linear program memory addressing to 64 Kbytes• Linear data memory addressing to 4 Kbytes • 1 Kbyte of data EEPROM• Up to 10 MIPs operation:

- DC – 40 MHz osc./clock input- 4 MHz – 10 MHz osc./clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path• Priority levels for interrupts • 31-level, software accessible hardware stack• 8 x 8 Single-cycle Hardware Multiplier

Peripheral Features:• High current sink/source 25 mA/25 mA• Four external interrupt pins• Timer0 module: 8-bit/16-bit timer/counter • Timer1 module: 16-bit timer/counter • Timer2 module: 8-bit timer/counter • Timer3 module: 16-bit timer/counter • Timer4 module: 8-bit timer/counter • Secondary oscillator clock option – Timer1/Timer3• Two Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution 6.25 ns (TCY/16)- Compare is 16-bit, max. resolution 100 ns (TCY)- PWM output: 1 to 10-bit PWM resolution

• Three Enhanced Capture/Compare/PWM (ECCP) modules:- Same Capture/Compare features as CCP- One, two or four PWM outputs- Selectable polarity- Programmable dead time- Auto-Shutdown on external event- Auto-Restart

• Master Synchronous Serial Port (MSSP) module with two modes of operation:- 2/3/4-wire SPI (supports all 4 SPI modes)- I2C™ Master and Slave mode

• Two Enhanced USART modules:- Supports RS-485, RS-232 and LIN 1.2- Auto-Wake-up on Start bit- Auto-Baud Rate Detect

• Parallel Slave Port (PSP) module

External Memory Interface (PIC18F8525/8621 Devices Only):• Address capability of up to 2 Mbytes• 16-bit interface

Analog Features:• 10-bit, up to 16-channel Analog-to-Digital

Converter (A/D): - Auto-Acquisition- Conversion available during Sleep

• Programmable 16-level Low-Voltage Detection (LVD) module:- Supports interrupt on Low-Voltage Detection

• Programmable Brown-out Reset (BOR)• Dual analog comparators:

- Programmable input/output configuration

Special Microcontroller Features:• 100,000 erase/write cycle Enhanced Flash

program memory typical• 1,000,000 erase/write cycle Data EEPROM

memory typical• 1 second programming time• Flash/Data EEPROM Retention: > 100 years• Self-reprogrammable under software control• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)• Watchdog Timer (WDT) with its own On-Chip

RC Oscillator for reliable operation• Programmable code protection• Power-saving Sleep mode• Selectable oscillator options including:

- 4x Phase Lock Loop (PLL) – of primary oscillator- Secondary Oscillator (32 kHz) clock input

• In-Circuit Serial Programming™ (ICSP™) via two pins• MPLAB® In-Circuit Debug (ICD 2) via two pins

CMOS Technology:• Low power, high-speed Flash technology• Fully static design• Wide operating voltage range (2.0V to 5.5V)• Industrial and Extended temperature ranges

DeviceProgram Memory Data Memory

I/O10-bitA/D (ch)

CCP/ECCP PWM

MSSP/SPI™/Master I2C™ EUSART

Timers8-bit/16-bit EMIBytes # Single-Word Instructions

SRAM (bytes)

EEPROM (bytes)

PIC18F6525 48K 24576 3840 1024 53 12 2/3 14 Y 2 2/3 NPIC18F6621 64K 32768 3840 1024 53 12 2/3 14 Y 2 2/3 NPIC18F8525 48K 24576 3840 1024 70 16 2/3 14 Y 2 2/3 YPIC18F8621 64K 32768 3840 1024 70 16 2/3 14 Y 2 2/3 Y

2003-2013 Microchip Technology Inc. DS39612C-page 1

PIC18F6525/6621/8525/8621

Pin Diagrams

PIC18F6525

1234567891011121314

383736353433

50 49

17 18 19 20 21 22 23 24 25 26

RE

2/C

S/P

2BR

E3/

P3C

RE

4/P3

BR

E5/

P1C

RE

6/P1

BR

E7/

ECC

P2(1

) /P2A

(1)

RD

0/P

SP0

VD

D

VS

S

RD

1/P

SP1

RD

2/P

SP2

RD

3/P

SP3

RD

4/P

SP4

RD

5/P

SP5

RD

6/P

SP6

RD

7/P

SP7

RE1/WR/P2CRE0/RD/P2D

RG0/ECCP3/P3ARG1/TX2/CK2RG2/RX2/DT2

RG3/CCP4/P3DMCLR/VPP/RG5(2)

RG4/CCP5/P1DVSSVDD

RF7/SSRF6/AN11

RF5/AN10/CVREFRF4/AN9RF3/AN8

RF2/AN7/C1OUT

RB0/INT0/FLT0RB1/INT1RB2/INT2RB3/INT3RB4/KBI0RB5/KBI1/PGMRB6/KBI2/PGCVSSOSC2/CLKO/RA6OSC1/CLKIVDDRB7/KBI3/PGD

RC4/SDI/SDARC3/SCK/SCLRC2/ECCP1/P1A

RF0

/AN

5R

F1/A

N6/

C2O

UT

AVD

D

AVS

S

RA

3/A

N3/

VRE

F+R

A2/

AN

2/VR

EF-

RA

1/A

N1

RA

0/A

N0

VS

S

VD

D

RA

4/T0

CK

IR

A5/

AN4/

LVD

IN

RC

1/T1

OS

I/EC

CP

2(1)

/P2A

(1)

RC

0/T1

OS

O/T

13C

KI

RC

7/R

X1/

DT1

RC

6/TX

1/C

K1

RC5/SDO

1516

31

4039

27 28 29 30 32

4847464544434241

54 53 52 5158 57 56 5560 5964 63 62 61

64-Pin TQFP

Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set.2: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

PIC18F6621

DS39612C-page 2 2003-2013 Microchip Technology Inc.

PIC18F6525/6621/8525/8621

Pin Diagrams (Cont.’d)

PIC18F8525

345678910111213141516

4847464544434241

4039

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32

RE

2/AD

10/C

S/P

2BR

E3/

AD11

/P3C

(2)

RE

4/AD

12/P

3B(2

)

RE

5/AD

13/P

1C(2

)

RE

6/AD

14/P

1B(2

)

RE

7/AD

15/E

CC

P2(

1)/P

2A(1

)

RD

0/A

D0/

PS

P0

VD

D

VS

S

RD

1/A

D1/

PS

P1

RD

2/A

D2/

PS

P2

RD

3/A

D3/

PS

P3

RD

4/A

D4/

PS

P4

RD

5/A

D5/

PS

P5

RD

6/A

D6/

PS

P6

RD

7/A

D7/

PS

P7

RE1/AD9/WR/P2CRE0/AD8/RD/P2DRG0/ECCP3/P3A

RG1/TX2/CK2RG2/RX2/DT2

RG3/CCP4/P3DMCLR/VPP/RG5(3)

RG4/CCP5/P1DVSSVDD

RF7/SS

RB0/INT0/FLT0RB1/INT1RB2/INT2RB3/INT3/ECCP2(1)/P2A(1)

RB4/KBI0RB5/KBI1/PGMRB6/KBI2/PGCVSSOSC2/CLKO/RA6OSC1/CLKIVDDRB7/KBI3/PGD

RC4/SDI/SDARC3/SCK/SCLRC2/ECCP1/P1A

RF0

/AN

5R

F1/A

N6/

C2O

UT

AVD

D

AVS

S

RA

3/A

N3/

VRE

F+R

A2/

AN

2/VR

EF-

RA

1/A

N1

RA

0/A

N0

VS

S

VD

D

RA

4/T0

CK

IR

A5/

AN

4/LV

DIN

RC

1/T1

OS

I/EC

CP

2(1)

/P2A

(1)

RC

0/T1

OS

O/T

13C

KI

RC

7/R

X1/

DT1

RC

6/TX

1/C

K1

RC5/SDOR

J0/A

LER

J1/O

E

RH

1/A

17R

H0/

A16

12

RH2/A18RH3/A19

1718

RH7/AN15/P1B(2)

RH6/AN14/P1C(2)

RH

5/A

N13

/P3B

(2)

RH

4/A

N12

/P3C

(2)

RJ5

/CE

RJ4

/BA

0

37

RJ7/UBRJ6/LB

5049

RJ2/WRLRJ3/WRH

1920

33 34 35 36 38

5857565554535251

6059

68 67 66 6572 71 70 6974 7378 77 76 757980

80-Pin TQFP

Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device is configured in Microcontroller mode; or with RB3 when CCP2MX is cleared in all other program memory modes.

2: P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set and with RH7:RH4 when ECCPMX is not set.

3: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

RF5/AN10/CVREFRF4/AN9RF3/AN8

RF2/AN7/C1OUT

RF6/AN11

PIC18F8621


PIC18F6525/6621/8525/8621

Table of Contents1.0 Device Overview .......................................................................................................................................................................... 72.0 Oscillator Configurations ............................................................................................................................................................ 213.0 Reset .......................................................................................................................................................................................... 294.0 Memory Organization ................................................................................................................................................................. 395.0 Flash Program Memory.............................................................................................................................................................. 616.0 External Memory Interface ......................................................................................................................................................... 717.0 Data EEPROM Memory ............................................................................................................................................................. 798.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 859.0 Interrupts .................................................................................................................................................................................... 8710.0 I/O Ports ................................................................................................................................................................................... 10311.0 Timer0 Module ......................................................................................................................................................................... 13112.0 Timer1 Module ......................................................................................................................................................................... 13513.0 Timer2 Module ......................................................................................................................................................................... 14114.0 Timer3 Module ......................................................................................................................................................................... 14315.0 Timer4 Module ......................................................................................................................................................................... 14716.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 14917.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 15718.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 17319.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 21320.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 23321.0 Comparator Module.................................................................................................................................................................. 24322.0 Comparator Voltage Reference Module................................................................................................................................... 24923.0 Low-Voltage Detect .................................................................................................................................................................. 25324.0 Special Features of the CPU.................................................................................................................................................... 25925.0 Instruction Set Summary .......................................................................................................................................................... 27526.0 Development Support............................................................................................................................................................... 31727.0 Electrical Characteristics .......................................................................................................................................................... 32328.0 DC and AC Characteristics Graphs And Tables ...................................................................................................................... 35729.0 Packaging Information.............................................................................................................................................................. 373Appendix A: Revision History............................................................................................................................................................. 377Appendix B: Device Differences......................................................................................................................................................... 377Appendix C: Conversion Considerations ........................................................................................................................................... 378Appendix D: Migration From Mid-Range to Enhanced Devices......................................................................................................... 378Appendix E: Migration From High-End to Enhanced Devices............................................................................................................ 379Index .................................................................................................................................................................................................. 381On-Line Support................................................................................................................................................................................. 391Systems Information and Upgrade Hot Line ...................................................................................................................................... 391Reader Response .............................................................................................................................................................................. 392PIC18F6525/6621/8525/8621 Product Identification System ............................................................................................................ 393


PIC18F6525/6621/8525/8621

TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.We welcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Web site; http://www.microchip.com• Your local Microchip sales office (see last page)• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-ature number) you are using.

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PIC18F6525/6621/8525/8621

NOTES:


PIC18F6525/6621/8525/8621

1.0 DEVICE OVERVIEWThis document contains device specific information forthe following devices:

• PIC18F6525• PIC18F6621• PIC18F8525• PIC18F8621

This family offers the advantages of allPIC18 microcontrollers – namely, high computationalperformance at an economical price – with the additionof high-endurance Enhanced Flash program memory.The PIC18F6525/6621/8525/8621 family also providesan enhanced range of program memory options andversatile analog features that make it ideal for complex,high performance applications.

1.1 Key Features

1.1.1 EXPANDED MEMORYThe PIC18F6525/6621/8525/8621 family providesample room for application code and includesmembers with 48 Kbytes or 64 Kbytes of code space.

Other memory features are:

• Data RAM and Data EEPROM: The PIC18F6525/6621/8525/8621 family also provides plenty of roomfor application data. The devices have 3840 bytes ofdata RAM, as well as 1024 bytes of data EEPROMfor long term retention of nonvolatile data.

• Memory Endurance: The Enhanced Flash cells forboth program memory and data EEPROM are ratedto last for many thousands of erase/write cycles –up to 100,000 for program memory and 1,000,000for EEPROM. Data retention without refresh isconservatively estimated to be greater than40 years.

1.1.2 EXTERNAL MEMORY INTERFACEIn the unlikely event that 64 Kbytes of program memoryis inadequate for an application, the PIC18F8525/8621members of the family also implement an externalmemory interface. This allows the controller’s internalprogram counter to address a memory space of up to2 MBytes, permitting a level of data access that few8-bit devices can claim.

With the addition of new operating modes, the externalmemory interface offers many new options, including:

• Operating the microcontroller entirely from externalmemory

• Using combinations of on-chip and externalmemory, up to the 2-Mbyte limit

• Using external Flash memory for reprogrammable application code or large data tables

• Using external RAM devices for storing large amounts of variable data

1.1.3 EASY MIGRATIONRegardless of the memory size, all devices share thesame rich set of peripherals, allowing for a smoothmigration path as applications grow and evolve.

The consistent pinout scheme used throughout theentire family also aids in migrating to the next largerdevice. This is true when moving between the 64-pinmembers, between the 80-pin members, or evenJumping From 64-pin To 80-pin Devices.

1.1.4 OTHER SPECIAL FEATURES• Communications: The PIC18F6525/6621/8525/

8621 family incorporates a range of serial communi-cation peripherals, including 2 independentEnhanced USARTs and a Master SSP module capa-ble of both SPI and I2C (Master and Slave) modes ofoperation. Also, for PIC18F6525/6621/8525/8621devices, one of the general purpose I/O ports can bereconfigured as an 8-bit Parallel Slave Port for directprocessor to processor communications.

• CCP Modules: All devices in the family incorporatetwo Capture/Compare/PWM (CCP) modules andthree Enhanced CCP (ECCP) modules to maximizeflexibility in control applications. Up to four differenttime bases may be used to perform several differentoperations at once. Each of the three ECCPs offerup to four PWM outputs, allowing for a total of12 PWMs. The ECCPs also offer many beneficialfeatures, including polarity selection, ProgrammableDead Time, Auto-Shutdown and Restart andHalf-Bridge and Full-Bridge Output modes.

• Analog Features: All devices in the family feature10-bit A/D converters with up to 16 input channels,as well as the ability to perform conversions duringSleep mode and auto-acquisition conversions. Alsoincluded are dual analog comparators withprogrammable input and output configuration, aprogrammable Low-Voltage Detect module and aProgrammable Brown-out Reset module.

• Self-programmability: These devices can write totheir own program memory spaces under internalsoftware control. By using a bootloader routinelocated in the protected boot block at the top ofprogram memory, it becomes possible to create anapplication that can update itself in the field.


PIC18F6525/6621/8525/8621

1.2 Details on Individual Family

MembersThe PIC18F6525/6621/8525/8621 devices are avail-able in 64-pin (PIC18F6525/6621) and 80-pin(PIC18F8525/8621) packages. They are differentiatedfrom each other in four ways:

1. Flash program memory (48 Kbytes forPIC18F6525/8525 devices; 64 Kbytes forPIC18F6621/8621 devices).

2. A/D channels (12 for PIC18F6525/6621devices; 16 for PIC18F8525/8621 devices).

3. I/O ports (7 on PIC18F6525/6621 devices; 9 onPIC18F8525/8621 devices).

4. External program memory interface (presentonly on PIC18F8525/8621 devices)

All other features for devices in the PIC18F6525/6621/8525/8621 family are identical. These are summarizedin Table 1-1.

Block diagrams of the PIC18F6525/6621 andPIC18F8525/8621 devices are provided in Figure 1-1and Figure 1-2, respectively. The pinouts for thesedevice families are listed in Table 1-2.

TABLE 1-1: PIC18F6525/6621/8525/8621 DEVICE FEATURES Features PIC18F6525 PIC18F6621 PIC18F8525 PIC18F8621

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHzProgram Memory (Bytes) 48K 64K 48K 64KProgram Memory (Instructions) 24576 32768 24576 32768Data Memory (Bytes) 3840 3840 3840 3840Data EEPROM Memory (Bytes) 1024 1024 1024 1024External Memory Interface No No Yes YesInterrupt Sources 17 17 17 17I/O Ports Ports A, B, C, D,

E, F, GPorts A, B, C, D,

E, F, GPorts A, B, C, D, E,

F, G, H, JPorts A, B, C, D, E,

F, G, H, JTimers 5 5 5 5Capture/Compare/PWM Modules 2 2 2 2Enhanced Capture/Compare/PWM Module

3 3 3 3

Serial Communications MSSP, Addressable EUSART (2)

MSSP, Addressable EUSART (2)



Parallel Communications PSP PSP PSP PSP10-bit Analog-to-Digital Module 12 input channels 12 input channels 16 input channels 16 input channelsResets (and Delays) POR, BOR,

RESET Instruction, Stack Full,

Stack Underflow (PWRT, OST)

POR, BOR, RESET Instruction,

Stack Full, Stack Underflow

(PWRT, OST)



(PWRT, OST)



(PWRT, OST)Programmable Low-Voltage Detect

Yes Yes Yes Yes

Programmable Brown-out Reset Yes Yes Yes YesInstruction Set 77 Instructions 77 Instructions 77 Instructions 77 InstructionsPackage 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP


PIC18F6525/6621/8525/8621

FIGURE 1-1: PIC18F6525/6621 BLOCK DIAGRAM

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

InstructionDecode and

Control

OSC1/CLKIOSC2/CLKO

VDD,

PORTA

PORTB

PORTC

RA4/T0CKIRA5/AN4/LVDIN

RB0/INT0/FLT0

RC0/T1OSO/T13CKIRC1/T1OSI/ECCP2(1)/P2A(1)RC2/ECCP1/P1ARC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX1/CK1RC7/RX1/DT1

Brown-outReset

RA3/AN3/VREF+RA2/AN2/VREF-RA1/AN1RA0/AN0

TimingGeneration

RB1/INT1

Data Latch

Data RAM(3.8 Kbytes)

Address Latch

Address

12

Bank 0, FBSR FSR0FSR1FSR2

inc/declogicDecode

4 12 4PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

W

8

BITOP88

ALU

8

Test ModeSelect

Address LatchProgram Memory

(48/64 Kbytes)

Data Latch

20

21

16

8

8

8

Table Pointer

inc/dec logic

218

Data Bus

Table Latch

8

IR

12

3

ROM Latch

PORTD

RD7/PSP7

RB2/INT2RB3/INT3

PCLATU

PCU

Precision

ReferenceBand Gap

PORTE

PORTGRG0/ECCP3/P3ARG1/TX2/CK2RG2/RX2/DT2RG3/CCP4/P3DRG4/CCP5/P1D

RE6/P1BRE7/ECCP2(1)/P2A(1)

RE5/P1CRE4/P3BRE3/P3CRE2/CS/P2B

RE0/RD/P2DRE1/WR/P2C

OSC2/CLKO/RA6

VSS

Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set.2: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

PORTF

RF6/AN11RF7/SS

RF5/AN10/CVREFRF4/AN9RF3/AN8RF2/AN7/C1OUT

RF0/AN5RF1/AN6/C2OUT

RB4/KBI0RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGD

MCLR(2)

MCLR/VPP/RG5(2)

:RD0/PSP0

EUSART1Comparator MSSP EUSART2

10-bit ADCTimer2Timer1 Timer3 Timer4Timer0

CCP4 CCP5

LVD

ECCP2 ECCP3ECCP1

BOR DataEEPROM


PIC18F6525/6621/8525/8621

FIGURE 1-2: PIC18F8525/8621 BLOCK DIAGRAM

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

InstructionDecode and

Control

OSC1/CLKIOSC2/CLKO

Brown-outReset

EUSART1Comparator MSSP EUSART2

TimingGeneration

10-bit ADC

Data Latch

Data RAM(3.8 Kbytes)

Address Latch

Address

12

Bank0, FBSR FSR0FSR1FSR2

inc/declogicDecode

4 12 4PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

W

8

BITOP88

ALU

8

Test ModeSelect

Address LatchProgram Memory

(48/64 Kbytes)

Data Latch

20

21

16

8

8

8

Table Pointer

inc/dec logic

218

Data Bus

Table Latch

8

IR

12

3

ROM Latch

PCLATU

PCU

Precision

ReferenceBand Gap

PORTHRH0/A16:RH3/A19(4)

PORTJ

RJ6/LBRJ7/UB

RJ5/CERJ4/BA0RJ3/WRHRJ2/WRL

RJ0/ALERJ1/OE

Timer2Timer1 Timer3 Timer4Timer0

Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device is configured inMicrocontroller mode; or with RB3 when CCP2MX is cleared in all other program memory modes.

2: P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set and with RH7:RH4 when ECCPMX is not set.3: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.4: External memory interface pins are multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).

CCP4 CCP5

RH7/AN15/P1B(2)RH6/AN14/P1C(2)RH5/AN13/P3B(2)RH4/AN12/P3C(2)

LVD

PORTA

PORTB

PORTC

RA4/T0CKIRA5/AN4/LVDIN

RB0/INT0/FLT0

RC0/T1OSO/T13CKI

RC2/ECCP1/P1ARC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX1/CK1RC7/RX1/DT1

RA3/AN3/VREF+RA2/AN2/VREF-RA1/AN1RA0/AN0

RB1/INT1

PORTD

RB2/INT2RB3/INT3/ECCP2(1)/P2A(1)

PORTE

PORTGRG0/ECCP3/P3ARG1/TX2/CK2RG2/RX2/DT2RG3/CCP4/P3DRG4/CCP5/P1D

RE6/AD14/P1B(2,4)RE7/AD15/ECCP2(1)/P2A(1,4)

RE5/AD13/P1C(2,4)RE4/AD12/P3B(2,4)RE3/AD11/P3C(2,4)RE2/AD10/CS/P2B(4)

RE0/AD8/RD/P2D(4)RE1/AD9/WR/P2C(4)

OSC2/CLKO/RA6

PORTF

RF6/AN11RF7/SS

RF5/AN10/CVREFRF4/AN9RF3/AN8RF2/AN7/C1OUT

RF0/AN5RF1/AN6/C2OUT

RB4/KBI0RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGD

RC1/T1OSI/ECCP2(1)/P2A(1)

VDD, VSS MCLR(3)

ECCP2 ECCP3ECCP1

MCLR/VPP/RG5(3)

RD7/AD7/PSP7:

BOR

AD15:AD0, A19:16(4)

Sys

tem

Bus

Inte

rface

DataEEPROM

RD0/AD0/PSP0(4)


PIC18F6525/6621/8525/8621

TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS

Pin NamePin Number Pin

TypeBufferType DescriptionPIC18F6X2X PIC18F8X2X

MCLR/VPP/RG5(9)

MCLR

VPPRG5

7 9

I

PI

ST

—ST

Master Clear (input) or programming voltage (output).

Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.Digital input.

OSC1/CLKIOSC1

CLKI

39 49I

I

CMOS/ST

CMOS

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS.External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).

OSC2/CLKO/RA6OSC2

CLKO

RA6

40 50O

O

I/O

—

—

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal oscillator mode.In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD)

Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H) is not set (all Program Memory modes except Microcontroller).

2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).3: External memory interface functions are only available on PIC18F8525/8621 devices.4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H) is set and for

all PIC18F6525/6621 devices.5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H) is not set.8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of

the part in user or ICSP™ modes. See parameter D001 for details.9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.


PIC18F6525/6621/8525/8621

PORTA is a bidirectional I/O port.RA0/AN0

RA0AN0

24 30I/OI

TTLAnalog

Digital I/O.Analog input 0.

RA1/AN1RA1AN1

23 29I/OI

TTLAnalog


RA2/AN2/VREF-RA2AN2VREF-

22 28I/OII

TTLAnalogAnalog

Digital I/O.Analog input 2.A/D reference voltage (low) input.

RA3/AN3/VREF+RA3AN3VREF+

21 27I/OII

TTLAnalogAnalog

Digital I/O.Analog input 3.A/D reference voltage (high) input.

RA4/T0CKIRA4

T0CKI

28 34I/O

I

ST/OD

ST

Digital I/O – Open-drain when configured as output.Timer0 external clock input.

RA5/AN4/LVDINRA5AN4LVDIN

27 33I/OII

TTLAnalogAnalog

Digital I/O.Analog input 4.Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.

TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)









PIC18F6525/6621/8525/8621

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/INT0/FLT0RB0INT0FLT0

48 58I/OII

TTLSTST

Digital I/O.External interrupt 0.PWM Fault input for ECCP1.

RB1/INT1RB1INT1

47 57I/OI

TTLST

Digital I/O.External interrupt 1.

RB2/INT2RB2INT2

46 56I/OI

TTLST

Digital I/O.External interrupt 2.

RB3/INT3/ECCP2/P2ARB3INT3ECCP2(1)

P2A(1)

45 55I/OI/OI/O

O

TTLSTST

—

Digital I/O.External interrupt 3.Enhanced Capture 2 input, Compare 2 output, PWM2 output.ECCP2 output P2A.

RB4/KBI0RB4KBI0

44 54I/OI

TTLST

Digital I/O.Interrupt-on-change pin.

RB5/KBI1/PGMRB5KBI1PGM

43 53I/OI

I/O

TTLSTST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP™ programming enable pin.

RB6/KBI2/PGCRB6KBI2PGC

42 52I/OI

I/O

TTLSTST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock.

RB7/KBI3/PGDRB7KBI3PGD

37 47I/OI

I/O

TTLSTST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger andICSP programming data.










PIC18F6525/6621/8525/8621

PORTC is a bidirectional I/O port.RC0/T1OSO/T13CKI

RC0T1OSOT13CKI

30 36I/OOI

ST—ST

Digital I/O.Timer1 oscillator output. Timer1/Timer3 external clock input.

RC1/T1OSI/ECCP2/P2ARC1T1OSIECCP2(2)

P2A(2)

29 35I/OI

I/O

O

STCMOS

ST

—

Digital I/O.Timer1 oscillator input.Enhanced Capture 2 input, Compare 2 output, PWM 2 output.ECCP2 output P2A.

RC2/ECCP1/P1ARC2ECCP1

P1A

33 43I/OI/O

O

STST

—

Digital I/O.Enhanced Capture 1 input, Compare 1 output, PWM 1 output.ECCP1 output P1A.

RC3/SCK/SCLRC3SCK

SCL

34 44I/OI/O

I/O

STST

ST

Digital I/O.Synchronous serial clock input/output for SPI™ mode.Synchronous serial clock input/output for I2C™ mode.

RC4/SDI/SDARC4SDISDA

35 45I/OI

I/O

STSTST

Digital I/O.SPI data in.I2C data I/O.

RC5/SDORC5SDO

36 46I/OO

ST—

Digital I/O.SPI data out.

RC6/TX1/CK1RC6TX1CK1

31 37I/OO

I/O

ST—ST

Digital I/O.USART1 asynchronous transmit.USART1 synchronous clock (see RX1/DT1).

RC7/RX1/DT1RC7RX1DT1

32 38I/OI

I/O

STSTST

Digital I/O.USART1 asynchronous receive.USART1 synchronous data (see TX1/CK1).










PIC18F6525/6621/8525/8621

PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled.

RD0/AD0/PSP0RD0AD0(3)PSP0

58 72I/OI/OI/O

STTTLTTL

Digital I/O.External memory address/data 0.Parallel Slave Port data.


55 69I/OI/OI/O

STTTLTTL



54 68I/OI/OI/O

STTTLTTL



53 67I/OI/OI/O

STTTLTTL



52 66I/OI/OI/O

STTTLTTL



51 65I/OI/OI/O

STTTLTTL



50 64I/OI/OI/O

STTTLTTL



49 63I/OI/OI/O

STTTLTTL











PIC18F6525/6621/8525/8621

PORTE is a bidirectional I/O port.RE0/AD8/RD/P2D

RE0AD8(3)RDP2D

2 4I/OI/OIO

STTTLTTL—

Digital I/O.External memory address/data 8.Read control for Parallel Slave Port.ECCP2 output P2D.

RE1/AD9/WR/P2CRE1AD9(3)WRP2C

1 3I/OI/OIO

STTTLTTLST

Digital I/O.External memory address/data 9.Write control for Parallel Slave Port.ECCP2 output P2C.

RE2/AD10/CS/P2BRE2AD10(3)CSP2B

64 78I/OI/OIO

STTTLTTL—

Digital I/O.External memory address/data 10.Chip select control for Parallel Slave Port.ECCP2 output P2B.

RE3/AD11/P3CRE3AD11(3)P3C(4)

63 77I/OI/OO

STTTL—

Digital I/O.External memory address/data 11.ECCP3 output P3C.

RE4/AD12/P3BRE4AD12(3)P3B(4)

62 76I/OI/OO

STTTL—

Digital I/O.External memory address/data 12.ECCP3 output P3B.

RE5/AD13/P1CRE5AD13(3)P1C(4)

61 75I/OI/OO

STTTL—

Digital I/O.External memory address/data 13.ECCP1 output P1C.

RE6/AD14/P1BRE6AD14(3)P1B(4)

60 74I/OI/OO

STTTL—

Digital I/O.External memory address/data 14.ECCP1 output P1B.

RE7/AD15/ECCP2/P2ARE7AD15(3)ECCP2(5)

P2A(5)

59 73I/OI/OI/O

O

STTTLST

—

Digital I/O.External memory address/data 15.Enhanced Capture 2 input, Compare 2 output, PWM 2 output.ECCP2 output P2A.










PIC18F6525/6621/8525/8621

PORTF is a bidirectional I/O port.RF0/AN5

RF0AN5

18 24I/OI

STAnalog


RF1/AN6/C2OUTRF1AN6C2OUT

17 23I/OIO

STAnalog

ST

Digital I/O.Analog input 6.Comparator 2 output.

RF2/AN7/C1OUTRF2AN7C1OUT

16 18I/OIO

STAnalog

ST

Digital I/O.Analog input 7.Comparator 1 output.

RF3/AN8RF1AN8

15 17I/OI

STAnalog


RF4/AN9RF1AN9

14 16I/OI

STAnalog


RF5/AN10/CVREFRF1AN10CVREF

13 15I/OIO

STAnalogAnalog

Digital I/O.Analog input 10.Comparator VREF output.

RF6/AN11RF6AN11

12 14I/OI

STAnalog


RF7/SSRF7SS

11 13I/OI

STTTL

Digital I/O.SPI™ slave select input.










PIC18F6525/6621/8525/8621

PORTG is a bidirectional I/O port.RG0/ECCP3/P3A

RG0ECCP3

P3A

3 5I/OI/O

O

STST

—

Digital I/O.Enhanced Capture 3 input, Compare 3 output, PWM 3 output.ECCP3 output P3A.

RG1/TX2/CK2RG1TX2CK2

4 6I/OO

I/O

ST—ST

Digital I/O.USART2 asynchronous transmit.USART2 synchronous clock (see RX2/DT2).

RG2/RX2/DT2RG2RX2DT2

5 7I/OI

I/O

STSTST

Digital I/O.USART2 asynchronous receive.USART2 synchronous data (see TX2/CK2).

RG3/CCP4/P3DRG3CCP4

P3D

6 8I/OI/O

O

STST

—

Digital I/O.Capture 4 input, Compare 4 output, PWM 4 output.ECCP3 output P3D.

RG4/CCP5/P1DRG4CCP5

P1D

8 10I/OI/O

O

STST

—

Digital I/O.Capture 5 input, Compare 5 output, PWM 5 output.ECCP1 output P1D.

RG5 7 9 — — See MCLR/VPP/RG5 pin.










PIC18F6525/6621/8525/8621

PORTH is a bidirectional I/O port(6).RH0/A16

RH0A16

— 79I/OO

STTTL

Digital I/O.External memory address 16.

RH1/A17RH1A17

— 80I/OO

STTTL


RH2/A18RH2A18

— 1I/OO

STTTL


RH3/A19RH3A19

— 2I/OO

STTTL


RH4/AN12/P3CRH4AN12P3C(7)

— 22I/OIO

STAnalog

—

Digital I/O.Analog input 12.ECCP3 output P3C.

RH5/AN13/P3BRH5AN13P3B(7)

— 21I/OIO

STAnalog

—

Digital I/O.Analog input 13.ECCP3 output P3B.

RH6/AN14/P1CRH6AN14P1C(7)

— 20I/OIO

STAnalog

—

Digital I/O.Analog input 14.ECCP1 output P1C.

RH7/AN15/P1BRH7AN15P1B(7)

— 19I/OIO

STAnalog

—

Digital I/O.Analog input 15.ECCP1 output P1B.










PIC18F6525/6621/8525/8621

PORTJ is a bidirectional I/O port(6).RJ0/ALE

RJ0ALE

— 62I/OO

STTTL

Digital I/O.External memory address latch enable.

RJ1/OERJ1OE

— 61I/OO

STTTL

Digital I/O.External memory output enable.

RJ2/WRLRJ2WRL

— 60I/OO

STTTL

Digital I/O.External memory write low control.

RJ3/WRHRJ3WRH

— 59I/OO

STTTL

Digital I/O.External memory write high control.

RJ4/BA0RJ4BA0

— 39I/OO

STTTL

Digital I/O.System bus byte address 0 control.

RJ5/CERJ5CE

— 40I/OO

STTTL

Digital I/OExternal memory access indicator.

RJ6/LBRJ6LB

— 41I/OO

STTTL

Digital I/O.External memory low byte select.

RJ7/UBRJ7UB

— 42I/OO

STTTL

Digital I/O.External memory high byte select.

VSS 9, 25, 41, 56

11, 31, 51, 70

P — Ground reference for logic and I/O pins.

VDD 10, 26, 38, 57

12, 32, 48, 71

P — Positive supply for logic and I/O pins.

AVSS(8) 20 26 P — Ground reference for analog modules.AVDD(8) 19 25 P — Positive supply for analog modules.










PIC18F6525/6621/8525/8621

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator TypesThe PIC18F6525/6621/8525/8621 devices can beoperated in twelve different oscillator modes. The usercan program four configuration bits (FOSC3, FOSC2,FOSC1 and FOSC0) to select one of these eightmodes:

1. LP Low-Power Crystal2. XT Crystal/Resonator3. HS High-Speed Crystal/Resonator4. RC External Resistor/Capacitor5. EC External Clock6. ECIO External Clock with I/O pin

enabled7. HS+PLL High-Speed Crystal/Resonator

with PLL enabled8. RCIO External Resistor/Capacitor with

I/O pin enabled9. ECIO+SPLL External Clock with software

controlled PLL10. ECIO+PLL External Clock with PLL and I/O

pin enabled11. HS+SPLL High-Speed Crystal/Resonator

with software control12. RCIO External Resistor/Capacitor with

I/O pin enabled

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS, HS+PLL or HS+SPLL Oscillator modes, acrystal or ceramic resonator is connected to the OSC1and OSC2 pins to establish oscillation. Figure 2-1 showsthe pin connections.

The PIC18F6525/6621/8525/8621 oscillator designrequires the use of a parallel cut crystal.

FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP CONFIGURATION)

TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS

Note: Use of a series cut crystal may give afrequency out of the crystal manufacturersspecifications.

Ranges Tested:

Mode Freq C1 C2

XT 455 kHz2.0 MHz4.0 MHz

68-100 pF15-68 pF15-68 pF

68-100 pF15-68 pF15-68 pF

HS 8.0 MHz16.0 MHz

10-68 pF10-22 pF

10-68 pF10-22 pF

These values are for design guidance only. See notes following this table.

Resonators Used:

2 kHz 8 MHz4 MHz 16 MHz

Note 1: Higher capacitance increases the stabilityof the oscillator but also increases thestart-up time.

2: When operating below 3V VDD, or whenusing certain ceramic resonators at anyvoltage, it may be necessary to use highgain HS mode, try a lower frequencyresonator or switch to a crystal oscillator.

3: Since each resonator/crystal has its owncharacteristics, the user should consult theresonator/crystal manufacturer for appro-priate values of external components orverify oscillator performance.

Note 1: See Table 2-1 and Table 2-2 for recommended values of C1 and C2.

2: A series resistor (RS) may be required for AT strip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

To

Logic

PIC18F6X2X/8X2XRS(2)

Internal


PIC18F6525/6621/8525/8621

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

An external clock source may also be connected to theOSC1 pin in the HS, XT and LP modes as shown inFigure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSCILLATOR CONFIGURATION)

2.3 RC OscillatorFor timing insensitive applications, the “RC” and“RCIO” device options offer additional cost savings.The RC oscillator frequency is a function of the supplyvoltage, the resistor (REXT) and capacitor (CEXT)values and the operating temperature. In addition tothis, the oscillator frequency will vary from unit to unitdue to normal process parameter variation. Further-more, the difference in lead frame capacitancebetween package types will also affect the oscillationfrequency, especially for low CEXT values. The useralso needs to take into account variation due totolerance of external R and C components used.Figure 2-3 shows how the R/C combination isconnected.

In the RC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic.

FIGURE 2-3: RC OSCILLATOR MODE

The RCIO Oscillator mode functions like the RC modeexcept that the OSC2 pin becomes an additionalgeneral purpose I/O pin. The I/O pin becomes bit 6 ofPORTA (RA6).

Ranges Tested:

Mode Freq C1 C2

LP 32.0 kHz 33 pF 33 pFXT 200 kHz 47-68 pF 47-68 pF

1.0 MHz 15 pF 15 pF4.0 MHz 15 pF 15 pF

HS 4.0 MHz 15 pF 15 pF8.0 MHz 15-33 pF 15-33 pF20.0 MHz 15-33 pF 15-33 pF25.0 MHz 15-33 pF 15-33 pF

These values are for design guidance only. See notes following this table.

Crystals Used

32 kHz 4 MHz200 kHz 8 MHz1 MHz 20 MHz

Note 1: Higher capacitance increases the stabilityof the oscillator but also increases thestart-up time.

2: RS (see Figure 2-1) may be required inHS mode, as well as XT mode, to avoidoverdriving crystals with low drive levelspecification.

3: Since each resonator/crystal has its owncharacteristics, the user should consult theresonator/crystal manufacturer for appro-priate values of external components orverify oscillator performance.

OSC1

OSC2Open

Clock fromExt. System PIC18F6X2X/8X2X

OSC2/CLKO

CEXT

REXT

PIC18F6X2X/8X2X

OSC1

FOSC/4

InternalClock

VDD

VSS

Recommended values: 3 k REXT 100 kCEXT > 20 pF


PIC18F6525/6621/8525/8621

2.4 External Clock InputThe EC, ECIO, EC+PLL and EC+SPLL Oscillatormodes require an external clock source to be con-nected to the OSC1 pin. The feedback device betweenOSC1 and OSC2 is turned off in these modes to savecurrent. There is a maximum 1.5 s start-up requiredafter a Power-on Reset or wake-up from Sleep mode.

In the EC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic. Figure 2-4 shows the pin connections for the ECOscillator mode.

FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC modeexcept that the OSC2 pin becomes an additionalgeneral purpose I/O pin. The I/O pin becomes bit 6 ofPORTA (RA6). Figure 2-5 shows the pin connectionsfor the ECIO Oscillator mode.

FIGURE 2-5: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)

2.5 Phase Locked Loop (PLL)A Phase Locked Loop circuit is provided as aprogrammable option for users that want to multiplythe frequency of the incoming oscillator signal by 4.For an input clock frequency of 10 MHz, the internalclock frequency will be multiplied to 40 MHz. This isuseful for customers who are concerned with EMI dueto high-frequency crystals.

The PLL can only be enabled when the oscillatorconfiguration bits are programmed for High-SpeedOscillator or External Clock mode. If they areprogrammed for any other mode, the PLL is notenabled and the system clock will come directly fromOSC1. There are two types of PLL modes: SoftwareControlled PLL and Configuration Bits Controlled PLL.In Software Controlled PLL mode, PIC18F6525/6621/8525/8621 executes at regular clock frequency after allReset conditions. During execution, the application canenable PLL and switch to 4x clock frequency operationby setting the PLLEN bit in the OSCCON register. InConfiguration Bits Controlled PLL, the PLL operationcannot be changed “on-the-fly”. To enable or disable it,the controller must either cycle through a Power-onReset, or switch the clock source from the mainoscillator to the Timer1 oscillator and back again (seeSection 2.6 “Oscillator Switching Feature” fordetails).

The type of PLL is selected by programmingFOSC configuration bits in the CONFIG1HConfiguration register. The oscillator mode is specifiedduring device programming.

A PLL lock timer is used to ensure that the PLL haslocked before device execution starts. The PLL locktimer has a time-out that is called TPLL.

FIGURE 2-6: PLL BLOCK DIAGRAM

OSC1

OSC2FOSC/4


OSC1

I/O (OSC2)RA6


MU

X

VCO

Divide by 4

PLL Enable

FIN

FOUT SYSCLK

PhaseComparator

LoopFilter


PIC18F6525/6621/8525/8621

2.6 Oscillator Switching FeatureThe PIC18F6525/6621/8525/8621 devices include afeature that allows the system clock source to beswitched from the main oscillator to an alternate lowfrequency clock source. For the PIC18F6525/6621/8525/8621 devices, this alternate clock source is theTimer1 oscillator. If a low-frequency crystal (32 kHz, forexample) has been attached to the Timer1 oscillatorpins and the Timer1 oscillator has been enabled, thedevice can switch to a low-power execution mode.

Figure 2-7 shows a block diagram of the system clocksources. The clock switching feature is enabled byprogramming the Oscillator Switching Enable(OSCSEN) bit in the CONFIG1H Configuration registerto a ‘0’. Clock switching is disabled in an erased device.See Section 12.0 “Timer1 Module” for further detailsof the Timer1 oscillator. See Section 24.0 “SpecialFeatures of the CPU” for Configuration registerdetails.

FIGURE 2-7: DEVICE CLOCK SOURCES

PIC18F6X2X/8X2X

TOSC

4 x PLL

TT1P

TSCLK

ClockSource

MU

X

TOSC/4

T1OSCENEnableOscillator

T1OSO

T1OSI

Clock Source Option for Other Modules

OSC1

OSC2

Sleep

Timer1 Oscillator

Main Oscillator


PIC18F6525/6621/8525/8621

2.6.1 SYSTEM CLOCK SWITCH BIT

The system clock source switching is performed undersoftware control. The system clock switch bits,SCS1:SCS0 (OSCCON), control the clockswitching. When the SCS0 bit is ‘0’, the system clocksource comes from the main oscillator that is selectedby the FOSC configuration bits in the CONFIG1HConfiguration register. When the SCS0 bit is set, thesystem clock source will come from the Timer1oscillator. The SCS0 bit is cleared on all forms of Reset.

When the FOSC bits are programmed for Software PLLmode, the SCS1 bit can be used to select betweenprimary oscillator/clock and PLL output. The SCS1 bitwill only have an effect on the system clock if the PLLis enabled (PLLEN = 1) and locked (LOCK = 1), else itwill be forced cleared. When programmed withConfiguration Controlled PLL, the SCS1 bit will beforced clear.

REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER

Note: The Timer1 oscillator must be enabledand operating to switch the system clocksource. The Timer1 oscillator is enabledby setting the T1OSCEN bit in the Timer1Control register (T1CON). If the Timer1oscillator is not enabled, then any write tothe SCS0 bit will be ignored (SCS0 bitforced cleared) and the main oscillator willcontinue to be the system clock source.

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0— — — — LOCK PLLEN(1) SCS1 SCS0(2)

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’bit 3 LOCK: Phase Lock Loop Lock Status bit

1 = Phase Lock Loop output is stable as system clock0 = Phase Lock Loop output is not stable and output cannot be used as system clock

bit 2 PLLEN: Phase Lock Loop Enable bit(1)

1 = Enable Phase Lock Loop output as system clock0 = Disable Phase Lock Loop

bit 1 SCS1: System Clock Switch bit 1When PLLEN and LOCK bits are set:1 = Use PLL output0 = Use primary oscillator/clock input pinWhen PLLEN or LOCK bit is cleared:Bit is forced clear.

bit 0 SCS0: System Clock Switch bit 0(2)

When OSCSEN configuration bit = 0 and T1OSCEN bit = 1:1 = Switch to Timer1 oscillator/clock pin0 = Use primary oscillator/clock input pinWhen OSCSEN and T1OSCEN are in other states:Bit is forced clear.

Note 1: PLLEN bit is forced set when configured for ECIO+PLL and HS+PLL modes. Thisbit is writable for ECIO+SPLL and HS+SPLL modes only; forced cleared for all otheroscillator modes.

2: The setting of SCS0 = 1 supersedes SCS1 = 1.

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown


PIC18F6525/6621/8525/8621

2.6.2 OSCILLATOR TRANSITIONS

PIC18F6525/6621/8525/8621 devices contain circuitryto prevent “glitches” when switching between oscillatorsources. Essentially, the circuitry waits for eight risingedges of the clock source that the processor is switch-ing to. This ensures that the new clock source is stableand that its pulse width will not be less than the shortestpulse width of the two clock sources.

A timing diagram indicating the transition from the mainoscillator to the Timer1 oscillator is shown in Figure 2-8.The Timer1 oscillator is assumed to be running all thetime. After the SCS0 bit is set, the processor is frozen atthe next occurring Q1 cycle. After eight synchronizationcycles are counted from the Timer1 oscillator, operationresumes. No additional delays are required after thesynchronization cycles.

FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR

The sequence of events that takes place when switch-ing from the Timer1 oscillator to the main oscillator willdepend on the mode of the main oscillator. In additionto eight clock cycles of the main oscillator, additionaldelays may take place.

If the main oscillator is configured for an externalcrystal (HS, XT, LP), then the transition will take placeafter an oscillator start-up time (TOST) has occurred. Atiming diagram, indicating the transition from theTimer1 oscillator to the main oscillator for HS, XT andLP modes, is shown in Figure 2-9.

FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)

Q3Q2Q1Q4Q3Q2

OSC1

Internal

SCS(OSCCON)

Program PC + 2PC

Note: TDLY is the delay from SCS high to first count of transition circuit.

Q1

T1OSI

Q4 Q1Q1

TSCS

Clock

Counter

System

Q2 Q3 Q4 Q1

TDLY

TT1P

TOSC

21 3 4 5 6 7 8

PC + 4

Q3Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2

OSC1

Internal

SCS(OSCCON)

ProgramPC PC + 2

Note: TOST = 1024 TOSC (drawing not to scale).

T1OSI

System Clock

TOST

Q1

PC + 6

TT1P

TOSC

TSCS

1 2 3 4 5 6 7 8

Counter


PIC18F6525/6621/8525/8621

If the main oscillator is configured for HS mode withPLL active, an oscillator start-up time (TOST) plus anadditional PLL time-out (TPLL) will occur. The PLL time-out is typically 2 ms and allows the PLL to lock to themain oscillator frequency. A timing diagram, indicatingthe transition from the Timer1 oscillator to the mainoscillator for HS+PLL mode, is shown in Figure 2-10.

FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1(HS WITH PLL ACTIVE, SCS1 = 1)

If the main oscillator is configured for EC mode with PLLactive, only PLL time-out (TPLL) will occur. The PLL time-out is typically 2 ms and allows the PLL to lock to themain oscillator frequency. A timing diagram, indicatingthe transition from the Timer1 oscillator to the mainoscillator for EC with PLL active, is shown in Figure 2-11.

FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (EC WITH PLL ACTIVE, SCS1 = 1)

Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2

OSC1

Internal System

SCS(OSCCON)

Program Counter PC PC + 2

Note: TOST = 1024 TOSC (drawing not to scale).

T1OSI

Clock

TOST

Q3

PC + 4

TPLLTOSC

TT1P

TSCS

Q4

PLL ClockInput 1 2 3 4 5 6 7 8

Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2

OSC1

Internal System

SCS(OSCCON)

Program Counter PC PC + 2

T1OSI

Clock

Q3

PC + 4

TPLLTOSC

TT1P

TSCS

Q4

PLL ClockInput 1 2 3 4 5 6 7 8


PIC18F6525/6621/8525/8621

If the main oscillator is configured in the RC, RCIO, ECor ECIO modes, there is no oscillator start-up time-out.Operation will resume after eight cycles of the mainoscillator have been counted. A timing diagram, indi-cating the transition from the Timer1 oscillator to themain oscillator for RC, RCIO, EC and ECIO modes, isshown in Figure 2-12.

FIGURE 2-12: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)

2.7 Effects of Sleep Mode on the On-Chip Oscillator

When the device executes a SLEEP instruction, the on-chip clocks and oscillator are turned off and the deviceis held at the beginning of an instruction cycle (Q1state). With the oscillator off, the OSC1 and OSC2signals will stop oscillating. Since all the transistor

switching currents have been removed, Sleep modeachieves the lowest current consumption of the device(only leakage currents). Enabling any on-chip featurethat will operate during Sleep will increase the currentconsumed during Sleep. The user can wake fromSleep through external Reset, Watchdog Timer Reset,or through an interrupt.

TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

2.8 Power-up DelaysPower-up delays are controlled by two timers so that noexternal Reset circuitry is required for mostapplications. The delays ensure that the device is keptin Reset until the device power supply and clock arestable. For additional information on Reset operation,see Section 3.0 “Reset”.The first timer is the Power-up Timer (PWRT) whichoptionally provides a fixed delay of 72 ms (nominal) onpower-up only (POR and BOR). The second timer isthe Oscillator Start-up Timer (OST), intended to keepthe chip in Reset until the crystal oscillator is stable.

With the PLL enabled (HS+PLL and EC+PLL oscillatormode), the time-out sequence following a Power-onReset is different from other oscillator modes. Thetime-out sequence is as follows: First, the PWRT time-out is invoked after a POR time delay has expired.Then, the Oscillator Start-up Timer (OST) is invoked.However, this is still not a sufficient amount of time toallow the PLL to lock at high frequencies. The PWRTtimer is used to provide an additional fixed 2 ms(nominal) time-out to allow the PLL ample time to lockto the incoming clock frequency.

Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3

OSC1

Internal System

SCS(OSCCON)

Program PC PC + 2

Note: RC Oscillator mode assumed.

PC + 4

T1OSI

Clock

Q4TT1P

TOSC

TSCS

1 2 3 4 5 6 7 8

Counter

Oscillator Mode OSC1 Pin OSC2 Pin

RC Floating, external resistor should pull high At logic lowRCIO Floating, external resistor should pull high Configured as PORTA, bit 6ECIO Floating Configured as PORTA, bit 6EC Floating At logic lowLP, XT and HS Feedback inverter disabled at

quiescent voltage levelFeedback inverter disabled at quiescent voltage level

Note: See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.


PIC18F6525/6621/8525/8621

3.0 RESETThe PIC18F6525/6621/8525/8621 devices differentiatebetween various kinds of Reset:

a) Power-on Reset (POR) b) MCLR Reset during normal operationc) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal

operation)e) Programmable Brown-out Reset (BOR) f) RESET Instructiong) Stack Full Reseth) Stack Underflow Reset

Most registers are unaffected by a Reset. Their statusis unknown on POR and unchanged by all otherResets. The other registers are forced to a “Resetstate” on Power-on Reset, MCLR, WDT Reset, Brown-out Reset, MCLR Reset during Sleep and by theRESET instruction.

Most registers are not affected by a WDT wake-upsince this is viewed as the resumption of normal oper-ation. Status bits from the RCON register, RI, TO, PD,POR and BOR, are set or cleared differently in differentReset situations as indicated in Table 3-2. These bitsare used in software to determine the nature of theReset. See Table 3-3 for a full description of the Resetstates of all registers.

A simplified block diagram of the On-Chip Reset Circuitis shown in Figure 3-1.

The Enhanced MCU devices have a MCLR noise filterin the MCLR Reset path. The filter will detect andignore small pulses. The MCLR pin is not driven low byany internal Resets, including the WDT.

FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

S

R Q

External Reset

MCLR

VDD

OSC1

WDTModule

VDD RiseDetect

OST/PWRT

On-chipRC OSC(1)

WDTTime-out

Power-on Reset

OST10-bit Ripple Counter

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST(2)

Enable PWRT

Sleep

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.2: See Table 3-1 for time-out situations.

Brown-outReset

BOR

RESET Instruction

StackPointer

Stack Full/Underflow Reset


PIC18F6525/6621/8525/8621

3.1 Power-on Reset (POR)A Power-on Reset pulse is generated on-chip whenVDD rise is detected. To take advantage of the PORcircuitry, tie the MCLR pin through a 1 k to 10 kresistor to VDD. This will eliminate external RCcomponents usually needed to create a Power-onReset delay. A minimum rise rate for VDD is specified(parameter D004). For a slow rise time, see Figure 3-2.

When the device starts normal operation (i.e., exits theReset condition), device operating parameters(voltage, frequency, temperature, etc.) must be met toensure operation. If these conditions are not met, thedevice must be held in Reset until the operatingconditions are met.

FIGURE 3-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)

3.2 Power-up Timer (PWRT)The Power-up Timer provides a fixed nominal time-out(parameter 33) only on power-up from the POR. ThePower-up Timer operates on an internal RC oscillator.The chip is kept in Reset as long as the PWRT is active.The PWRT’s time delay allows VDD to rise to anacceptable level. A configuration bit is provided toenable/disable the PWRT.

The power-up time delay will vary from chip-to-chip dueto VDD, temperature and process variation. See DCparameter 33 for details.

3.3 Oscillator Start-up Timer (OST)The Oscillator Start-up Timer (OST) provides a 1024oscillator cycle (from OSC1 input) delays after thePWRT delay is over (parameter 32). This ensures thatthe crystal oscillator or resonator has started andstabilized.

The OST time-out is invoked only for XT, LP and HSmodes and only on Power-on Reset, or wake-up fromSleep.

3.4 PLL Lock Time-outWith the PLL enabled, the time-out sequence followinga Power-on Reset is different from other oscillatormodes. A portion of the Power-up Timer is used to pro-vide a fixed time-out that is sufficient for the PLL to lockto the main oscillator frequency. This PLL lock time-out(TPLL) is typically 2 ms and follows the oscillatorstart-up time-out.

3.5 Brown-out Reset (BOR)A configuration bit, BOR, can disable (if clear/programmed) or enable (if set) the Brown-out Resetcircuitry. If VDD falls below parameter D005 for greaterthan parameter 35, the brown-out situation will resetthe chip. A Reset may not occur if VDD falls belowparameter D005 for less than parameter 35. The chipwill remain in Brown-out Reset until VDD rises aboveBVDD. If the Power-up Timer is enabled, it will beinvoked after VDD rises above BVDD; it then will keepthe chip in Reset for an additional time delay(parameter 33). If VDD drops below BVDD while thePower-up Timer is running, the chip will go back into aBrown-out Reset and the Power-up Timer will beinitialized. Once VDD rises above BVDD, the Power-upTimer will execute the additional time delay.

3.6 Time-out SequenceOn power-up, the time-out sequence is as follows:First, PWRT time-out is invoked after the POR timedelay has expired. Then, OST is activated. The totaltime-out will vary based on oscillator configuration andthe status of the PWRT. For example, in RC mode withthe PWRT disabled, there will be no time-out at all.Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 andFigure 3-7 depict time-out sequences on power-up.

Since the time-outs occur from the POR pulse, thetime-outs will expire if MCLR is kept low long enough.Bringing MCLR high will begin execution immediately(Figure 3-5). This is useful for testing purposes or tosynchronize more than one PIC18F6525/6621/8525/8621 device operating in parallel.

Table 3-2 shows the Reset conditions for some SpecialFunction Registers, while Table 3-3 shows the Resetconditions for all of the registers.

Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down.

2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device’s electrical specification.

3: R1 = 1 k to 10 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

C

R1RD

VDD

MCLR

PIC18F6X2X/8X2X


PIC18F6525/6621/8525/8621

TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS

REGISTER 3-1: RCON REGISTER BITS AND POSITIONS(1)

TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER

OscillatorConfiguration

Power-up(2)Brown-out

Wake-up fromSleep or

Oscillator SwitchPWRTE = 0 PWRTE = 1

HS with PLL enabled(1) 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms 72 ms(2) + 1024 TOSC + 2 ms 1024 TOSC + 2 msHS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms(2) + 1024 TOSC 1024 TOSC

EC 72 ms 1.5 s 72 ms(2) 1.5 s(3)

External RC 72 ms — 72 ms(2) —

Note 1: 2 ms is the nominal time required for the 4x PLL to lock.2: 72 ms is the nominal power-up timer delay, if implemented.3: 1.5 s is the recovery time from Sleep. There is no recovery time from oscillator switch.

R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0

IPEN — — RI TO PD POR BORbit 7 bit 0

Note 1: Refer to Section 4.14 “RCON Register” for bit definitions.

Condition Program Counter RI TO PD POR BOR STKFUL STKUNF

Power-on Reset 0000h 1 1 1 0 0 u u

MCLR Reset during normal operation 0000h u u u u u u uSoftware Reset during normal operation 0000h 0 u u u u u uStack Full Reset during normal operation 0000h u u u u u u 1Stack Underflow Reset during normal operation

0000h u u u u u 1 u

MCLR Reset during Sleep 0000h u 1 0 u u u uWDT Reset 0000h 1 0 1 u u u uWDT Wake-up PC + 2 u 0 0 u u u uBrown-out Reset 0000h 1 1 1 1 0 u uInterrupt Wake-up from Sleep PC + 2(1) u 1 0 u u u uLegend: u = unchanged, x = unknownNote 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (0008h or 0018h).


PIC18F6525/6621/8525/8621

TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Register Applicable Devices Power-on Reset,Brown-out Reset

MCLR ResetsWDT Reset

RESET InstructionStack Resets

Wake-up via WDT or Interrupt

TOSU Feature1 Feature2 ---0 0000 ---0 0000 ---0 uuuu(3)

TOSH Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu(3)

TOSL Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu(3)

STKPTR Feature1 Feature2 00-0 0000 uu-0 0000 uu-u uuuu(3)

PCLATU Feature1 Feature2 ---0 0000 ---0 0000 ---u uuuuPCLATH Feature1 Feature2 0000 0000 0000 0000 uuuu uuuuPCL Feature1 Feature2 0000 0000 0000 0000 PC + 2(2)

TBLPTRU Feature1 Feature2 --00 0000 --00 0000 --uu uuuuTBLPTRH Feature1 Feature2 0000 0000 0000 0000 uuuu uuuuTBLPTRL Feature1 Feature2 0000 0000 0000 0000 uuuu uuuuTABLAT Feature1 Feature2 0000 0000 0000 0000 uuuu uuuuPRODH Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuPRODL Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuINTCON Feature1 Feature2 0000 000x 0000 000u uuuu uuuu(1)

INTCON2 Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu(1)

INTCON3 Feature1 Feature2 1100 0000 1100 0000 uuuu uuuu(1)

INDF0 Feature1 Feature2 N/A N/A N/APOSTINC0 Feature1 Feature2 N/A N/A N/APOSTDEC0 Feature1 Feature2 N/A N/A N/APREINC0 Feature1 Feature2 N/A N/A N/APLUSW0 Feature1 Feature2 N/A N/A N/AFSR0H Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuuFSR0L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuWREG Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuINDF1 Feature1 Feature2 N/A N/A N/APOSTINC1 Feature1 Feature2 N/A N/A N/APOSTDEC1 Feature1 Feature2 N/A N/A N/APREINC1 Feature1 Feature2 N/A N/A N/APLUSW1 Feature1 Feature2 N/A N/A N/AFSR1H Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuuLegend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 3-2 for Reset value for specific condition.5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.7: If MCLR function is disabled, PORTG is a read-only bit.8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode.


PIC18F6525/6621/8525/8621

FSR1L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuBSR Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuuINDF2 Feature1 Feature2 N/A N/A N/APOSTINC2 Feature1 Feature2 N/A N/A N/APOSTDEC2 Feature1 Feature2 N/A N/A N/APREINC2 Feature1 Feature2 N/A N/A N/APLUSW2 Feature1 Feature2 N/A N/A N/AFSR2H Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuuFSR2L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuSTATUS Feature1 Feature2 ---x xxxx ---u uuuu ---u uuuuTMR0H Feature1 Feature2 0000 0000 uuuu uuuu uuuu uuuuTMR0L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuT0CON Feature1 Feature2 1111 1111 1111 1111 uuuu uuuuOSCCON Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuuLVDCON Feature1 Feature2 --00 0101 --00 0101 --uu uuuuWDTCON Feature1 Feature2 ---- ---0 ---- ---0 ---- ---uRCON(4) Feature1 Feature2 0--1 11qq 0--1 qquu u--1 qquuTMR1H Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuTMR1L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuT1CON Feature1 Feature2 0-00 0000 u-uu uuuu u-uu uuuuTMR2 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuuPR2 Feature1 Feature2 1111 1111 1111 1111 uuuu uuuuT2CON Feature1 Feature2 -000 0000 -000 0000 -uuu uuuuSSPBUF Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuSSPADD Feature1 Feature2 0000 0000 0000 0000 uuuu uuuuSSPSTAT Feature1 Feature2 0000 0000 0000 0000 uuuu uuuuSSPCON1 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuuSSPCON2 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuuADRESH Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuuADRESL Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu

TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register Applicable Devices Power-on Reset,Brown-out Reset

MCLR ResetsWDT Reset

RESET InstructionStack Resets

Wake-up via WDT or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 3-2 for Reset value for specific condition.5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.7: If MCLR function is disabled, PORTG is a read-only bit.8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.9: The MEMCON register is unimplemented and reads a

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