384 • 2008 IEEE International Solid-State Circuits Conference

ISSCC 2008 / SESSION 21 / SRAM / 21.5

21.5 65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS

Masanao Yamaoka1, Noriaki Maeda2, Yasuhisa Shimazaki2, Kenichi Osada1

1Hitachi, Tokyo, Japan, 2Renesas Technology, Tokyo, Japan

Increasing Vth variation is becoming a serious problem in SoCs.Especially in SRAM, Vth variation has a critical impact on operat-ing margins. Self-repairing SRAM [1] uses body bias to improveSRAM operating margin; however, this scheme does not correctthe ratio of the Vth values of NMOS and PMOS, which is importantfor SRAM operation. Assist circuits [2] require special treatment,and also require large design costs. We thus create a body-biasedSRAM in which the NMOS and PMOS body biases are separatelycontrolled to maintain the operating margin at the target value bymaintaining the ratio between the Vth values of NMOS and PMOS.Furthermore, we design a technique to separately measure the Vth

of NMOS and PMOS. This technique is used to determine the bodybias of NMOS and PMOS individually. Prototype chips with 1Mb0.51mm2 high-density SRAM cells using a 65nm low-power processare fabricated and achieve 1.0V operation, even when consideringactual Vth variation.

Figure 21.5.1 shows a performance improvement system tolerantto PVT fluctuation in multi-core SoCs. The performance deteriora-tion of the core logic circuits is improved by boosting local supplyvoltages according to a speed monitor, because the PVT fluctuationcauses speed deterioration in logic circuits. In SRAM, the largestcomponent of PVT fluctuation is due to Vth variation, causing dete-rioration of SRAM operating margin, which is reduced by the fluc-tuation of the ratio of NMOS and PMOS Vth. By applying bodybiases to NMOS (VBN) and PMOS (VBP) individually, the varyingVth is compensated and the deteriorated operating margin isimproved. Voltages VBN and VBP are generated by a VBB gener-ator according to the process condition.

The Vth variation of a MOSFET is composed of random and sys-tematic components. The systematic component is compensated byVBB. The graph of Fig. 21.5.2 shows the Vth window of SRAM oper-ation. The horizontal and vertical axes indicate Vth values ofNMOS and PMOS due to systematic variation. The area in thecenter bounded by the read and write limit lines is the operatingwindow defined by considering the random variation in addition tothe systematic variation. In the graph, there are two limit lines forboth read and write; one limit line shows 5.2σ random variation,which bounds a smaller area, and the other shows half the varia-tion of 2.6σ, which bounds a larger area. Thus these two pairs oflimit lines show the deterioration of operating margin due toincreasing random variation. When the average values ofMOSFETs Vth in SRAM array are within the window, the SRAMoperates correctly and the Vth values are roughly distributed with-in the diamond shape of 3σ systematic variation in both NMOSand PMOS. By applying adequate VBB, as shown by the arrows inFig. 21.5.2, the distributed Vth values are adjusted within the oper-ating window. In areas (B) and (C), reverse body bias only to theNMOS or PMOS pushes the Vth values into the operating window,showing the benefit of separate control of the VBBs of NMOS andPMOS to increasing SRAM operating margin.

The upper left graph of Fig. 21.5.3 shows the Vth distribution of10,000 chips (gray points) due to systematic Vth variation, calculat-ed by Monte-Carlo simulation. The gray points show the averageVth value of all MOSFETs integrated in one chip, which is used todetermine the VBB, and therefore the value has to be accuratelymeasured. The Vth values of MOSFETs in one chip have a normaldistribution, as shown in the upper right graph in Fig. 21.5.3. Onesimple method to aquire the average Vth value of a chip is to meas-ure only a small number of MOSFET devices, for example, about10 devices. As shown in the graph, the average value of all devices(gray points in left graph) is different from the average values of10 monitoring devices (black points in the left graph). The differ-

ences across 10,000 chips between the average of all devices and10 devices are plotted in the lower right graph and the distributionvalues are indicated left lower table in Fig. 21.5.3. These differ-ences are large and fatal when using VBB. For example, in the leftgraph in Fig. 21.5.3, if the Vth of a fabricated SRAM is at point Aand a 20mV error occurs in Vth measurement, the measured Vth isat point B which requires NMOS reverse body bias, a body biaschanges the Vth to point C, which is out of the operating Vth win-dow (indicated as broken lines in the graph). This situation showsthat an originally operable device is changed to an inoperabledevice. Furthermore, in actual measurements, the measurementerror further deteriorates the accuracy of the approximate V th.

By measuring the total leakage current of all MOSFETs in SRAMarray, the average Vth values in an SRAM array is inferred asshown in the left graph in Fig. 21.5.4. The Vth distribution inSRAM array due to random Vth variation is shown as upper line,and corresponding leakage distribution is also shown as lower line.From the measured average leakage, found by measuring the totalleakage current of the SRAM array, the average value of the Vth

can be calculated by using the standard deviation of random vari-ation and subthreshold swing of a MOSFET. However, by measur-ing only SRAM array leakage does not separate the Vth value ofNMOS and PMOS transistors in the array. To find the relative Vth

values for NMOS and PMOS, Fig. 21.5.4 shows a measurementmethod that uses memory-cell leakage current. By changing thevoltage of the virtual ground (VSSM) of a memory cell (a leakagereduction technique [3]) and measuring the leakage current, thetotal leakage can be broken down into each leakage current,because the change of each leakage current is different as shownin Fig. 21.5.4. When the VSSM voltage is changed from 0V to 0.5V,the leakage current of the PMOS (IL) is reduced by only about half,and that of NMOS (ID, IT) is greatly reduced. When VSSM ischanged from 0V to 0.5V, if the leakage current is greatly reduced,the leakage current of NMOS is dominant and Vth of NMOS is low.On the other hand, if the leakage change is small, the PMOS leak-age is dominant and the Vth of PMOS is low. The changes in mem-ory-cell leakage current corresponding to the process corners areplotted in Fig. 21.5.4. The leakage-current change can be used tomeasure the NMOS and PMOS Vth individually and, in turn, theapplicability of individual reverse body bias to NMOS and PMOSis determined.

Prototype SRAM chips are manufactured (Fig. 21.5.7) in a 65nmlow-power process. The cell size is 0.51mm2. Figure 21.5.5 showsthe leakage measurement results of four 1Mb modules, which arerepresentatives of VBB control patterns. Patterns (A) to (D) corre-spond to areas (A) to (D) in Fig. 21.5.2. A shmoo plot of the worst-performance chip is shown in Fig. 21.5.6. Without VBB control, theSRAM cannot operate even with a high 1.3V VDD; however, when1.2V reverse bias is applied, the SRAM operates correctly with1.0V VDD. The graph on the right shows the failure rate of SRAMcells. When no body bias is applied, the device has fail bits under1.3V VDD. When the body bias is applied to PMOS (VBP), the fail-ure rate is improved. If the body bias is applied to both NMOS andPMOS, the failure rate is not improved. This situation indicatesthat an inappropriate body bias deteriorates the SRAM operatingmargin, and the individual body bias of NMOS and PMOSimproves the SRAM operating margin.

Acknowledgements:We thank Y. Kanno, S. Komatsu, A. Miyanishi, F. Igaue, and K. Yanagisawafor prototype design and valuable discussion; and T. Hattori and N. Irie forproject management.

References:[1] S. Mukhopadhyay, K. Kim, H. Mahmoodi et al., “Self-Repairing SRAMfor Reducing Parametric Failures in Nanoscaled Memory,” Dig. Symp. VLSICircuits, pp. 132-133, Jun. 2006.[2] M. Yabuuchi, K. Nii, Y. Tsukamoto et al., “A 45nm Low-Standby-PowerEmbedded SRAM with Improved Immunity Against Process andTemperature Variations,” ISSCC Dig. Tech. Papers, pp. 326-327, Feb. 2007.[3] M. Yamaoka, Y. Shinozaki, N. Maeda et al., “A 300-MHz 25µA/Mb-Leakage On-Chip SRAM Module Featuring Process-Variation Immunityand Low-Leakage-Active Mode for Mobile-Phone Application Processor,”ISSCC Dig. Tech. Papers, pp. 494-495, Feb. 2004.

978-1-4244-2011-7/08/$25.00 ©2008 IEEE

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ISSCC 2008 / February 5, 2008 / 3:45 PM

Figure 21.5.1: Performance compensation methods for PVT fluctuation inmulti-core SoC.

Figure 21.5.2: Concept of VBB control to improve SRAM cell margins withNMOS and PMOS body bias separately controlled.

Figure 21.5.3: Vth distribution by systematic variation, and difference betweenaverage values of 10 monitoring devices and all MOSFET devices.

Figure 21.5.5: Measured 1Mb cell leakage current of fabricated SRAM arraywith 65nm process and examples of VBB control applicability.

Figure 21.5.6: Shmoo plots and failure rate of worst condition 1Mbit SRAMmodule

Figure 21.5.4: Vth calculating method by measuring SRAM array total leakagecurrent and NMOS/PMOS respective leakage measurement method by virtualground control.

CORE(Logic circuit)

Shared memory(SRAM)

V Boost

VDD

SMON

CORE(Logic circuit)

SMON

CORE(Logic circuit)

SMON

CORE(Logic circuit)

SMONShared memory

(SRAM)

VBB Gen FUSE(P info)

VBP

VBN

SRAM margin:- Balance of nMOS / pMOS- Low local VDD fluctuation(Discoverable and few hot spots)

Logic speed:- Total of nMOS / pMOS Vth variation- Large VDD fluctuation(Everywhere Hot spots)

V Boost

V Boost

V Boost

VBB is easily and effectively used

Using VBB is difficult(Speed deterioration by differencebetween body and source voltage)

V Boost: local power supply boosterSMON: speed monitorFUSE: storing process conditionVBB Gen: body-bias voltage generator

VSSM

VDDM

VBP (VDD Reverse VBB)

VBN (VSS Reverse VBB)BLT BLB

WL

pMOS

ΔΔ ΔΔV t

h(V

)

nMOS ΔΔΔΔVth (V)

Read limit2.6-σ σ σ σ 65-nm

random variation

0.0 0.1 0.2-0.1-0.2

0.0

0.1

0.2

-0.1

-0.2

Read limit5.2-σ σ σ σ 65-nm

random variation

Write limitwith

5.2-σ σ σ σ 65-nmrandomvariation

Write limit2.6-σ σ σ σ 65-nm

randomvariation

OperatingVth window

(B)VBB onlyfor nMOS

(C)VBB onlyfor pMOS

(A)no VBB

(D)VBBto all

-200 mV +200 mV

-200 mV

+200 mV

pMOS ΔΔΔΔVth

nMOSΔΔΔΔVth

> 10 mV 43%> 20 mV 11%> 30 mV 1.8%> 40 mV 0.2%

C

: Average Vth valueof all MOSFETs

: Average Vth value of 10 monitor devices

Vth difference (|Vth_all-Vth_meas|) distribution:

A

B

Chip number

Vth

Gray points (Vth_all)(Average of all MOSFETs

distributed by random var.)

RandomVth variation

Black points (Vth_meas)(Average of 10 MOSFETs

distributed by random var.)

: Vth values of monitoring devices Vth difference

1 2000 4000 6000 8000 10000

V th

diffe

renc

e|V

th_a

ll–V

th_m

eas|

(mV)

010203040506070

1.2V

VSSM0V 0.5V

VDDM=1.2V

BLT=1.2V BLB=1.2V

WL=0V

0V

IL

IDIT

VSSM (V)

FF

FSSFTT

SS0.0 0.2 0.4 0.6 0.8

1

10

100

0.11IT (A.U.)0.051ID (A.U.)0.51IL (A.U.)0.50.0VSSM (V)

Vth distributionin SRAM array

(by random var.)

Subthresholdleakage distribution

(by random var.)

Average ofSRAM array Vth

(Calculated)

Leak

age c

urre

nt (A

.U.)

ln10 * σσσσvth2

S

S: Subthreshold swing

Average ofsubthreshold leakage

(Measured)

σσσσvth: Standard deviation of random variation

Vth

Subthreshold Leakage(Corresponding to Vth)

μμ μμ

μμμμ

μμμμ

μμμμ

μμμμ

Supply voltage, VDD (V)

pMOS

reve

rse b

ody b

ias (V

)

0.0

-0.6

-1.2

0.9 1.0 1.1 1.2 1.3

P P P P

P P

Supply voltage, VDD (V)

Failu

re ra

te (%

)

0.0

0.01

0.8 0.9 1.0 1.1 1.2 1.3

0.02

0.03

0.04

0.05

VBP=VDD+1.2V

VBP=VDD+0.6V

no body bias

VBN=-0.6VVBP=VDD+0.6V

21

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622 • 2008 IEEE International Solid-State Circuits Conference 978-1-4244-2011-7/08/$25.00 ©2008 IEEE

ISSCC 2008 PAPER CONTINUATIONS

Figure 21.5.7: Chip micrograph.

16kB Array 16kB Array

16kB Array 16kB Array

16kB Array 16kB Array

16kB Array 16kB Array

128kB Module

1.5mm

0.9mm

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