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Advance program of the 65th ECTC.

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Page 1: 65th ECTC Advance Program
Page 2: 65th ECTC Advance Program

On behalf of the Program Committee and Executive Committee, it is my pleasure to invite you to join us for the IEEE 65th Electronic Components and Technology Conference (ECTC) which will be held at the Sheraton San Diego Hotel & Marina in San Diego, California, USA, from May 26–29, 2015. This premier international conference is sponsored by the IEEE Components, Packaging, and Manufacturing Technology (CPMT) Society.

The ECTC Program Committee has selected over 350 papers which will be presented in 36 oral sessions and five interactive presentation sessions including one student interactive presentation session. The oral sessions will feature selected papers on 3D and TSV technologies, wafer level packaging, electrical and mechanical modeling, RF packaging, system design, and optical interconnects. Session topics will cover advanced packaging technologies, material development and characterization, reliability, assembly and manufacturing, and power & signal integrity. Four interactive presentation sessions showcase papers in a format that encourages more in-depth discussion and interaction with authors about their work. Similarly, the student interactive presentation session will focus on the research being done at academic institutions around the world by emerging scientists and engineers. The Program Committee has created sessions which cover the ongoing technological challenges of established disciplines as well as addressing emerging topics of interest to the industry. Authors from companies, research institutions, and universities from over 25 countries will present their work at ECTC, illustrating the conference’s global focus.

ECTC will also feature panel and special sessions with industry experts covering a number of important and emerging topic areas. On Tuesday, May 26 at 10 a.m., Ibrahim Guven will chair a session entitled “Sustainability in Microelectronics” where a panel of experts will discuss technical and business challenges and opportunities for this important “green” aspect of our industry. Tuesday at 2 p.m., Shawn Shi and John Knickerbocker will chair a special session sponsored jointly by the Assembly & Manufacturing Technology and Advanced Packaging Subcommittees on “Advancements in Bio-Medical Technology & Associated Packaging”. I am happy to announce that this year on Tuesday at 4 p.m., 65th ECTC General Chair Dr. Beth Keser will chair a “CPMT Women’s Panel and Reception” featuring a panel of women in distinguished technical and management roles in our industry including the current CPMT President Dr. Jie Xue. All conference attendees are invited. On Tuesday evening at 7:30 p.m., the ECTC Panel Discussion “Nanopackaging: Hype, Hope, or Happening?” will be chaired by James Morris and Jie Xue and features panelists from various segments of the industry and academia to discuss the application of nanotechnologies to electronics systems and packaging. Jan Vardaman will chair the ECTC Plenary Session titled “The Internet of Things and the Future of Interconnected Electronics” on Wednesday evening, May 27 at 7 p.m. where a panel of experts will discuss the emerging IoT and its anticipated impact on our lives and businesses. On Thursday evening at 8 p.m. the CPMT Seminar

titled “Liquid and Phase-Change Cooling for High-Performance Systems” will be moderated by Venky Sundaram and Yasumitsu Orii.

Supplementing the technical program, ECTC will also offer several Professional Development Courses (PDCs) and the Technology Corner exhibits. ECTC will offer 16 PDCs for 2015, covering a wide array of technical areas and organized by the PDC Committee chaired by Kitty Pearsall. The PDCs will take place on Tuesday morning and afternoon and are taught by distinguished experts in their respective fields. The Technology Corner will showcase the latest products and technologies offered by leading companies in the electronic components, materials, packaging, and services fields. The more than 100 Technology Corner exhibits will be open Wednesday and Thursday starting at 9 a.m. ECTC also offers attendees numerous opportunities for networking and discussion with colleagues during coffee breaks, daily luncheons, and nightly receptions. I am also pleased to announce that Matthew Grob, Executive Vice President and CTO of Qualcomm Technologies, Inc., will be the invited keynote speaker at the ECTC Luncheon on Wednesday.

Whether you are an engineer, a scientist, a manager, a student, or an executive, ECTC offers something for everyone in the packaging industry. I invite you to make your plans now to join us for the 65th ECTC and be a part of the exciting technical and professional opportunities. I also want to take this opportunity to thank our sponsors, exhibitors, authors, speakers, PDC instructors, session chairs, program committee members, as well as all the volunteers who help to make the 65th ECTC another success. I look forward to meeting you in San Diego, May 26–29, 2015.

Henning Braunisch65th ECTC Program ChairIntel CorporationPhone: +1-480-552-0844Email: [email protected]

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IndexECTC Registration ................................................................ 3, 29, 30General Information ............................................................................3Hotel Information .........................................................................3, 292015 ECTC Special Session ...............................................................42015 Technical Subcommittee Special Session ...............................42015 ECTC Panel Session ...................................................................42015 ECTC Plenary Session ..............................................................42015 CPMT Seminar ............................................................................5ECTC Luncheon Keynote Speaker ....................................................5Luncheons and Receptions ................................................................52015 CPMT Women’s Panel and Reception ...................................5Executive and Program Committees ............................................6-7Professional Development Courses ...........................................8-13Area Attractions ............................................................................... 13Program Sessions .........................................................................14-292015 Technology Corner Exhibits ................................................. 29Conference Overview ..................................................................... 31

The 65th Electronic Components and Technology Conference (ECTC)Sheraton San Diego Hotel & Marina, San Diego, California, USA • May 26 - 29, 2015

INTRODUCTION FROM THE 65TH ECTC PROGRAM CHAIR HENNING BRAUNISCH

Page 3: 65th ECTC Advance Program

Advance RegistrationOnline registration is available at www.ectc.net. For more information on registration rates, terms, and conditions see page 30.

Register early … save $100 or more!

All applications received after May 8, 2015 will be considered Door Registrations. Those who register in advance can pick up their registration packets at the ECTC Registration Desk in the Bayview Foyer.

On-Site Registration Schedule

Registration will be held in the Bayview Foyer on the Lobby Level.Monday, May 25, 2015 3:00 p.m. to 5:00 p.m. Tuesday, May 26, 2015 6:45 a.m. to 5:00 p.m.* *6:45 a.m. to 8:00 a.m. ( a.m. PD Courses & Special Morning Session Only)

Wednesday, May 27, 2015 6:45 a.m. to 4:00 p.m. Thursday, May 28, 2015 7:30 a.m. to 4:00 p.m.Friday, May 29, 2015 7:30 a.m. to 12:00 noon

General Information

Conference organizers reserve the right to cancel or change the program without prior notice. The Sheraton San Diego Hotel and Marina, as well as the ECTC, are both smoke free environments.

Loss Due to Theft

Conference management is not responsible for loss or theft of personal belongings. Security for each individual’s belongings is the individual’s responsibility.

ECTC SponsorsWith 64 years of history and experience behind us, ECTC is recognized as the premier semiconductor packaging conference and offers an unparalleled opportunity to build relationships with more than 1,000 individuals and organizations committed to driving innovation in semiconductor packaging.

We have a limited number of sponsorship opportunities in a variety of packages to help you get your message out to attendees. These include Gala, Program, Internet Interface, and several other sponsorship options that can be customized to your company’s interest.

If you would like to enhance your presence at ECTC and increase your impact with a sponsorship, please take a look at our sponsorship brochure on the website www.ectc.net under “Sponsors”.

To sign-up for sponsorship, or to get more details, please contact David McCann at

[email protected] or +1-518-222-6128.

Hotel Accommodations

Rooms for ECTC attendees have been reserved at the Sheraton San Diego Hotel and Marina. The special conference rate for a single/double occupancy room is:

US$189.00 per nightThis price includes single or double occupancy in one room.

Please note these rooms are on a first come, first serve basis. If the conference rate is no longer available, attendees will be offered the next best price available.

Room reservations must be made directly with the hotel by May 1, 2015 to ensure our preferred conference rate. All reservations made after the cutoff date of May 1, 2015 at 5 p.m. Pacific Time will be accepted on a space and rate availability basis. If you need to cancel a reservation, please do so AT LEAST 5 days before arrival for a full refund. In the event that you check into the Sheraton San Diego Hotel and Marina and check out prior to your scheduled check out date, you will be charged a US$100 early departure fee. To avoid this fee, you must advise the hotel at or before check-in. Check-in time: 3 p.m. & check-out time: 12 noon.

Note about Hotel Reservations

Attendees should note that only reputable sites should be used to book a hotel room for the 2015 ECTC. Be advised that you may receive emails about booking a hotel room for ECTC 2015 from 3rd party companies. These emails and sites are not to be trusted. The only formal communication ECTC will convey about hotel rooms will come in the form of ECTC e-blasts or ECTC emails from our Executive Committee. ECTC’s only authorized site for reserving a room is through our website (www.ectc.net). You may, however, use other trusted sites that you personally have used in the past to book travel. Please be advised, there are scam artists out there and if it’s too good to be true it likely is. Should you have any questions about booking a hotel room please contact ECTC staff at: [email protected]

Transportation Services

Enjoy the free shuttle transportation, which runs every 15 minutes, between the East and West Towers as well as the San Diego International Airport. Look for the gray, white, and blue vans!

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The above schedule for Tuesday will be rigorously enforced to prevent students from being late for their courses.

65th ECTC ADVANCE REGISTRATION

Page 4: 65th ECTC Advance Program

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2015 ECTC Special Session

Sustainability in MicroelectronicsTuesday, May 26, 2015 • 10:00 a.m. – 11:30 a.m.

Chair: Ibrahim Guven – Virginia Commonwealth University

Sustainability in the electronics industry has evolved from being a regulation and compliance issue to a competitive advantage. Sustainability in electronics has numerous fac-ets ranging from practices that help reduce cost through energy efficiency to seemingly costly ethical and environ-mental considerations. The cost-saving practices include increasing efficiency, reducing waste, and minimizing use of water and energy in manufacturing and distribution. Currently, our industry is using considerable resources to address ecological footprint concerns. While expensive at the beginning, taking steps towards more

environmentally friendly practices in fact helps the electronics industry by building and improving their brands. In this special session, experts from the industry and academe will share their thoughts and experiences on the complex issue of sustainability from a wide variety of perspectives. Topics to be covered include data center and performance computing efficiency, conflict minerals, responsible sourcing and supply chain, design for reuse and recycling, sustainable operation, product ecology, and collaborative efforts within the electronics industry.

1. William Bullock – University of Illinois at Urbana-Champaign2. Karen Butner – IBM Corporation3. Corey Gough – Intel Corporation4. Michelle Lee – Qualcomm Technologies, Inc. 5. Michael Pierce – Texas Instruments

2015 Assembly & Manufacturing Technology

and Advanced Packaging Special SessionAdvancement in Bio-Medical Technology

& Associated Packaging Tuesday, May 26, 2015 • 2:00 p.m. – 3:30 p.m.

Chairs: Shawn Shi – Medtronic and John Knickerbocker – IBM Corporation

Life-science technology has been advancing at an accelerating pace. New therapies and medicine have brought solutions to many hard to treat diseases. A paradigm shift is beginning from disease treatment to disease prevention and from visit-based compensation to outcome-based compensation, which may offer healthcare cost reduction and quality-of-life improvement. Bio-medical technology and associated packaging has been growing business value in the industry and has great potential to change the healthcare industry with personalized healthcare, healthcare monitoring, data analysis, and disease prevention. The panelists will discuss the major challenges as well as share their vision on the possible pathways towards solutions. The panel topics include advancement of battery technology for medical device applications, electronic packaging challenges in the medical device industry, tomorrow’s implantable electronics and brain implants for disease prevention and monitoring, and trends and challenges of wearable medical electronics and sensors. We all should begin to learn how to ride the revolutionary wave of healthcare paradigm shifts from disease treatment to disease prevention and from visit-based compensation to outcome-based compensation. The panelists include distinguished experts from both industry and academic institutions.

1. Gaurav Jain – Medtronic2. Gabriel Mouchawar – St. Jude Medical, Inc.3. Kendall Lee – Mayo Clinic4. Joseph Wang – University of California, San Diego5. Kaustubh Nagarkar – General Electric6. Kent Dicks – Alere Connect

2015 ECTC Panel Session

Nanopackaging: Hype, Hope, or Happening?Tuesday, May 26, 2015 • 7:30 p.m. – 9:00 p.m.

Chairs: James E. Morris – Portland State University and Jie Xue – CPMT President; Cisco Systems, Inc.

Nanopackaging can refer either to the packaging of nanoelectronic devices or to the application of nano-technologies to electronics systems and packaging. Much of ECTC covers the former, now that nanoscale CMOS has been ubiquitous for over a decade and nanoscale device packaging proceeds inexorably as the mainstream. But what of the latter definition? Nanotechnologies have been systematically developed in academic laboratories, some of which even look at packaging applications, but the panel will take a primarily industrial view of the status quo and near future of nanotechnologies in micro-electronics packaging, including nanoparticles, carbon nanotubes, graphene, and more—with a wee peek into the post-CMOS future.

1. Alexander Balandin – University of California, Riverside2. Taisuke Iwai – Fujitsu Laboratories3. Nancy Iwamoto – Honeywell4. James Matayabas, Jr. – Intel Corporation5. Anton Miric – Heraeus Materials6. Thomas Rueckes – Nantero

2015 ECTC Plenary Session

The Internet of Things and the Future of Interconnected Electronics

Wednesday, May 27, 2015 • 7:00 p.m. – 8:30 p.m.Chair: E. Jan Vardaman – TechSearch International, Inc.

IEEE defines “The Internet of Things” (IoT) as a self-configuring and adaptive system consisting of networks of sensors and smart objects whose purpose is to interconnect “all” things, including every day and indus-trial objects, in such a way as to make them intelligent, programmable and more capable of interacting with oth-ers. Smart devices are expected to collect data, transmit and/or process information. IoT includes an increasing number of MEMS and sensors, but it is more than just a sensing function. It includes the infrastructure of data collection and processing that goes with these functions. Does IoT mean totally new products? Yes and no.

Obviously, it means more sensors, wireless chips, and processors. Of course it includes existing mobile devices such as smartphones and tablets, intelligent cars with enhanced driving and safety features, and emerging wearable electronics products such as activity monitoring cameras, wrist products, and other clothing, and it probably includes devices that are still an inventor’s dream. This panel brings together a panel of technology and business leaders to help understand the true impact of IoT on the way we live, do busi-ness, design and fabricate our semiconductor products, and assemble them. Challenges in the expansion of IoT will be discussed as well.

1. Jerry Tzou – Taiwan Semiconductor Manufacturing Company Ltd. (TSMC)2. Tao Zhang – Cisco Systems, Inc. 3. Ilyas Mohammed – Jawbone4. Chris Matthieu – Octoblu, Inc.5. Subramanian Iyer – IBM Corporation

These sessions are open to all conference attendees.

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General Chair’s Speakers ReceptionTuesday, May 26, 2015 • 6:00 p.m. - 7:00 p.m.

(by invitation only)

ECTC Student ReceptionTuesday, May 26, 2015 • 5:00 p.m. - 6:00 p.m.

Hosted by IBM CorporationStudents, have you ever wondered what career opportunities exist in the industry and how you could use your technical skills and innovative talent? If so, you are invited to attend the ECTC Student Reception, where you will have the opportunity to talk to industry professionals about what helped them be successful in their first job search and reach their current positions. You will have the chance to enjoy good food and network with industry leaders and achievers. Don’t miss the opportunity to interact with people that you might not have the chance to meet otherwise! Sponsored by the IBM Corporation.

Exhibitor Reception Wednesday, May 27, 2015 • 5:30 p.m. - 6:30 p.m.

65th ECTC Gala ReceptionThursday, May 28, 2015 • 6:30 p.m.

All badged attendees and their guests are invited to attend a reception hosted by Gala Reception sponsors.

LUNCHEONSTuesday PDC LuncheonAll individuals attending a PDC are invited to join us for lunch. Proctors and instructors are welcome, too!

Wednesday Conference LuncheonPlease be sure not to miss our Wednesday luncheon with guest speaker Matthew Grob, Executive Vice President and CTO of Qualcomm Technologies, Inc. All conference attendees are welcome!

Thursday CPMT LuncheonOur sponsor, the IEEE Components, Packaging and Manufacturing Technology Society, will be sponsoring lunch on Thursday for all conference attendees!

Friday Program Chair LuncheonPlease attend Friday’s lunch hosted by the 65th ECTC Program Chair. We will honor conference paper award recipients and raffle off a vast array of prizes including a hotel stay, free conference registrations, and many other attractive items!

ECTC Luncheon Keynote SpeakerSmartphone-Powered Future

Wednesday, May 27, 2015 • 12:00 Noon

Presenter: Matthew Grob Executive Vice President and Chief Technology Officer

Qualcomm Technologies, Inc.

With sales expected to reach more than 8 billion units over the next five years, smartphones are not only ubiquitous, they are a major source of technology innovation worldwide. The massive popularity of smartphones, combined with rapid replacement cycles, is driving the pace of technology innovations that benefit many other high-tech devices, ranging from tablets, cars, smartwatches, and health sensors, to robots and drones. Matt Grob, Executive Vice President

& Chief Technology Officer of Qualcomm Technologies, Inc. will discuss how smartphone technology is driving this innovation and extending the boundaries of what’s possible.

In the role of EVP & CTO of Qualcomm Technologies, Inc., Matt Grob is responsible for the oversight of Qualcomm’s technical path, the coordination of R&D activities across the company, and the development of next-generation wireless technologies. He also directs the Company’s broad portfolio of research projects with topics ranging from 3G HetNets to small cells. In addition, Matt leads Qualcomm Research and Qualcomm Corporate Engineering Services, and he is a member of Qualcomm’s executive committee.

Matt joined Qualcomm in 1991 as an engineer. In 1998, Matt was promoted to lead the Company’s R&D system engineering group and in 2006, he became in charge of Qualcomm Research. Matt holds a Master of Science in electrical engineering from Stanford University and a Bachelor of Science in electrical engineering from Bradley University. He is a member of the IEEE and holds more than 70 patents.

2015 CPMT SeminarLiquid and Phase-Change Cooling

for High-Performance SystemsThursday, May 28, 2015 • 8:00 p.m. – 9:30 p.m.

Chairs: Venky Sundaram – Georgia Institute of Technology and Yasumitsu Orii – IBM Research Tokyo

Thermal management has been one of the critical technologies for developing high-performance systems from the early age of computers. In current high-end and future systems, IC interconnect density must be significantly advanced such as in 3D packaging systems, so it is not an exaggeration to say that cooling capability will determine system performance the same as power efficiency. In this seminar, cutting edge cooling technolo-gies, namely applied liquid and phase-change technolo-gies, will be discussed from the user perspective. Also, novel thermally conductive materials will be discussed from the vendor’s view.

1. Jie Wei – Fujitsu2. Hitoshi Sakamoto – NEC Corporation3. Kousuke Suzuki – Dai Nippon Printing Co., Ltd.4. Yasuhiro Kawase – Mitsubishi Chemical Corporation

2015 CPMT Women’s Panel and Reception

Own Your Professional Success – What You Should Do

Tuesday, May 26, 2015 • 4:00 p.m. – 5:00 p.m.Chair: Beth Keser, Ph.D. – 65th ECTC General Chair

Qualcomm Technologies, Inc.

CPMT Society President Jie Xue and 65th ECTC General Chair Beth Keser cordially invite all ECTC attendees to attend our first Women’s Panel and Recep-tion sponsored by CPMT. The three panelists will speak on their experiences and achievements in the microelectronics industry and provide insights into how they have cultivated successful careers. A Q&A session and reception for panelists and attendees will follow.

1. Jie Xue, Ph.D. – CPMT President; Sr. Director, Component Quality and Technology Group, Cisco Systems, Inc.2. Jean Trewhella – Director of Packaging, GLOBALFOUNDRIES3. Navrina Singh – Director, Product Management, Qualcomm Labs, Inc.

iNEMI Technical & Research Committee Meetings

Tuesday, May 26, 2015 • 9:00 a.m. – 5:00 p.m.By invitation only

Page 6: 65th ECTC Advance Program

2015 ExecutiveCommitteeGeneral Chair Beth Keser Qualcomm Technologies, Inc. [email protected] +1-858-658-3332

Vice-General Chair Alan Huffman RTI International [email protected] +1-919-248-9216

Program Chair Henning Braunisch Intel Corporation [email protected] +1-480-552-0844

Assistant Program Chair Sam Karikalan Broadcom Corporation [email protected] +1-949-926-7296

Arrangements Chair Lisa Renzi Renzi & Company, Inc. [email protected] +1-703-863-2223

Professional Development Course Chair Kitty Pearsall Boss Precision, Inc. [email protected] +1-512-845-3287

Finance Chair Patrick Thompson Texas Instruments, Inc. [email protected] +1-214-567-0660

Publications Chair Steve Bezuk Qualcomm Technologies, Inc. [email protected] +1-858-651-2770

Publicity Chair Eric Perfecto IBM Corporation [email protected] +1-845-894-4400

CPMT Representative C. P. Wong Georgia Institute of Technology [email protected] +1-404-894-8391

Web Administrator Mark D. Poliks i3 Electronics, Inc. [email protected] +1-607-727-7104

Sr. Past General Chair ECTC David McCann GLOBALFOUNDRIES [email protected] +1-518-222-6128

Jr. Past General Chair ECTC Wolfgang Sauter IBM Corporation [email protected] +1-802-922-3083

Treasurer Tom Reynolds T3 Group LLC [email protected] +1-850-897-7323

Exhibits Chair Joe Gisler Vector Associates [email protected] +1-480-288-6660

Sponsorship Chair David McCann GLOBALFOUNDRIES [email protected] +1-518-222-6128

2015 ProgramCommittee Advanced Packaging Chair Christopher Bower X-Celeprint Ltd. [email protected] +1-919-522-3230

Assistant Chair Rozalia Beica Yole Developpement [email protected]

Aleksandar Aleksov Intel Corporation

Muhannad Bakir Georgia Institute of Technology

Daniel Baldwin Engent, Inc.

Omar Bchir Qualcomm Technologies, Inc.

Jianwei Dong Dow Electronic Materials

Altaf Hasan Intel Corporation

Erik Jung Fraunhofer IZM

Beth Keser Qualcomm Technologies, Inc.

Young-Gon Kim IDT

John Knickerbocker IBM Corporation

John H. Lau ASM Pacific Technology

Markus Leitgeb AT&S

Dean Malta RTI International

Raj N. Master Microsoft Corporation

Luu T. Nguyen Texas Instruments Inc.

Deborah S. Patterson Principal, Patterson Group

Raj Pendse STATS ChipPAC, Inc.

Eric Perfecto IBM Corporation

Peter Ramm Fraunhofer EMFT

Subhash L. Shinde Sandia National Laboratory

Joseph W. Soucy Draper Laboratory

E. Jan Vardaman TechSearch International, Inc.

Applied Reliability Chair Scott Savage Medtronic Microelectronics Center [email protected] +1-480-303-4749

Assistant Chair Vikas Gupta Texas Instruments, Inc. [email protected] +1-214-567-3160

Jo Caers Royal Philips

Sridhar Canumalla Microsoft Corporation

Tim Chaudhry Broadcom Corporation

Tz-Cheng Chiu National Cheng Kung University

Darvin R. Edwards Edwards Enterprises

Deepak Goyal Intel Corporation

Dongming He Qualcomm Technologies, Inc.

Toni Mattila Aalto University

Keith Newman Hewlett-Packard Company

Donna M. Noctor Siemens Industry, Inc.

John H. L. Pang Nanyang Technological University

S. B. Park Binghamton University

Lakshmi N. Ramanathan Microsoft Corporation

Ephraim Suhir University of California, Santa Cruz

Jeffrey Suhling Auburn University

Dongji Xie NVIDIA Corporation

Assembly & Manufacturing Technology Chair Shawn Shi Medtronic Corporation [email protected] +1-480-929-5614

Assistant Chair Valerie Oberson IBM Corporation, Canada Ltee [email protected] +1-450-534-7767

Sai Ankireddi Maxim Integrated Products, Inc.

Sharad Bhatt Shanta Systems, Inc.

Claudius Feger IBM Corporation

Mark Gerber Consultant

Paul Houston Engent

Sa Huang Medtronic Corporation

Li Jiang Texas Instruments, Inc.

Vijay Khanna IBM Corporation

Chunho Kim Medtronic Corporation

Wei Koh Pacrim Technology

Choon Heung Lee Amkor Technology

Mali Mahalingam Freescale Semiconductor, Inc.

Debendra Mallik Intel Corporation

Jae-Woong Nah IBM Corporation

Hirofumi Nakajima Consultant

Tom Poulin Aerie Engineering

Shichun Qu Philips

Tom Swirbel Motorola, Inc.

Paul Tiner Texas Instruments, Inc.

Sean Too Microsoft Corporation

Andy Tseng JSR Micro

Shaw Fong Wong Intel Corporation

Jie Xue Cisco Systems, Inc.

Jin Yang Intel Corporation

Tonglong Zhang Nantong Fujitsu Microelectronics Ltd.

High-Speed, Wireless & Components Chair Nanju Na Xilinx [email protected] +1-408-879-5574

Assistant Chair Prem Chahal Michigan State University [email protected] +1-517-355-0248

Amit P. Agrawal Cisco Systems, Inc.

Eric Beyne IMEC

Craig Gaw Freescale Semiconductor, Inc.

Apostolos Georgiadis Centre Tecnologic de Telecomunicacions de Catalunya (CTTC)

Abhilash Goyal Oracle

Rockwell Hsu Cisco Systems, Inc.

Lih-Tyng Hwang National Sun Yat-Sen University

Mahadevan K. Iyer Texas Instruments, Inc.

Timothy G. Lenihan TGL Consulting

Li Li Freescale Semiconductor, Inc.

Sebastian Liau ITRI

Lianjun Liu Freescale Semiconductor, Inc.

Andrea Paganini IBM Corporation

Albert F. Puttlitz Mechanical Eng. Consultant

P. Markondeya Raj Georgia Institute of Technology

Luca Roselli University of Perugia

Clemens Ruppel TDK

Hideki Sasaki Renesas Electronics Corporation

Li-Cheng Shen Quanta Research Institute

Manos M. Tentzeris Georgia Institute of Technology

Frank Theunis Qualcomm Technologies Netherlands B.V.

Leena Ukkonen Tampere University of Technology

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Emerging Technologies Chair C. S. Premachandran GLOBALFOUNDRIES [email protected] +1-518-305-7317

Assistant Chair Rabindra N. Das MIT Lincoln Labs [email protected] +1-781-981-1318

Isaac Robin Abothu Siemens Medical Solutions USA Inc.

Jai Agrawal Purdue University

Vasudeva P. Atluri Renavitas Technologies

Mark Bachman University of California, Irvine

Karlheinz Bock Technische Universitat Dresden

Vaidyanathan Chelakara Ciena Corporation

John Cunningham Oracle

Steve Greathouse Plexus Corporation

Kevin J. Lee Intel Corporation

Joana Maria IBM Corporation

Goran Matijasevic University of California, Irvine

Shah Milind Qualcomm Technologies, Inc.

Dave Peard Henkel Corporation

Koneru Ramakrishna Hewlett-Packard Company

Jintang Shang Southeast University

Nancy Stoffel GE Global Research

Vivek Subramanian University of California

Klaus-Jürgen Wolter Technische Universität Dresden

Allison Xiao Henkel Corporation

Jimin Yao Intel Corporation

Interconnections Chair Li Li Cisco Systems, Inc. [email protected] +1-408-527-0801

Assistant Chair Changqing Liu Loughborough University [email protected] +44-1509-227681

William Chen Advanced Semiconductor Engineering, Inc.

Kathy Cook Ziptronix

Rajen Dias Intel Corporation

Bernd Ebersberger Intel Mobile Communications

Takafumi Fukushima Tohoku University

Tom Gregorich Micron Technology, Inc.

Wei-Chung Lo ITRI

Nathan Lower Rockwell Collins, Inc.

James Lu Rensselaer Polytechnic Institute

Voya Markovich Microelectronic Advanced Hardware Consulting, LLC

James E. Morris Portland State University

Lou Nicholls Amkor Technology, Inc.

Gilles Poupon CEA-LETI

Katsuyuki Sakuma IBM Corporation

Lei Shan IBM Corporation

Katsuaki Suganuma Osaka University

Chuan Seng Tan Nanyang Technological University

Matthew Yao GE Energy Management

Materials & Processing Chair Diptarka Majumdar Superior Graphite [email protected] +1-919-418-8025

Assistant Chair Bing Dang IBM Corporation [email protected] +1-914-945-1568

Tanja Braun Fraunhofer IZM

Choong Kooi Chee KBU International College

Tim Chen Darbond Technology Co., Ltd.

Yu-Hua Chen Unimicron

C. Robert Kao National Taiwan University

Dong Wook Kim Qualcomm Technologies, Inc.

Chin C. Lee University of California, Irvine

Yi Li Intel Corporation

Kwang-Lung Lin National Cheng Kung University

Daniel D. Lu Henkel Corporation

Hongxia Lu Intel Corporation

Hongtao Ma Lightera Corporation

Mikel Miller Draper Laboratory

Kyung-Wook Paik KAIST

Mark D. Poliks i3 Electronics, Inc.

Dwayne Shirley Qualcomm Technologies, Inc.

Ivan Shubin Oracle

Yoichi Taira IBM Corporation, Japan

Lejun Wang Qualcomm Technologies, Inc.

Frank Wei Disco Japan

Myung Jin Yim Intel Corporation

Tieyu Zheng Microsoft Corporation

Modeling & Simulation Chair Yong Liu Fairchild Semiconductor Corporation [email protected] +1-207-761-3155

Assistant Chair Dan Oh Altera Corporation [email protected] +1-408-544-8103

Kemal Aygun Intel Corporation

Wendem Beyene Rambus Inc.

Zhaoqing Chen IBM Corporation

Kuo-Ning Chiang National Tsinghua University

Daniel de Araujo Mentor Graphics

Xuejun Fan Lamar University

Xiaoxiong (Kevin) Gu IBM Corporation

Woopoung Kim Qualcomm Technologies, Inc.

Bruce Kim City University of New York

Pradeep Lall Auburn University

Sheng Liu Huazhong University of Science and Technology

En-Xiao Liu Institute of High Performance Computing, A*STAR

Erdogan Madenci University of Arizona

Tony Mak Wentworth Institute of Technology

Gamal Refai-Ahmed PreQual Technologies Corp.

Sandeep Sane Intel Corporation

Jaemin Shin Samsung Electronics Co., Ltd.

Suresh K. Sitaraman Georgia Institute of Technology

G. Q. (Kouchi) Zhang Delft University of Technology (TUD)

Optoelectronics Chair Stefan Weiss II-VI Laser Enterprise GmbH [email protected] +41-44-455-8732

Assistant Chair Hiren Thacker Oracle [email protected] +1-858-526-9442

Fuad Doany IBM Corporation

Gordon Elger Technische Hochschule Ingolstadt

Z. Rena Huang Rensselaer Polytechnic Institute

Takaaki Ishigure Keio University

Soon Jang ficonTEC USA

Harry G. Kellzi Teledyne Microelectronic Technologies

Michael Leers Laserline GmbH

Masanobu Okayasu Oclaro Japan, Inc.

Kannan Raj Oracle

Alex Rosiewicz Gooch & Housego

Henning Schroeder Fraunhofer IZM

Andrew Shapiro JPL

Masao Tokunari IBM Corporation

Jean Trewhella GLOBALFOUNDRIES

Shogo Ura Kyoto Institute of Technology

Ping Zhou LDX Optronics, Inc.

Interactive Presentations Chair Ibrahim Guven Virginia Commonwealth University [email protected] +1-804-827-3652

Assistant Chair Michael Mayer University of Waterloo [email protected] +1-519-888-4024

Rao Bonda Amkor Technology

Mark Eblen Kyocera America, Inc.

John Hunt ASE US Inc.

Nam Pham IBM Corporation

Mark D. Poliks i3 Electronics, Inc.

Nancy Stoffel GE Global Research

Patrick Thompson Texas Instruments, Inc.

Professional Development Courses Chair Kitty Pearsall Boss Precision, Inc. [email protected] +1-512-845-3287

Assistant Chair Jeffrey Suhling Auburn University [email protected] +1-334-844-3332

Eddie Kobeda IBM Corporation (retired)

Al Puttlitz Consultant

Page 8: 65th ECTC Advance Program

PROFESSIONAL DEVELOPMENT

COURSESTuesday, May 26, 2015

Kitty Pearsall, ChairBoss Precision, Inc.

[email protected]+1-512-845-3287

Jeff Suhling, Assistant ChairAuburn University

[email protected]+1-334-844-3332

MORNING COURSES8:00 a.m. – 12:00 Noon

1. ACHIEVING HIGH RELIABILITY OF LEAD-FREE SOLDER JOINTS – MATERIAL CONSIDERATIONSCourse Leader: Ning-Cheng Lee – Indium Corporation

Course Objectives:This course covers the detailed material considerations required for achieving high reliability for lead-free solder joints. The reliability discussed includes joint mechanical properties, development of type and extent of intermetallic compounds (IMCs) under a variety of material combinations and aging conditions, and how those IMCs affect the reliability. Failure modes (thermal cycling reliability, fragility of solder joints as a function of material combination, thermal history, and stress history) will be addressed in detail, and novel alloys with reduced fragility will be presented. Electromigration, corrosion, and tin whisker growth will also be discussed. Furthermore, the reliability of through hole solder joints will be reviewed and recommendations will be provided, particularly for thick boards. The emphasis of this course is placed on the understanding of how the various factors contributing to the failure modes, and how to select proper solder alloys and surface finishes for achieving high reliability. Also presented are the desirable future alloys and fluxes in order to meet the challenge of miniaturization.

Course Outline: 1. Implementation Status

2. Prevailing Materials – Alloys and Finishes

3. Surface Finishes Issues – ENIG, Immersion Ag, and Immersion Sn

4. Mechanical Properties – Shear, Pull, and Creep

5. Intermetallic Compounds – Effect of Cu, Ni, Other Additives, and Heat History

6. Failure Modes – Grain Deterioration, Orientation, Mixed Alloys, and Interfacial Voiding

7. Thermal Cycle Reliability – Effect of Cycling Condition, Surface Finishes, and Reflow Temperature

8. Reliability of Through-Hole Joints – Large and Thick Boards, Partially Filled Through-Holes

9. Fragility – Effect of Surface Finishes, Alloys, Reflow, Strain Rate, Aging, Cycling, and IMCs

10. Electromigration – Effect of Current Density, Back Stress, and Cu UBM Thickness

11. Corrosion – SAC and Performance of Surface Finishes Under Harsh Conditions

12. Tin Whiskers – Causes of Formation, Methods for Control

Who Should Attend:Anyone interested in achieving high reliability lead-free solder joints should take this course.

2. FAN-OUT WAFER LEVEL PACKAGINGCourse Leader: Beth Keser – Qualcomm Technologies, Inc.

Course Objectives:Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 5 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, lead-frames, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces, package structures available in the industry, process flows, material challenges, design rule roadmap, reliability, and benchmarking.

Course Outline:1. Current Challenges in Packaging

2. Definition and Advantages

3. Applications

4. Package Structures

5. Process

6. Material Challenges

7. Equipment Challenges

8. Design Rule Roadmap

9. Reliability

10. Benchmarking

Who Should Attend:Engineers and managers responsible for advanced packaging development, package characterization, package quality, package reliability, and package design should attend this course. Both newcomers and experienced practitioners are welcome.

3. PACKAGE FAILURE ANALYSIS - FAILURE MECHANISMS AND ANALYTICAL TOOLSCourse Leaders: Rajen Dias and Deepak Goyal – Intel Corporation

Course Objectives:The technical course will provide an overview of the failure modes and mechanisms observed in organic packages. A brief introduction to the methodology of failure analysis of these packages will be described. The focus of the course will be on package failure mechanisms highlighted by case studies and on analytical tools and techniques currently used and the future direction for the tools and techniques required for successful and timely failure analysis of next generation package technologies. A discussion on the strategies for use of these techniques and a flow chart for failure analysis will be included.

Course Outline:1. Package Technology – Trends, Drivers &

Challenges

2. Failure Analysis Challenges Offered by Package Technology Roadmap

3. Introduction to the Methodology of Failure Analysis of Organic Packages

4. Current Analytical Capabilities for Package Fault Isolation and Failure Analysis

5. Strategies to Use These Techniques to Identify Failures and Understand Failure Mechanisms

6. Analytical Capabilities to Support Next Generation Packaging Technologies

7. Typical Failure Analysis Flow Charts for Opens and Shorts

8. Failure Modes/Mechanisms Including Chip/Package Interactions, 1st/2nd Level Interconnections and Package/Board Substrates

9. Failure Analysis Case Studies

Who Should Attend:Engineers and technical managers who are involved in package technology development, reliability assessment of packages, and failure analysis should attend.

8

IMPORTANT NOTICEIt is extremely important to register

in advance to prevent delays atdoor registration. Course sizes

are limited.

Page 9: 65th ECTC Advance Program

4. NEXT FRONTIER IN ELECTRONICS: SYSTEMS SCALING FOR SMALL AND ULTRA-SMALL SMART MOBILE, WEARABLE, MEDICAL, AND IOP SYSTEMSCourse Leader: Rao R. Tummala – Georgia Institute of Technology

Course Objectives:Transistor scaling, starting with the invention of the transistor in 1949, made electronics the largest single, $1.5T global industry, serving a variety of individual industries that span computing, communications, consumer, automotive, and others. The basis for this industry is a result of singular focus in transistor scaling, leading to a 5B transistor chip, involving dozens of semiconductor companies around the globe. But the electronics landscape is changing, driven by a new industry that integrates all these individual industries into so-called “Smart Mobile Systems” that promise to perform every imaginable function, in smallest size and lowest cost that every global person could afford. In addition, wearable systems, internet of things and miniaturized medical devices such as medical implants, electronic eyes and hearing aids are also emerging as important products requiring “More Than Moore” that has been pursued for more than 15 years. These small and ultra-small systems, however, require revolutionary technologies referred to as System Scaling, in contrast to transistor scaling during the last 60 years. These systems are expected to drive unparalleled electronics technology paradigms in system miniaturization, functionality, and cost. The system scaling technologies are many that need to be explored, developed, integrated, interconnected, tested, and commercialized. This course presents a vision, strategy and reviews status of system scaling technologies.

Course Outline:1. Challenges and Status

2. 2D, 2.5D, and 3D Through-Via Substrates

3. Off-Chip Electrical and Optical Interconnections

4. Board Level Interconnections

5. Advanced Passives and Their Integration with Actives

6. Electrical Designs

7. Thermal Designs

8. Mechanical Designs

Who Should Attend:This is a new course on a strategic topic of great interest to industry R&D executives, senior managers, and technical leaders who are developing both short and long-term strategies for their companies in every electronic technology.

5. POLYMERS AND NANO-COMPOSITES FOR ELECTRONIC AND PHOTONIC PACKAGINGCourse Leaders: C.P. Wong – Georgia Institute of Technology; Daniel Lu – Henkel Corporation

Course Objectives:Polymers and nanocomposites are widely used in electronic and photonic packaging as adhesives, encapsulants, insulators, dielectrics, molding compounds, and conducting elements for interconnects. These materials also play a critical role in the recent advances of low-cost, high performance novel no flow underfills, reworkable underfills for ball grid array (BGA), chip scale packaging (CSP), system in a package (SIP), direct chip attach (DCA), flip-chip (FC), paper-thin IC and 3D packaging, conductive adhesives (Isotropic Conductive Adhesives and Anisotropic Conductive Adhesives), embedded passives (high K polymer composites), and nano particles and nanofunctional materials such as CNTs (some with graphenes). It is imperative that material suppliers, formulators, and their users have a thorough understanding of polymeric materials and the recent advances on nano materials and their importance in the advances of the electronic packaging and interconnect technologies.

Course Outline:1. Fundamentals of Polymers and Materials

Science and Engineering

2. Material Needs for Next Generation Electronic Packaging

3. Novel Nanocomposites for Flip-Chip Underfill Applications

4. Recent Advances on Nano Lead-Free Alloys for High Performance Components Interconnects

5. Low-Cost High Performance Lead-Free Interconnect Materials and Processes

6. Recent Advances on CNTs as Thermal Interface Materials (TIMs)

7. Lotus Effect Coating for Self-Cleaning Applications

8. Fundamentals of Electrically Conductive Adhesives (ECAs)

9. Recent Advances on Conductive Adhesives

10. Recent Advances on Nano Conductive Adhesives

Who Should Attend:Engineers, scientists, and managers involved in the design, process, and manufacturing of IC electronic components, and hybrid packaging, electronic material suppliers involved in materials manufacturing and research & development should attend.

6. INTEGRATED THERMAL PACKAGING AND RELIABILITY OF POWER ELECTRONICSCourse Leaders: Patrick McCluskey and Avram Bar-Cohen – University of Maryland

Course Objectives:Power electronics are becoming ubiquitous in engineered systems as they replace traditional ways to control the generation, distribution, and use of energy. They are used in products as diverse as home appliances, cell phone towers, aircraft, wind turbines, radar systems, and smart grids. This widespread incorporation has resulted in significant improvements in efficiency over previous technologies, but it also has made it essential that the reliability of power electronics be characterized and enhanced. Recently, increased power levels, made possible by new compound semiconductor materials, combined with increased packaging density have led to higher heat densities in power electronic systems, especially inside the switching module, making thermal management more critical to performance and reliability of power electronics. Following a review of heat transfer principles and thermal management techniques, along with prognostic health management approaches to assess and ensure reliability, this short course will present the latest developments in the packaging, assembly, and thermal management of power electronic modules and systems, along with modeling and testing techniques. This course will emphasize thermal packaging techniques capable of addressing performance limits and reliability concerns associated with increased power levels and power density in power electronic components.

Course Outline:1. Introduction to Packaging for Reliable Power

Electronic Systems

2. Passive Thermal Management Techniques (Thermal Interface and Phase Change Materials)

3. Active Thermal Management Techniques (Air, Single Phase Liquid, Two Phase, Thermoelectric)

4. Durability Assessment (Failure Modeling, Simulation, Testing, and Condition Monitoring)

5. Reliability and Thermal Packaging of Active Devices (Si, SiC, GaN)

6. Reliability and Thermal Packaging of Switching Modules

7. Reliability in Assembly Level Thermal Packaging (Boards, Passives, Solder)

Who Should Attend:This course is intended for new and established engineers and technical managers in the field of electronic packaging who would like to learn more about the thermo-mechanical issues involved in reliably packaging devices and circuits for applications involving high voltage, current, and power dissipation.

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Page 10: 65th ECTC Advance Program

7. FUNDAMENTAL CONCEPTS OF RELIABILITY AND MECHANICS IN ELECTRONIC PACKAGINGCourse Leaders: Shubhada Sahasrabudhe and Sandeep Sane – Intel Corporation

Course Objectives:The objective of this course is to provide an overview of an integrated methodology that combines the fundamentals of reliability and solid mechanics to perform knowledge-based decision making. The methodology is about comprehensively understanding mechanics of failures and correlating to empirical observations. This unified method drives proactive product risk assessment at use conditions and optimizes future product designs for reliability. The course will introduce key elements of reliability such as use conditions, accelerated life tests, methods of statistical data analysis, acceleration factor models for different failure mechanisms, and use of statistics to project reliability performance at use conditions. It will provide an overview of the basic concepts of solid mechanics such as stress-strain curves, characterization of material behavior, stress analysis methods including FEA, and fundamentals of fracture mechanics. Deriving on these concepts, the course will introduce a unified methodology for using mechanics-based reliability assessment. Comprehensive case studies highlighting different package risk areas will be introduced to showcase the application of methodology to real examples. The concepts of design for reliability and experiment planning will be discussed. Hands-on exercises will help students reinforce the skills learned.

Course Outline:1. Introduction to Quality and Reliability

2. Overview of Key Components of Reliability Statistics and Accelerated Testing

3. Hands-On Class Exercise – I

4. Introduction to Solid Mechanics

5. Key Components of Solid Mechanics: Stress/Strain Curves, Material Characterization, Finite Element Analysis

6. Overlapping Areas Between Reliability and Mechanics

7. Overview of the Unified Reliability Assessment Methodology Using Mechanics

8. Unified Reliability Assessment Methodology Applied to Packaging – Case Study 1

9. Unified Reliability Assessment Methodology Applied to Packaging – Case Study 2

10. Hands-On Class Exercise – II

11. Summary of Key Learning

Who Should Attend:Engineers working on packaging, reliability, and materials should attend this class.

8. FUNDAMENTALS OF ELECTRICAL DESIGN AND FABRICATION PROCESSES OF INTERPOSERS, INCLUDING THEIR RDLSCourse Leaders: Ivan Ndip and Michael Töpper – Fraunhofer IZM

Course Objectives:As a result of their myriad of advantages in system-integration, glass and silicon interposers will continue to play a crucial role in the development of future electronic systems for a wide range of applications. The fabrication processes and electrical performance of these interposers, including their re-distribution layers (RDLs), will contribute significantly to the cost and performance of the entire system. The objective of this course is to provide and illustrate the fundamentals of efficient electrical design, and fabrication processes of glass and silicon interposers, including their RDLs. The properties of dielectric materials and packaging structures used for fabricating glass and silicon interposers as well as their RDLs will first be presented. Secondly, their fabrication processes will be discussed. This will be followed by an illustration of the fundamentals of efficient electrical design of the interposers and their RDLs in a frequency range from 100 MHz to 100 GHz. A comparative analysis of transmission lines and vias in these interposers will also be provided. Finally, the impact of process variations on RF performance will be illustrated. Examples of glass and silicon interposers designed and fabricated at Fraunhofer IZM will also be discussed.

Course Outline:1. Materials Packaging Structures for Fabricating

Glass and Silicon Interposers Including RDLs

2. Step-by-Step Illustration of Fabrication Processes of RDLs, Glass, and Silicon Interposers

3. Illustration of a Holistic and Systematic Design Approach for Interposers and RDLs

4. Explanation of Fundamental Electrical Design Concepts (Including Impedance, RLCG Parasitics, S-Parameters, Signal/Power Integrity)

5. Electrical Design of Transmission Lines on RDLs, Silicon and Glass Interposers

6. Comparison of Transmission Lines on Silicon and Glass Interposers from 100 MHz to 100 GHz

7. Electrical Design of Through-Silicon Vias (TSVs) and Through-Glass Vias (TGVs) from 100 MHz to 100 GHz

8. Comparison of TSVs and TGVs from 100 MHz to 100 GHz

9. Impact of Process Variations on RF Performance of RDLs, Silicon and Glass Interposers

10. Examples of Glass and Silicon Interposers Designed and Fabricated at Fraunhofer IZM

Who Should Attend:Engineers, researchers, designers, technical managers, and graduate students involved in the process of electrical design, layout, processing, fabrication, and/or system-integration of interposers and electronic packages.

9. FLIP CHIP TECHNOLOGIESCourse Leaders: Eric Perfecto – IBM Corporation; Shengmin Wen – Synaptics Incorporated

Course Objectives:This course will cover all aspects of the flip chip technology used in today’s flip chip products, including the lead free solder bumping and highly customized Cu Pillar bumping technologies. Single chip, multichip, single unit based BGA package, as well as strip based chip scale packages, chip-on-chip, and 2.5D/3D flip chip packages will all be discussed and demonstrated. It will detail and compare the various under-bump metalization (UBM) and solder deposition methods. It will include process considerations when joining die bumped with various methods to various types of substrates (organic laminate, ceramic and Si substrates). This course will cover the accelerated reliability tests, the failure types, and the analytical tools used to identify defect root cause. A substantial portion of this course will be covering the Cu pillar flip chip technologies with highly customized bumping and assembly processes that are applied to flip chip packages inside today’s mobile devices. Failure modes and solutions associated with flip chip assembly implementation, such as barrier consumption, Kirkendall void formation, BEOL dielectric cracking, electromigration, etc. will be included respectively in the related subjects of the whole course. The students are encouraged to bring topics and technical issues from their daily job function for group discussions.

Course Outline:1. Introduction to Flip Chip

2. UBM Metal Selection

3. Flip Chip Solder Deposition Processes

4. Cu Fabrication Issues

5. Flip Chip-Plastic Ball Grid Array (FCPBGA) Assembly Process Flow

6. White Bump and Electromigration

7. Cu Pillar Flip Chip Summary

8. Cu Pillar Bumping

9. Cu Pillar Assembly

10. Non-Conductive Paste (NCP) and Thermal Compression Bonding

11. Substrate Technologies for Cu Pillar Flip Chip Assembly

10

AFTERNOON COURSES1:15 p.m. – 5:15 p.m.

Page 11: 65th ECTC Advance Program

11. MOISTURE AND MEDIA INFLUENCE ON MICROELECTRONIC PACKAGE RELIABILITYCourse Leaders: Tanja Braun and Hans Walter – Fraunhofer IZM

Course Objectives:Many electronic products used in different applications, such as automotive and medical, are exposed to extreme loading profiles such as high temperatures, random vibrations, or humid and even wet environments. Absorbed moisture has a plasticizing effect on the physical properties of polymers. Furthermore, moisture leads to corrosion of metallic parts of the devices and therefore molding compounds are used to protect sensible electronics. Polymer systems, for example, epoxy molding compounds, adhesives, underfills, etc., tend to absorb water molecules and exhibit a swelling behavior. Since most other materials involved do not swell when exposed to moisture, a stress between the materials is induced which is similar in origin (dimensional change in materials) and magnitude as the thermal mismatch induced stresses or chemical shrinkage. Consequently, moisture plays an important role in the reliability of microelectronic applications and thus it is important to know both absorption and desorption properties of polymers used in such devices. For the indication of failure mechanisms and to estimate the lifetime of electronic products, temperatures and moisture concentration at more elevated levels than usual are used to accelerate testing. The workshop provides a comprehensive overview on moisture and other media induced changes in properties of micro relevant materials used for microelectronic packaging in automotive or medical applications. Related reliability issues will be discussed and application examples shown.

Course Outline:1. Introduction to Moisture Sorption, Diffusion,

and Swelling in Polymers

2. Overview of State of the Art Measurement Equipment

3. Important Aspects of Encapsulation Technologies for Non-Hermetical Packaging

4. Moisture and Media Induced Changes in Material Properties

5. Simulation of Small Molecule Transport and Swelling by Finite Element Method (FEM) and Molecular Dynamics

6. Moisture and Media Induced Failure Mechanisms

7. Package Reliability Enhancement by Introduction of Barrier Layers

Who Should Attend:This course is aimed at engineers in the field of microelectronic package design and reliability engineering, who will learn about incorporation of moisture induced phenomena into design rules for best device performance. It also aims at engineers at management level who are provided with knowledge that helps make decisions on materials and design options.

12. THERMAL AND MECHANICAL SIMULATION TECHNIQUES FOR IC PACKAGE YIELD, RELIABILITY, AND PERFORMANCECourse Leader: Kamal Karimanal – Cielutions, Inc.

Course Objectives:The Interconnect industry is becoming increasingly aware of the fact that thermal and mechanical factors related to packaging and assembly are crucial hurdles to the enablement of next generation IC and photonic products. These challenges are pervasively felt at all stages of the product development cycle starting from layout, IC design, power management, assembly processing strategy, package design, and testing. Due to the need to narrow down from a myriad of costly choices, even prior to test chip or prototype development, engineering simulation is an important tool at the disposal of the engineer.

Course Outline:1. Direct Thermal Modeling Techniques:

Steady-State, Transient

2. Compact Thermal Modeling: Applicability of Traditional CTM, Novel CTM Techniques, CielSpot Dynamic CTM Methodology

3. Overview of Mechanical Challenges to Packaging and Assembly: Warpage, Assembly Yield, CPI Effects on Yield & Reliability

4. Assembly Process Modeling Techniques: CTE, Reference Temperature, Element Birth & Death

5. The Concept of Global/Local Modeling: Lumped Modeling Techniques

6. Mechanical Risk Indicators: Warpage, Stress, Stress Intensity Factors, and Energy Release Rate

7. Chip Level Mobility/Stress Distribution: Contributions from Package, TSV, and Devices

Who Should Attend:This is an introductory course on thermal and mechanical simulation techniques pertaining to assembly and packaging designed for engineering professionals involved in the enablement of monolithic IC products as well as TSV-based 3D stacked SOCs. All IC design and packaging engineers interested in utilizing thermal and mechanical simulation should attend this course.

11

12. Substrate Technologies (2D & 2.5D) for Cu Pillar Flip Chip Assembly

13. Integration Options in Cu Pillar Assembly and Failure Modes

14. Cu Pillar Reliability Assessment

Who Should Attend:The targeted audience includes scientists, engineers, and managers currently using flip chip (with solder or Cu Pillar) or who are considering moving from wire bonding, as well as reliability, product, or applications engineers who need a deeper understanding of flip chip advantages, limitations, and failure mechanisms.

10. WAFER LEVEL CHIP SCALE PACKAGINGCourse Leader: Luu Nguyen – Texas Instruments

Course Objectives:This course will provide an overview of the Wafer Level-Chip Scale Packaging (WL-CSP) technology. The market drivers, end applications, benefits, and challenges facing industry-wide adoption will be discussed. Typical WL-CSP configurations (bump on pad, bump on polymer, fan-out) will be reviewed in terms of their construction, manufacturing processes, materials and equipment, and electrical and thermal performance, together with package and board level reliability. Since the technology marks the convergence of fab, assembly, and test, discussion will address questions on the industrial supply chain such as:

Course Outline:1. Does it fit best with front-end or back-end

processing?

2. Will it be applicable and cost-effective for memory and other complex devices such as ASICs and microprocessors?

3. Are the current standards for design rules, outline, and reliability applicable? Extensions to higher pin count packages and other areas such as RF and MEMS will be reviewed.

4. Future trends will also be covered:

• enhanced lead-free solder balls• large die size• wafer level underfill• thin and ultra-thin WL-CSP• RDL (redistribution layer)• stacked WL-CSP• MCM in “reconstituted wafers”• embedded components, etc.

Who Should Attend:The course will be useful to the following groups of engineers: Newcomers to the field who would like to obtain a general overview of WL-CSP and R&D practitioners who would like to learn new methods for solving CSP problems and are considering WL-CSP as a potential alternative for their packaging solutions.

IMPORTANT NOTICEIt is extremely important to register

in advance to prevent delays atdoor registration. Course sizes

are limited.

Page 12: 65th ECTC Advance Program

12

13. POLYMERS FOR ELECTRONIC PACKAGINGCourse Leader: Jeffrey Gotro – InnoCentrix, LLC

Course Objectives:The course will provide a broad overview of polymers used in semiconductor packaging and the important structure-property-process-performance relationships. We will cover in more depth the chemistries, material properties, and process considerations for adhesives, underfills, coatings, and mold compounds. Additionally, we will provide an introduction to common thermal analysis methods (DSC, DMA, TMA, and TGA) used to characterize thermoset polymers used in semiconductor packaging. Finally, the course will provide an introduction to the rheological performance of polymer-based materials used in packaging semiconductors. In most cases, adhesives, underfills, mold compounds, and coatings are applied as a viscous liquid and then cured. The flow properties of these materials are critical to performance in high volume manufacturing. The course will provide an introduction to rheology measurements and examples of rheology issues in semiconductor packaging.

Course Outline:1. Thermoset Polymers Versus Thermoplastics

2. Temperature Dependence of Physical Properties

3. Thermoset Polymers; Curing, Curing Mechanisms, Network Formation

4. Overview of Key Chemistries Used (Epoxies, Acrylates, Polyimides, Bismaleimides)

5. Chemistry of Die Attach Adhesives (Paste and Film) and Capillary Underfills

6. Chemistries Used in Mold Compounds

7. Packaging Substrate Materials

8. Encapsulants (Mold Compounds) and Coatings

9. Overview of Polymers Used in 2.5D and 3D Packaging

10. Introduction to Rheological Characterization Methods; Types of Rheometers and Basic Techniques

11. Introduction to the Rheological Properties of Adhesives

12. Key Rheology Properties; Shear Thinning, Viscosity, Rheology Changes during Curing

Who Should Attend:Packaging engineers involved in the development, production, and reliability testing of semiconductor packages would benefit from the course. R&D professionals interested in gaining a basic understanding of the structure/property/process/performance relationships in polymers and polymer-based materials used in electronic packaging will also find this course valuable.

14. NOVEL INTERCONNECT AND SYSTEM INTEGRATION TECHNOLOGIESCourse Leader: Muhannad Bakir – Georgia Institute of Technology

Course Objectives:Interconnects have emerged as a critical bottleneck to the realization of lower power and higher performance electronics. Coupled with this, the need for more tightly integrated systems presents unique cooling and power delivery challenges for next generation electronics. This course will present an overview of emerging technologies to address these areas and present key modeling results to help guide technology development. The course topics addressing advanced technologies include: 3D technology (monolithic 3D as well as TSV-based 3D), silicon interposer technologies (both electrical and photonic interconnect based), advanced cooling technologies including those based on microfluidics, and short discussion on testing strategies for such systems. The modeling effort to be presented in this course will not only help us understand the design considerations of the technologies discussed but will also help benchmark the performance of the various technologies so that optimal systems can be developed.

Course Outline:1. 3D-TSV Based System Integration

2. Monolithic-3D Based System Integration

3. Advances in Silicon Interposer Technologies (Digital and RF)

4. Photonic Silicon Interposer Technologies

5. Advanced Cooling Technologies, Including Microfluidic Cooling for Interposer and 3D Systems

6. Thermal and Power Delivery (Power Supply Noise) Modeling for 3D Systems

7. Short Discussion on Wafer-Level Testing Challenges and Possible Solutions

Who Should Attend:This short course will be of value to those working in the areas of interconnects, packaging, and 3D technology, and heterogeneous integration.

15. PACKAGE FAILURE MECHANISMS, RELIABILITY, AND SOLUTIONSCourse Leader: Darvin Edwards – Edwards Enterprises

Course Objectives:Major failure mechanisms for FC-BGA, plastic leaded, no lead, and TSV package types will be reviewed. These will include ILD damage under bumps and wire bonds, Cu vs. Au wire bond sensitivities, problems associated with delamination in the package, solder joint reliability, and system level problems such as drop and bend reliability. For each failure mechanism, the

failure analysis techniques needed to verify the mechanism will be summarized. Key parameters that influence the failures will be highlighted. Process parameters, design techniques, and materials selections that improve the reliability behavior of the packages will be provided with an emphasis on solving each of the issues. A brief discussion of reliability models as related to each failure mechanism will also be covered to give an understanding of the probability for field failure occurrence. The use of design guidelines to ensure that the failure modes are designed out will be encouraged. A methodology of test structures combined with qualification by similarity will be highlighted as a process for early detection of chip/package interaction failure mechanisms. The use of test structures to calibrate finite element models will be described.

Course Outline:1. Introduction and Description of Packages to

be Covered

2. Failure Analysis Techniques

3. FC-BGA Package Failure Mechanisms

4. Molded Package Failure Mechanisms

5. New Failure Mechanisms Associated with TSV and Cu Wire Bond Technologies

6. Materials Characteristics and How They Impact Failure Modes

7. Reliability Models for Failure Mechanisms

8. Common Test Structures for Mechanism Identification and Elimination

9. Qualification by Similarity (QBS) Methods

10. Using Test Structures for Model Calibration

Who Should Attend:This class is intended for those responsible for package reliability, package development, package design, and package processing where knowledge of package failure mechanisms will prove useful. Both beginning engineers and those skilled in the art will benefit from the holistic description of the failure mechanisms, the FA techniques, and the solutions.

16. 3D IC INTEGRATION AND 3D IC PACKAGINGCourse Leader: John Lau – ASM Pacific Technology Ltd.

Course Objectives:3D IC packaging and 2.5D/3D IC integration are different. In general, the TSV (through-silicon via) separates 3D IC packaging from 2.5D/3D IC integration because the latter use TSVs, but 3D IC packaging does not. TSV is the heart of 2.5D/3D IC integration. It provides the opportunity for the shortest chip-to-chip interconnect and the smallest pad size and pitch of interconnects. The potential high volume manufacturing of 2.5D/3D IC integration is: (1) memory-chip stacking, (2) Wide I/O memory (or logic-on-logic), (3) Wide I/O DRAM, Wide I/O 2, HMC, and HBM, and (4) Wide

Page 13: 65th ECTC Advance Program

I/O interface (or 2.5D IC integration). In this presentation, the supply chains and the critical steps such as FEOL, MOL, BEOL, TSV, MEOL (middle-end-of-line), assembly, and test and their ownerships for high-volume manufacturing for those four groups of 3D IC integration will be discussed. The 3D IC packaging, which has been keeping 3D IC integration away from volume production, will be briefly mentioned first. Key enabling technologies such as TSV forming and filling, front and backside metallization, RDL, temporary bonding and de-bonding, microbumping, assembly and reliability, and thermal management will be presented and discussed. All the materials are based on the papers and books published by the lecturer and others.

Course Outline:1. 3D IC Packaging

2. TSV Technology

3. Micro Bumping, Assembly, and Reliability

4. 3D IC Integration

5. 2.5D IC Integration

6. Thin-Wafer Handling

7. RDL Fabrication; Polymer and Cu Damascene

8. Supply Chains and Ownership for 2.5D/3D IC Integration

9. Advances in Package Substrates

10. Thermal Management of 2.5D/3D IC Integration

11. 3D CIS and IC Integration

12. 3D MEMS and IC Integration

13. 3D LED and IC Integration

14. Embedded Fan-Out Wafer-Level Packaging

15. Outlooks of 3D IC Packaging

16. Outlooks of 3D IC Integration

Who Should Attend:If you (students, engineers, and managers) are involved with any aspect of the electronics, LED, MEMS, CIS, and optoelectronic industry, you should attend this course. It is equally suited for R&D professionals and scientists.

IMPORTANT NOTICE Morning PD Courses 1 through

8 or afternoon PD Courses 9 through 16 run concurrently. Make

sure you indicate specific course numbers you plan to attend when

you register online. See page 30 for registration information.

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AREA ATTRACTIONSNestled at the edge of spectacular San Diego Bay, the Sheraton San Diego Hotel & Marina enjoys panoramic views of the bay and the city skyline, yet is just 10 minutes from renowned attractions including the Gaslamp Quarter, Old Town, and Balboa Park.

The 1,053 guest rooms and suites are located in two towers and feature bold naval hues, the Sheraton Sweet Sleeper Bed, Shine by Sheraton bath products, and balconies with bay or city views. Enjoy the five minute scenic walk around the marina that connects both hotel towers.

In addition to all that the hotel boasts and offers, other local San Diego area attractions include its longstanding naval base on Coronado Island as well as Old Globe Theater, La Jolla, Mission Bay, and Point Loma. San Diego also boasts more championship golf courses, over 85, than any other US city. And one last thing, don’t forget to take time out to visit the world renowned San Diego Zoo!

Continuing Education UnitsThe IEEE Components, Packaging and Manufacturing Technology Society (CPMT) is authorized to offer Continuing Education Units (CEUs) by the International Association for Continuing Education and Training (IACET) for all Professional Development Courses that will be presented at the 65th ECTC.

CEUs are recognized by employers for continuing professional development as a formal measure of participation and attendance in “non-credit” self-study courses, tutorials, symposia, and workshops. Complete details, including voluntary enrollment forms, will be available at the conference. All costs associated with ECTC Professional Development Course CEUs will be underwritten by the conference, i.e., there are no additional costs for Professional Development Course attendees to obtain CEU credit.

Page 14: 65th ECTC Advance Program

Committee: Advanced PackagingRoom: Harbor Island 1

Session Co-Chairs:Young-Gon Kim - IDTTel. [email protected]

Markus Leitgeb - AT&STel. [email protected]

1. 8:00 a.m. - High Reliability Packaging Technologies and Process for Ultra Low k Flip Chip DeviceJoonyoung Park, YunHee Kim, SeokHo Na, Lou Nicholls, JinYoung Kim, and ChoonHeung Lee – Amkor Technology, Inc.

2. 8:25 a.m. - Thermal Compression Bonding for Fine Pitch Solder InterconnectsJie Fu, Manuel Aldrete, Milind Shah, Marcus Hsu, and Vladimir Noveski – Qualcomm Technologies, Inc.

3. 8:50 a.m. - Chip Package Interaction Analysis for 20 nm Technology with Thermo-Compression Bonding with Non-Conductive PasteJae Kyu Cho, Shan Gao, Seungman Choi, Ryan Smith, Eng Chye Chua, and Sukeshwar Kannan – GLOBALFOUNDRIES; Bob Kuo, Miguel Jimarez, JinSuk Jeong, YunHee Kim, and SeokHo Na – Amkor Technology, Inc.

4. 10:00 a.m. - Multi Die Chip on Wafer Thermo Compression Bonding Using Non-Conductive FilmDavid Hiner, Min Jae Lee, Mike Kelly, Dae Byoung Kang, Seok Geun Ahn, Keun Soo Kim, Hwan Kyu Kim, and Ron Huemoeller – Amkor Technology, Inc.; Riko Radojcic, Sam Gu, and Dong Wook Kim – Qualcomm Technologies, Inc.

5. 10:25 a.m. - High Productivity Thermo-Compression Flip Chip BondingHorst Clauberg, Tom Colosimo, Daniel Buergi, Alireza Rezvani, and Bob Chylak – Kulicke and Soffa, Inc.

6. 10:50 a.m. - 14nm Chip Package Interaction Development with Cu Pillar Bump Flip Chip PackageKuo Ming Chen, Kai Kuang Ho, Cheng Hsiao Wang, Chung Yen Wu, and Po Chen Kuo – United Microelectronics Corporation

7. 11:15 a.m. - Flip Chip Assembly with Sub-Micron 3D Realignment via Solder Surface Tension Jae-Woong Nah, Yves Martin, Swetha Kamlapurkar, Sebastian Engelmann, Robert L. Bruce, and Tymon Barwicz – IBM Corporation

Committee: InterconnectionsRoom: Harbor Island 2

Session Co-Chairs:Katsuyuki Sakuma - IBM CorporationTel. [email protected]

Kathy Cook - ZiptronixTel. [email protected]

1. 8:00 a.m. - Metallization of High Density TSVs Using Super Inkjet TechnologyBehnam Khorramdel Vahed, Mika-Matti Laurila, and Matti Mäntysalo – Tampere University of Technology

2. 8:25 a.m. - Acoustic GHz-Microscopy and Its Potential Applications in 3D-Integration TechnologiesSebastian Brand, Sebastian Tismer, Jens Beyersdorfer, Frank Altmann, and Matthias Petzold – Fraunhofer Institute for Mechanics of Materials; Wolfram Steller and Jürgen Wolf – Fraunhofer IZM

3. 8:50 a.m. - Experimentally, How Does Cu TSV Diameter Influence Its Stress State?Chukwudi Okoro, Lyle Levine, and Yaw Obeng – National Institute of Standards and Technology (NIST); Ruqing Xu – Argonne National Laboratory

4. 10:00 a.m. - Room Temperature ALD Oxide Liner for TSV ApplicationsDingyou Zhang, Sarasvathi Thangaraju, Daniel Smith, Laehee Lee, David Lundeen, and Luke England – GLOBALFOUNDRIES

5. 10:25 a.m. - Advanced Metallization Scheme for 3x50um Via Middle TSV and BeyondStefaan Van Huylenbroeck, Yunlong Li, Nancy Heylen, and Eric Beyne – IMEC; Mohand Brouri, Sanjay Gopinath, Praveen Nalla, Matthew Thorum, Prashant Meshram, and Jengyi Yu – Lam Research Corporation

6. 10:50 a.m. - Improved C-V, I-V Characteristics for Co-Polymerized Organic Liner in the Through-Silicon Via for High Frequency Applications by Post Heat TreatmentMurugesan Mariappan, Takafumi Fukushma, JiCheol Bea, Hiroyuki Hashimoto, Yutaka Sato, KangWook Lee, and Mitsumasa Koyanagi – Tohoku University

7. 11:15 a.m. - Electroless Barrier/Seed Formulation in High Aspect Ratio ViaTakashi Tanaka, Mitsuaki Iwashita, and Takayuki Toshima – Tokyo Electron Kyusyu Ltd.; Keiichi Fujita and James Chen – Tokyo Electron Nexx, Inc.

Committee: Applied ReliabilityRoom: Harbor Island 3

Session Co-Chairs:S. B. Park - Binghamton UniversityTel. [email protected]

Toni Mattila - Aalto UniversityTel. [email protected]

1. 8:00 a.m. - Design and Assembly Process Effects on Lead Free Solder Joint Board Level Reliability of Bare Die and Lidded Flip Chip Ball Grid Array PackagesDongming He, Brian Roggeman, Eric Zhou, Jiantao Zheng, and Pat Holmes – Qualcomm Technologies, Inc.

2. 8:25 a.m. - Effects of Solder Joint Dimensions and Assembly Process on Acceleration Factors and Life in Thermal Cycling of SnAgCu Solder JointsPeter Borgesen, Sam Shirazi, Saif Khasawneh, and Luke Wentlent – Binghamton University; Liang Yin – GE Global Research

3. 8:50 a.m. - Key Parameters for Fast Metallization Dissolution during Electromigration of Solder Joint Deepak Goyal, Pilin Liu, and Alan Overson – Intel Corporation

4. 10:00 a.m. - Thermal Cycling Reliability of Aged PBGA Assemblies - Comparison of Weibull Failure Data and Finite Element Model PredictionsJeffrey Suhling, Munshi Basit, Mohammad Motalab, Zhou Hai, John Evans, Michael Bozack, and Pradeep Lall – Auburn University

5. 10:25 a.m. - Failure Mechanism and Microstructural Evolution of Pb-Free Solder Alloys in Thermal Cycling Tests: Effect of Solder Composition and Sn Grain MorphologyBabak Arfaei and Jim Wilcox – Universal Instruments Co.; Francis Mutuku and Eric Cotts – Binghamton University; Richard Coyle – Alcatel-Lucent

6. 10:50 a.m. - Thermal Cycling Reliability of Lead Free Solder Joints on Multi-Terminal Passive ComponentsVikas Gupta, Gregory Ostrowicki, Jaimal Williamson, and Siva Gurrum – Texas Instruments, Inc.

7. 11:15 a.m. - Mechanism of Void Formation in Cu Post Solder Joint under ElectromigrationM. Y. Kim, L. S. Chen, and C.-U. Kim – University of Texas, Arlington; S.-H. Chae – Texas Instruments, Inc.

Program Sessions: Wednesday, May 27, 8:00-11:40 a.m.

Refreshment Break: 9:15-10:00 a.m.

14

Session 1: Flip Chip Packaging Session 2: 3D Technology: TSV Fabrication and Reliability

Session 3: Solder Joint Reliability

Page 15: 65th ECTC Advance Program

Committee: Materials & ProcessingRoom: Nautilus 1 & 2

Session Co-Chairs:Lejun Wang - Qualcomm Technologies, Inc.Tel. [email protected]

Tieyu Zheng - Microsoft CorporationTel. [email protected]

1. 8:00 a.m. - Plasma-Etched Nanofiber Anisotropic Conductive Films (ACFs) for Ultra Fine Pitch InterconnectionSang Hoon Lee, Tae-Wan Kim, and Kyung-Wook Paik – Korea Advanced Institute of Science and Technology

2. 8:25 a.m. - Effect of Binder Chemistry on the Electrical Conductivity of Air-Cured Epoxy-Based Electrically Conductive Adhesives Containing Copper FillerMasahiro Inoue, Yoshiaki Sakaniwa, Takeshi Notsuke, and Yasunori Tada – Gunma University

3. 8:50 a.m. - Performance Evaluation of Thermal Interface Material (TIM1) in FCBGA+HS Package Using Automatic Test Equipment (ATE) Tester and Package Reliability TestsSri Priyanka Tunuguntla, Chunwei Yu, Daijiao Wang, and Sam Karikalan – Broadcom Corporation

4. 10:00 a.m. - Role of Encapsulation Formulation on Charge Transport Phenomena and HV Device InstabilityIlaria Imperiale, Susanna Reggiani, Elena Gnani, Antonio Gnudi, and Giorgio Baccarani – University of Bologna; Luu Nguyen, Alex Hernandez-Luna, James Huckabee, Dhanoop Varghese, and Marie Denison – Texas Instruments, Inc.

5. 10:25 a.m. - Stencil Printing of Underfill for Flip-Chips on Organic-Panel and Si-Wafer Assemblies John Lau, Qinglong Zhang, Ming Li, Kai Ming Yeung, Yiu Ming Cheung, Nelson Fan, and Yam Mo Wong – ASM Pacific Technology, Ltd.

6. 10:50 a.m. - Technology of Packaging by Liquid Mold-Underfill (MUF) Material for Advanced Mobile DevicesYuki Ishikawa, Joji Yukimaru, Tomoya Takao, Kazuhiro Ikeda, Kazuaki Yamane, Akira Nakao, and Naokatsu Hisanaga – Sanyu Rec Co., Ltd.

7. 11:15 a.m. - Rheology Design Considerations for One Step Chip Attach Materials (OSCA) Used for Conventional Mass Reflow ProcessingDaniel J. Duffy, Mahesh Desai, Hemal Bhavsar, Lin Xin, Jean Liu, and Bruno Tolla – Kester, Inc.

Committee: Assembly & Manufacturing Technology • Room: Nautilus 3 & 4

Session Co-Chairs:Wei Koh - Pacrim TechnologyTel. [email protected]

Shaw Fong Wong - Intel CorporationTel. [email protected]

1. 8:00 a.m. - The Silicon on Diamond Structure by Low-Temperature Bonding TechniqueSethavut Duangchan, Yusuke Uchikawa, Yusuke Koishikawa, Akiyoshi Baba, Kentaro Nakagawa, and Satoshi Matsumoto – Kyushu Institute of Technology; Masataka Hasegawa and Shinichi Nishizawa – The National Institute of Advanced Industrial Science & Technology (AIST)

2. 8:25 a.m. - Balanced Embedded Trace Substrate Design for Warpage ControlChia Ching Chen, Ming-Ze Lin, Guo-Cheng Liao, Yi-Chuan Ding, and Wen-Chi Cheng – Advanced Semiconductor Engineering, Inc.

3. 8:50 a.m. - Novel Mass Reflow Method for Organic SubstratesVijay Khanna and Sri M. Sri-Jayantha – IBM Corporation

4. 10:00 a.m. - Plasma Induced Deionization of High Ag Alloy in Wire Bond Integrated CircuitChen Nan Lin, Chen Hui Wu, and Shin Low – Xilinx, Inc.; Ming-Hsien Lu, Shin Rung Chen, Ying Yu Lu, Yu Yun Liao, Chin Wen Liao, and Chien Ming Chang – Siliconware Precision Industries Co., Ltd.

5. 10:25 a.m. - Assessment of Dicing Induced Damages and Strain Fields on the Mechanical and Electrical Behavior of ChipsMichael Fuegl and Gunther Mackh – Infineon Technologies AG; Elke Meissner and Lothar Frey – Fraunhofer IISB

6. 10:50 a.m. - High Reliability, Improved Performance and Low Cost “Interconnect Technology” for LED Light EnginesPeiching Ling and Dezhong Liu – Achrolux, Inc.; Ken Holcomb and Catherine Shearer – Ormet Circuits, Inc.; Kazuhiko Kobayashi – Apic Yamada Corporation; Vivek Dutta – Advenient, LLC

7. 11:15 a.m. - Solder Printability of Stencil Coated with Hydrophobic Organic CoatingKyoung-Ho Kim, Min-Soo Kang, and Sehoon Yoo – Korea Institute of Industrial Technology (KITECH); Ji-Young Jang, Chang-Joon Lee, Yong-Won Lee, and Soon-Min Hong – Samsung Electronics Company, Ltd.

Committee: High-Speed, Wireless & Components Joint

with Modeling & Simulation • Room: Nautilus 5

Session Co-Chairs:Amit P. Agrawal - Cisco Systems, Inc.Tel. [email protected]

Xiaoxiong (Kevin) Gu - IBM CorporationTel. +1-914-945-2292 [email protected]

1. 8:00 a.m. - Ultra-Thin and Ultra-Small 3D Double-Side Glass Power Modules with Advanced Inductors and CapacitorsSaumya Gandhi, P. Markondeya Raj, Bruce C. Chou, Parthasarathi Chakraborti, Min Suk Kim, Srikrishna Sitaraman, Himani Sharma, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology

2. 8:25 a.m. - A Novel TSV Inductor Structure for RF ApplicationsBruce Kim, Saikat Mondal, and Jonathan Gamboa – City University of New York; Sang-Bock Cho – University of Ulsan

3. 8:50 a.m. - Affordable 3D Printed Microwave ComponentMohd Ifwat Mohd Ghazali, Jennifer Byford, Eleazar Gutierrez, Joshua Myers, Amanpreet Kaur, and Prem Chahal – Michigan State University

4. 10:00 a.m. - Through Silicon Capacitors (TSC) for the Noise Reduction in Power Distribution NetworkKhadim Dieng, Cédric Bermond, Thierry Lacrevaz, Grégory Houzet, Bernard Flechet, and Philippe Artillan – IMEP LAHC Chambéry; Olivier Guiller, Sylvain Joblot, and Alexis Farcy – STMicroelectronics; Yann Lamy – CEA-LETI

5. 10:25 a.m. - Precise RLGC Modeling and Analysis of Through Glass Via (TGV) for 2.5D/3D ICJihye Kim, Jonghyun Cho, Youngwoo Kim, Insu Hwang, and Joungho Kim – KAIST; Venky Sundaram and Rao Tummala – Georgia Institute of Technology

6. 10:50 a.m. - Noise Coupling between TSVs and Active Devices: Planar nMOSFETs vs. nFinFETsXiao Sun, A. Rouhi Najaf Abadi, W. Guo, C. Roda Neve, G. Van der Plas, and E. Beyne – IMEC; K. Ben Ali, J. P. Raskin, and M. Rack – ICTE a.m., Université Catholique de Louvain; M. Choi and V. Moroz – Synopsys, Inc.

7. 11:15 a.m. - Silicon Interposer / TSV SignalingAndy Martwick and John Drew – Intel Corporation

Program Sessions: Wednesday, May 27, 8:00-11:40 a.m.

Refreshment Break: 9:15-10:00 a.m.

Session 4: Adhesives, Underfills, and Thermal Interface Materials

Session 5: Novel Manufacturing Solutions

Session 6: 3D Technology: High-Speed Components and Modeling

15

Page 16: 65th ECTC Advance Program

Committee: Advanced PackagingRoom: Harbor Island 1

Session Co-Chairs:Omar Bchir - Qualcomm Technologies, Inc.Tel. [email protected]

Dean Malta - RTI InternationalTel. [email protected]

1. 1:30 p.m. - Reliability Evaluation of an Extreme TSV Interposer and Interconnects for the 20nm Technology CoWoSTM IC-Package Bahareh Banijamali, Tom Lee, Henley Liu, Suresh Ramalingam, Ivor Barber, Jonathan Chang, and Myongseob Kim – Xilinx, Inc.

2. 1:55 PM - Fabrication and Characterization of Mixed-Signal Polymer-Enhanced Silicon Interposer Featuring Photodefined Coax TSVs and High-Q Inductors.Paragkumar Thadesar and Muhannad Bakir – Georgia Institute of Technology

3. 2:20 p.m. - Stress and Bowing Engineering in Passive Silicon InterposerMikael Detalle, Bart Vandevelde, Philip Nolmans, Andy Miller, Antonio La Manna, Gerald Beyer, and Eric Beyne – IMEC

4. 3:30 p.m. - A High-Speed, Long-Reach Signal Design Challenge for 2.5-D LSI Based on a Low-Cost Silicon Interposer and a Large-Scale SSO AnalysisRyuichi Oikawa, Tsuyoshi Kida, Kenji Sakata, Shuuichi Kariyazaki, Yuji Kayashima, and Yoshihiro Ono – Renesas Electronics Corporation; Toshihio Ochiai, Ryo Mori, and Takao Nomura – Renesas System Design Company Ltd.

5. 3:55 p.m. - Modeling, Design and Fabrication of Ultra-Thin and Low CTE Organic Interposers at 40µm I/O PitchZihan Wu, Chandrasekharan Nair, Yuya Suzuki, Fuhan Liu, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Daniel Foxman and Hiroyuki Mishima – Mitsubishi Gas Chemical Company

6. 1:55 p.m. - Integrated Low Loss RF Passive Components Based on Photosensitive Glass Interposer TechnologyArian Rahimi and Yong-Kyu Yoon – University of Florida

7. 4:45 p.m. - Embedded Glass Interposer for Heterogeneous Multi-Die IntegrationDyi-Chung Hu, Yin-Po Hung, Yu-Hua Chen, and Ra-Min Tain – Unimicron Technology Corp.; Wei-Chun Lo – Industrial Technology Research Institute

Committee: InterconnectionsRoom: Harbor Island 2

Session Co-Chairs:Tom Gregorich - Micron Technology, Inc.Tel. [email protected]

Wei-Chung Lo - ITRITel. [email protected]

1. 1:30 p.m. - An Enhanced Thermo-Compression Bonding Process to Address Warpage in 3D Integration of Large Die on Organic Substrates Katsuyuki Sakuma, Krishna Tunga, Buck Webb, Koushik Ramachandran, Marcus Interrante, Hsichang Liu, Matthew Angyal, Daniel Berger, John Knickerbocker, and Subramanian Iyer – IBM Corporation

2. 1:55 p.m. - Hybrid Bonding of Cu/Sn Microbump and Adhesive with Silica Filler for 3D Interconnection of Single-Micron PitchMasaki Ohyama, Masatsugu Nimura, Jun Mizuno, and Shuichi Shoji – Waseda University; Mamoru Tamura and Tomoyuki Enomoto – Nissan Chemical Industries; Akitsu Shigetou – National Institute for Materials Science

3. 2:20 p.m. - Wafer Level Packages (WLPs) Using B-Stage Non-Conductive Films (NCFs) for Highly Reliable 3D-TSV Micro-Bump InterconnectionHyeong Gi Lee, Yong-Won Choi, Ji-won Shin, and Kyung-Wook Paik – KAIST

4. 3:30 p.m. - Development of Highly-Reliable Microbump Bonding Technology Using Self-Assembly of NCF-Covered KGDs and Multi-Layer 3D Stacking ChallengesYuka Ito – Tohoku University and Sumitomo Bakelite Co., Ltd.; Takafumi Fukushima, Mariappan Murugesan, Hisashi Kino, Kang-Wook Lee, Tetsu Tanaka, and Mitsumasa Koyanagi – Tohoku University; Koji Choki – Sumitomo Bakelite Co., Ltd.

5. 3:55 p.m. - Challenges of High-Robustness Self-Assembly with Cu/SnAg Microbump Bonding for Die-to-Wafer 3D IntegrationTaku Suzuki, Kazushi Asami, and Yasuhiro Kitamura – Denso Corporation; Takafumi Fukushima, Chisato Nagai, Jichoel Bea, Yutaka Sato, Mariappan Murugesan, Kangwook Lee, and Mitsumasa Koyanagi – Tohoku University

6. 4:20 p.m. - High Precision Alignment Process for Future 3D Wafer BondingIsao Sugaya, Hajime Mitsuishi, Hidehiro Maeda, and Masashi Okada – Nikon; Kazuya Okamoto – Nikon; Osaka University

7. 4:45 p.m. - Effects of Packaging on Mechanical Stress in 3D-ICsVladimir Cherman, Melina Lofrano, V. Simons, Mario Gonzalez, Geert Van der Plas, Joeri De Vos, Teng Wang, Robert Daily, A. Salahouelhadj, Gerald Beyer, and Antonio La Manna – IMEC

Committee: Materials & ProcessingRoom: Harbor Island 3

Session Co-Chairs:Frank Wei - Disco JapanTel. [email protected]

Dong Wook Kim - Qualcomm Technologies, Inc.Tel. [email protected]

1. 1:30 p.m. - Advanced Seed Layer of Cu Wiring for Printed Circuit Board with Sputtering MethodTetsushi Fujinaga – ULVAC, Inc.

2. 1:55 p.m. - Development of Photosensitive Solder Resist with High Reliability for Semiconductor PackageKazuya Okada and Toko Shiina – Taiyo Ink Mfg. Co. Ltd.

3. 2:20 p.m. - Development of a Consistent Multiaxial Viscoelastic Model for Package Warpage SimulationTz-Cheng Chiu, Dong-Yi Huang, and Bo-Sheng Lee – National Cheng Kung University; Dao-Long Chen, Ping-Feng Yang, and Chin-Li Kao – Advanced Semiconductor Engineering, Inc.

4. 3:30 p.m. - Resolution of Extreme Warpage In Ultra-Thin Molded Array Packages Under High Temperature Storage LifeNishant Lakhera, Sandeep Shantaram, and Akhilesh Singh – Freescale Semiconductor

5. 3:55 p.m. - A Sub-4 µm Via Technology of Thinfilm Polymers using Scanning Laser AblationMichael Toepper, Karin Hauck, Mario Schima, and Danny Jaeger – Fraunhofer IZM

6. 4:20 p.m. - Two-Dimensional (2D) In-Plane Strain Mapping Using A Laser Scanning Technique on the Cross-Section of a Microelectronics PackageHanshuang Liang, Zeming Song, Teng Ma, Hoa Nguyen, George Chen, Hanqing Jiang, and Hongbin Yu – Arizona State University

7. 4:45 p.m. - “Zero-Undercut” Semi-Additive Copper Patterning – A Breakthrough for Ultrafine-Line RDL Lithographic Structures and Precision RF Thinfilm PassivesP. Markondeya Raj, Chandrasekharan Nair, Hao Lu, Fuhan Liu, Venky Sundaram, Dennis W. Hess, and Rao Tummala – Georgia Institute of Technology

Program Sessions: Wednesday, May 27, 1:30-5:10 p.m.

Refreshment Break: 2:45-3:30 p.m.

16

Session 7: Interposer Technology Session 8: 3D Technology: TSV Bonding Process Development & Characterization

Session 9: Advancements in Substrate Technologies

Page 17: 65th ECTC Advance Program

Committee: Applied ReliabilityRoom: Nautilus 1 & 2

Session Co-Chairs:Tim Chaudhry - Broadcom CorporationTel. [email protected]

Vikas Gupta - Texas InstrumentsTel. [email protected]

1. 1:30 p.m. - X-Ray Micro-CT and Digital-Volume Correlation Based Three-Dimensional Measurements of Deformation and Strain In Operational ElectronicsPradeep Lall and Junchao Wei – Auburn University

2. 1:55 p.m. - Duplicable and Effective – A New Drop Test for BGA AssembliesDongji Xie – NVIDIA Corporation; Andy Zhang – Texas Instruments, Inc.; Hossein Shirangi – Robert Bosch GmbH; Sheldon Schwandt – Blackberry; Brian Roggeman – Qualcomm Technologies, Inc.

3. 2:20 p.m. - A New In-Situ Warpage Measurement of a Wafer with Speckle-Free Digital Image Correlation (DIC) MethodYuling Niu, Seungbae Park, and Hohyung Lee – Binghamton University

4. 3:30 p.m. - The Mechanism and Kinetic Study of Void Migration in Cu Vias under Current Flow by 3D X-Ray Computed TomographyYan Li, Luhua Xu, Pilin Liu, Mario Pachero, Balu Pathangey, Mohammad Hossain, Liang Hu, Rajen Dias, and Deepak Goyal – Intel Corporation

5. 3:55 p.m. - A Novel and Practical Method for In-Situ Monitoring of Interface Delamination by Local Thermal Diffusivity MeasurementBernhard Wunderle – Fraunhofer ENAS; Technische Universität Chemnitz; Marcus Schulz – Technische Universität Chemnitz; AMIC; Tanja Braun, Joerg Bauer, Ole Hoelck, and Hans Walter – Fraunhofer IZM; Daniel May – Technische Universität Chemnitz; Juergen Keller – AMIC

6. 4:20 p.m. - Chip Reliability Improvement by Designing Re-Distribution Layer (RDL) Pattern for Thermal Cycles in Wafer Level Packages (WLP)Sora Park, Donghyun Kim, Dawon Jeong, and Youngkeun Lee, Jongsung Jeon – Samsung Electronics Company, Ltd.

7. 4:45 p.m. - Galvanic Corrosion of Silicon-Based Thin Films: A Case Study of a MEMS MicrophonePetri Mikael Broas, Jue Li, Xuwen Liu, Ge Yanling, Antti Peltonen, Toni T. Mattila, and Mervi Paulasto-Krockel – Aalto University

Committee: Assembly & Manufacturing Technology • Room: Nautilus 3 & 4

Session Co-Chairs:Valerie Oberson - IBM CorporationTel. [email protected]

Jae-Woong Nah - IBM CorporationTel. [email protected]

1. 1:30 p.m. - Thermo-Compression Bonding for Fine-Pitch Copper Pillar Flip Chip Interconnect - Tool Features as Enablers of Unique TechnologyAmram Eitan – Intel Corporation; Kin-Yik Hung – ASM Pacific Technology, Ltd.

2. 1:55 p.m. - Alternative Fine Pitch Solution of Low Cost and High Throughput Thermal Compression Bonding by Using Capillary UnderfillMike Tsai, Yan Han Yao, Meng Yueh Wu, Eason Chen, Roger Lo, Cheng Kai Chang, and Albert Lan – Siliconware Precision Industries Co. Ltd.

3. 2:20 p.m. - Interconnection Materials, Processes and Tools for Fine-Pitch Panel Assembly of Ultra-Thin Glass SubstratesVanessa Smet, Ting-Chia Huang, Bhupender Singh, Venky Sundaram, Pulugurtha Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Satomi Kawamoto – NAMICS Corporation

4. 3:30 p.m. - Extending Advanced Interconnect Technology to Finer Pitches with Conventional Mass ReflowFernando Roa – Amkor Technology, Inc.

5. 3:55 p.m. - Challenge and Process Optimization of Thermal Compression Bonding with Non Conductive PastePo-Jen Cheng, W. C. Wu, W. J. Wang, and T. M. Pai – Advanced Semiconductor Engineering, Inc.

6. 4:20 p.m. - Development of High Throughput Adhesive Bonding Scheme by Wafer-Level Underfill for 3D Die-to-Interposer Stacking with 30µm-Pitch Micro InterconnectionsYu-Wei Huang, Chia-Wen Fan, Chau-Jie Zhan, Su-Mei Chen, Yu-Min Lin, Jing-Ye Juang, Su-Yu Fun, Su-Ching Chung, and Tao-Chih Chang – Industrial Technology Research Institute

7. 4:45 p.m. - WET Cleaning and Surface Preparation Emerging Challenges in Wafer Level Bumping TechnologiesMickael Fourel, Frederic Battegay, and Yannick Sanchez – STMicroelectronics; Patrice Loiodice and Thierry Braisaz – CEA-LETI

Committee: Modeling & Simulation Joint with High-

Speed, Wireless & Components • Room: Nautilus 5

Session Co-Chairs:Dan Oh - Altera CorporationTel. [email protected]

Rockwell Hsu - Cisco Systems, Inc.Tel. [email protected]

1. 1:30 p.m. - Reliable and Accurate Characterization of High Frequency Electrical Material PropertiesYichi Zhang, Leigh Wojewoda, and Kemal Aygun – Intel Corporation

2. 1:55 p.m. - Measurement and Characterization of Backplanes for Serial Links Operating at 56 GbpsWendem Beyene, Dave Secker, Don Mullen, Yeon-Chang Hahm, and Narayanan Mayandi – Rambus, Inc

3. 2:20 p.m. - Enabling Packaging Technology for Emerging 56Gbps Lane Rate TransceiversHong Shi, Suresh Ramalingam, and Shen Dong – Xilinx, Inc.

4. 3:30 PM - SFF-8431 12.5Gbps Channel Return Loss (RL) Failure Debug: Simulation and Measurement ValidationMinhong Mi, Arlo Aude, Jie Chen, and Rajen Murugan – Texas Instruments, Inc.

5. 3:55 p.m. - Coupling Capacitance in Face-to-Face (F2F) Bonded 3D ICs: Trends and ImplicationsTaigon Song and Sung Kyu Lim – Georgia Institute of Technology; Arthur Nieuwoudt – Synopsys Inc.; Yun Seop Yu – Hankyong National University

6. 4:20 p.m. - Multi-28Gbps Serial-Link FCBGA Equipped DC-Block Capacitors on the PackageKazuyuki Nakagawa, Takuji Komeda, Shinji Katayama, Hiroyuki Uchida, and Shinji Baba – Renesas Electronics Corporation; Masahiro Toyama and Yutaka Uematsu – Hitachi, Ltd.

7. 4:45 p.m. - A Frequency-Domain High-Speed Bus Signal Integrity Compliance Model: Design Methodology and ImplementationJose A. Hejase, Si T. Win, Wiren D. Becker, Glen A. Wiedemeier, and Daniel M. Dreps – IBM Corporation

Program Sessions: Wednesday, May 27, 1:30-5:10 p.m.

Refreshment Break: 2:45-3:30 p.m.

Session 10: Advanced Reliability Tests and Failure Analysis Methodologies

Session 11: Thermal Compression Bonding: Challenges & Process Improvement

Session 12: Advances in Signal Integrity

17

Page 18: 65th ECTC Advance Program

Committee: Advanced PackagingRoom: Harbor Island 1

Session Co-Chairs:Rozalia Beica - Yole [email protected]

John Knickerbocker - IBM CorporationTel. [email protected]

1. 8:00 a.m. - Alternative Integration Scheme of Backside Via Reveal (BVR) for Via-Middle Through-Silicon Via (TSV) FlowJengyi Yu, Stefan Detterbeck, CheePing Lee, Sanjay Gopinath, Praveen Nalla, Matthew Thorum, Prashant Meshram, Akhil Singhal, Joe Richardson, Arthur Kolics, and Tom Mountsier – Lam Research Corporation

2. 8:25 a.m. - Development of Chip-on-Wafer (CoW) Stacked Chip Packaging for High-End CIS ApplicationT. Ni, L. Lien, N. Chen, K. Y. Huang, W. Chang, K. W. Chung, W. Huang, R. Wang, M. J. Chen, A. Liu, and S. C. Hsu – Powertech Technology Inc.

3. 8:50 a.m. - Monolithic Integration of III-V HEMT and Si-CMOS through TSV-less 3D Wafer StackingKwang Hong Lee, Shuyu Bao, David Kohen, Chieh Chih Huang, Kenneth Eng Kian Lee, and Eugene Fitzgerald – Singapore-MIT Alliance for Research & Technology; Chuan Seng Tan – Nanyang Technological University

4. 10:00 a.m. - Physicochemical Effects of Seed Structure and Composition on TSV Fill PerformanceJ. Chen, K. Fujita, D. Goodman, J. Chiu, and D. Papapanayiotou – TEL-NEXX Inc.

5. 10:25 a.m. - A Comprehensive Reliability Study on a CoWoS 3D IC Package Ganesh Hariharan, Raghunandan Chaware, Inderjit Singh, Jeff Lin, Laurene Yip, Kenny Ng, and S. Y. Pai – Xilinx, Inc.

6. 10:50 a.m. - TSV Cu Pumping Analysis and Prevention for 3D IntegrationDaniel Smith, Yudesh Ramnath, Mohamed Rabie, Dingyou Zhang, and Luke England – GLOBALFOUNDRIES; Sanjeev Singh – Nanometrics, Inc.

7. 11:15 a.m. - Fine Pitch 3D-TSV Based High Frequency Components for RF MEMS ApplicationsWolfgang Vitale and Adrian Lonescu – École Polytechnique Fédérale de Lausanne; Montserrat Fernández-Bolaños – Armasuisse - Science and Technology; Reinhard Merkel, Josef Weber, and Peter Ramm – Fraunhofer EMFT; Amin Enayati, Ilja Ocket, and Walter De Raedt – IMEC

Committee: InterconnectionsRoom: Harbor Island 2

Session Co-Chairs:Bernd Ebersberger - Intel Mobile CommunicationsTel. [email protected] Lou Nicholls - Amkor Technology, Inc.Tel. [email protected]

1. 8:00 a.m. - Development and Electrical Investigation of Novel Fine-Pitch Cu/Sn Pad Bumping Using Ultra-Thin Buffer Layer Technique in 3D IntegrationYu-Sheng Hsieh, Yao-Jen Chang, and Kuan-Neng Chen – National Chiao Tung University

2. 8:25 a.m. - Evaluation of Sn Based Microbumping Technology for Hybrid IR Detectors, 10µm Pitch to 5µm PitchPhilippe Soussan and Bivragh Majeed – IMEC; Pascal Le Boterf and Pierre Bouillon – SOFRADIR

3. 8:50 a.m. - A High Throughput and Reliable Thermal Compression Bonding Process for Advanced Packaging InterconnectionMing Li, Dewen Tian, YM Cheung, Lei Yang, and John Lau – ASM Pacific Technology, Ltd.

4. 10:00 a.m. - FC Cu Pillar Package Development for Broad Market ApplicationsWei-Jen Wang, Benjamin Pai, Calvin Cheung, Jenny Chang, and Robert Cheng – Advanced Semiconductor Engineering, Inc.

5. 10:25 a.m. - Quantifying Impact of Design Parameters on Ultra-Low K ILD Reliability in Fine Pitch Cu Bump Interconnect StructuresAndy Bao, Tong Cui, Ahmer Syed, Steve Bezuk, and Lily Zhao – Qualcomm Technologies, Inc.

6. 10:50 a.m. - Electromigration Immortality of Purely Intermetallic Micro-Bump for 3D IntegrationHsiao-Yun Chen, C. H. Tung, Y. L. Hsiao, J. L. Wu, Y. C. Yeh, Larry L. C. Lin, and Douglas C. H. Yu – Taiwan Semiconductor Manufacturing Company; Chih Chen – National Chiao Tung University

7. 11:15 a.m. - The Impact and Performance of Electromigration on Fine Pitch Cu Pillar with Different Bump Structure for Bump on Trace Flip Chip PackagingKuei Hsiao Kuo, Cindy Mao, Jason Lee, Katch Wang, F.L. Chien, and Rick Lee – Siliconware Precision Industries Co., Ltd.

Committee: Applied ReliabilityRoom: Harbor Island 3

Session Co-Chairs:Keith Newman – Hewlett-PackardTel. [email protected]

Donna M. Noctor - Siemens Industry, Inc.Tel. [email protected]

1. 8:00 a.m. - Size Effect on Ductile-to-Brittle Transition in Cu-Solder-Cu Micro-JointsYaodong Wang, Igor M. De Rosa, and K. N. Tu – University of California, Los Angeles

2. 8:25 a.m. - High Strain Rate Properties of SAC305 Leadfree Solder at High Operating Temperature after Long-Term StoragePradeep Lall, Di Zhang, and Jeff Suhling – Auburn University

3. 8:50 a.m. - Reduction of Thermal Expansion Coefficient of Electrodeposited CopperKazuo Kondo, Shingo Mukahara, Taro Hayashi, and Masayuki Yokoi – Osaka Prefecture University; Jin Onuki – Ibaragi University

4. 10:00 a.m. - Reliability of Copper Wirebonds over Through-Silicon Vias for SiGe Power AmplifiersJeff Gambino, Rich Graf, Bill Guthrie, Jim Salimeno, and Jerry Nuzback – IBM Corporation

5. 10:25 a.m. - Effect of Cu Grain Boundary Sliding on TSV ExtrusionChenglin Wu, Tengfei Jiang, Jay Im, Rui Huang and Paul Ho – University of Texas, Austin

6. 10:50 a.m. - First Demonstration of Copper-Plated Through-Package-Via Reliability in Ultrathin 3D Glass Interposers with Double-Side Component AssemblyKaya Demir, Saumya Gandhi, Raghu Pucha, Vanessa Smet, Venky Sundaram, P. Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Tomonori Ogawa – Asahi Glass Company

7. 11:15 a.m. - Through Glass Vias (TGV) and Aspects of ReliabilityMatthew Lueck and Alan Huffman – RTI International; Aric Shorey – Corning, Inc.

Program Sessions: Thursday, May 28, 8:00-11:40 a.m.

Refreshment Break: 9:15-10:00 a.m.

18

Session 13: 3D Integration, TSV, and Reliability

Session 14: Flip Chip: Bonding, Chip-Package Interaction, and Electromigration

Session 15: 3D Technology: Materials and Reliability

Page 19: 65th ECTC Advance Program

Committee: Emerging TechnologiesRoom: Nautilus 1 & 2

Session Co-Chairs:Nancy Stoffel - GE Global ResearchTel. [email protected]

Joana Maria - IBM CorporationTel. [email protected]

1. 8:00 a.m. - Programmable e-Textile Composite Circuit Matija Varga, Niko Münzenrieder, Christian Vogt, and Gerhard Tröster – Swiss Federal Institute of Technology

2. 8:25 a.m. - Integrated Bioflexible Electronic Device for Electrochemical Analysis of BloodSarkis Babikian, G. P. Li, and Mark Bachman – University of California, Irvine

3. 8:50 a.m. - Active and Passive Integration on Flexible Glass Substrates: Subtractive Single Micron Metal Interposers and High Performance IGZO Thin Film TransistorsMark D. Poliks, Joshua Hewlett, Robert Malay, Abhishek Nandur, Rajesh Vaddi, and Bruce White – Binghamton University; Sean Garner, Ming-Huang Huang, and Scott Pollard – Corning, Inc.

4. 10:00 a.m. - Room Temperature Direct Bonding and Debonding of Polymer Film on Glass Wafer for Fabrication of Flexible Electronic DevicesKai Takeuchi, Masahisa Fujino, Tadatomo Suga, Mari Koizumi, and Takao Someya – University of Tokyo

5. 10:25 a.m. - Paper-Based Magneto-Electronics: Magnetoresistance of Permalloy onto Paper SubstratesMeriem Akin and Lutz Rissing – Universität Hannover

6. 10:50 a.m. - Ultra-Thin Chip-in-Flex (CIF) Technology Using Anisotropic Conductive Films (ACFs) for Wearable Electronics ApplicationsJi-Hye Kim, Ji-Won Shin, Yoo-Sun Kim, Tae-ik Lee, and Kyung-Wook Paik – KAIST

7. 11:15 a.m. - New Insulating Adhesive Film for Future High-Frequency Wearable DevicesMasaki Yoshida, Shin Teraki, and Satoko Takahashi – NAMICS Corporation

Committee: Modeling & SimulationRoom: Nautilus 3 & 4

Session Co-Chairs:Kemal Aygun - Intel CorporationTel. [email protected]

Zhaoqing Chen - IBM CorporationTel. [email protected]

1. 8:00 a.m. - A Simulation and Measurement Study of On-Chip Supply Noises in Multi-Gbps Serial InterfaceMinghui Han, Amir Amirkhany, and Wei Xiong – Samsung Display

2. 8:25 a.m. - Temperature-Aware Power Distribution Network Design for 3D ICs and SystemsSung Joo Park and Madhavan Swaminathan – Georgia Institute of Technology

3. 8:50 a.m. - Signal and Power Integrity Analysis in 2.5D Integrated Circuits (ICs) with Glass, Silicon and Organic InterposerYoungwoo Kim, Jonghyun Cho, Kiyeong Kim, and Joungho Kim – KAIST; Venky Sundaram and Rao Tummala – Georgia Institute of Technology

4. 10:00 a.m. - Accurate CPM Based Early Design Stage SERDES PDN Optimization in Mobile PlatformYongho Lee, Sanggwoun Lee, Jaehyun Park, and Jaemin Shin – Samsung Electronics Company, Ltd.

5. 10:25 a.m. - Impact of PCB Decoupling on Device Electromigration PerformanceGuang Chen, Janani Chandrasekhar, Dan Oh, and Hui Liu – Altera Corporation

6. 10:50 a.m. - IR Drop Analysis in Mobile IC Package with Consideration of Self-Heating and Leakage PowerZheng Qin, Zhi Wang, He Ma, and Daquan Yu – Chinese Academy of Sciences; Shuqiang Zhang – Apache Design Solutions, Inc.

7. 11:15 a.m. - An Accurate On-Chip Design Estimation for Mitigating EMI Effects in a Large-Scale Integration ChipSungwook Moon, Jinho Kim, Jihyun Lee, Taeyong Kim, and Kyongho Kim – Samsung Electronics Company, Ltd.

Committee: OptoelectronicsRoom: Nautilus 5

Session Co-Chairs:Harry G. Kellzi - Teledyne Microelectronic TechnologiesTel. [email protected]

Ping Zhou - LDX Optronics, Inc.Tel. [email protected]

1. 8:00 a.m. - Hybrid Integration and Packaging of an Ultralow Energy WDM Silicon Photonic Chip-to-Chip InterconnectH. D. Thacker, J. Lexau, X. Zheng, S. S. Djordjevic, S. Lin, J. Simons, P. Amberg, E. Chang, and I. Shubin – Oracle; R. Shafiiha and A. Abed – Mellanox

2. 8:25 a.m. - Low-Loss Single-Mode Polymer Optical Waveguide at 1550-nm Wavelength Compatible with Silicon PhotonicsTakaaki Ishigure, Sho Yoshida, Kazuki Yasuhara, and Daisuke Suganuma – Keio University

3. 8:50 a.m. - Automated, Self-Aligned Assembly of 12 Fibers per Nanophotonic Chip with Standard Microelectronics Assembly ToolingTymon Barwicz, Nicolas Boyer, Stephane Harel, Alexander Janta-Polczynski, Swetha Kamlapurkar, Sebastian Engelmann, Yurii Vlasov, and Paul Fortier – IBM Corporation; Ted Lichoulas and Eddie Kimbrell – AFL Telecommunications

4. 10:00 a.m. - 40 Gb/s Card-Edge Connected Optical Transceiver Using Novel High-Speed ConnectorTakatoshi Yagisawa, Takashi Shiraishi, Mariko Sugawara, and Kazuhiro Tanaka – Fujitsu Laboratories, Ltd.; Yasuyuki Miki, Takahiro Kondou, and Mitsuru Kobayashi – Fujitsu Component Ltd.

5. 10:25 a.m. - Thin Glass Based Electro-Optical Circuit Board (EOCB) with Through Glass Vias, Gradient-Index Multimode Optical Waveguides and Collimated Beam Mid-Board Coupling InterfacesLars Brusberg, Henning Schröder, and Dominik Pernthaler – Fraunhofer IZM; Christian Ranzinger – Contag AG; Marco Queisser, Christian Herbst, Sebastian Marx, Jens Hofmann, Marcel Neitz, and Klaus-Dieter Lang – Technical University of Berlin

6. 10:50 a.m. - Assembly and Demonstration of High Bandwidth-Density Optical MCMMasao Tokunari, Hsiang Han Hsu, and Shigeru Nakagawa – IBM Corporation

7. 11:15 a.m. - Self-Aligned Chip-to-Chip Optical Interconnections for Ultra-Thin 3D Glass InterposersWilliam Vis, Bruce C Chou, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology

Program Sessions: Thursday, May 28, 8:00-11:40 a.m.

Refreshment Break: 9:15-10:00 a.m.

Session 16: Wearable, Bendable, Flexible Electronics

Session 17: Advances in Power Integrity and Electromagnetic Interference

Session 18: Advanced Optical Interconnects

19

Page 20: 65th ECTC Advance Program

Committee: Advanced Packaging Joint with Applied Reliability • Room: Harbor Island 1

Session Co-Chairs:Peter Ramm - Fraunhofer EMFTTel. [email protected]

Lakshmi N. Ramanathan - Microsoft CorporationTel. +1-425-421-3838 [email protected]

1. 1:30 p.m. - Effect of Au/Pd Surface Finishing on Metastable Sn Phase Formation in MicrobumpsYingxia Liu and K N. Tu – University of California, Los Angeles; Nobumichi Tamura – Lawrence Berkeley National Laboratory; Dong-Wook Kim and Sam Gu – Qualcomm Technologies, Inc.

2. 1:55 p.m. - Mechanical and Electrical Reliability Assessment of Bumpless Wafer-on-Wafer Integration with One-Time Bottom-Up TSV FillingYong Guan, Yunhui Zhu, Qinghua Zeng, Jing Chen, Yufeng Jin, Yuan Bian, and Xiao Zhong – Peking University; Shenglin Ma – Peking University; Xiamen University; Fei Su – Beijing University of Aeronautics and Astronautics

3. 2:20 p.m. - Impact of Deep-Via Plasma Etching Process on Transistor Performance in 3D-IC with Via-Last Backside TSVYohei Sugawara, Hideto Hashiguchi, Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Kangwook Lee, Mitsumasa Koyanagi, and Tetsu Tanaka – Tohoku University

4. 3:30 p.m. - Silicon Interposer with Embedded Microfluidic Cooling for High-Performance Computing SystemsLi Zheng, Yang Zhang, and Muhannad Bakir – Georgia Institute of Technology

5. 3:55 p.m. - Embedded Power Insert Enabling Dual-Side Cooling of MicroprocessorsThomas Brunschwiler, Dominic Gschwend, Stephan Paredes, Timo Tick, Keiji Matsumoto, and Stefano Oggioni – IBM Corporation; Uwe Zschenderlein – Technische Universität Chemnitz; Mario Baum – FhG - ENAS; Christoph Lehnberger and Jens Pohl – Andus

6. 4:20 p.m. - Thermal Management of 3D Stacked Dies with Air Convection and Water Cooling MethodsDelong Qiu, Liqiang Cao, Xiaomeng Wu, Fengze Hou, Jing Zhang, and Qidong Wang – Chinese Academy of Sciences

7. 4:45 p.m. - Failure Analysis of Complex 3D Stacked-Die IC Packages Using Microwave Induced Plasma Afterglow DecapsulationJiaqi Tang – JIACO Instruments B.V.; Sharon Furcone and Mitch Curiel – Freescale Semiconductor; Ewald Reinders and Kees Revenberg – Maser Engineering; Kees Beenakker – Delft University of Technology

Committee: Advanced Packaging Joint with Assembly &

Manufacturing Technology • Room: Harbor Island 2

Session Co-Chairs:Muhannad Bakir - Georgia Institute of Technology Tel. [email protected]

Paul Tiner - Texas InstrumentsTel. [email protected]

1. 1:30 p.m. - Wafer Level Dicing Method Using Metal-Assisted Chemical EtchingYusaku Asano, Keiichiro Matsuo, Hisashi Ito, Kazuhito Higuchi, Kazuo Shimokawa, and Tsuyoshi Sato – Toshiba Corporation

2. 1:55 p.m. - A Flexible Interconnect Technology Demonstrated on a Wafer-Level Chip Scale PackageSu-Chun Yang, Chung-Jung Wu, Yi-Li Hsiao, Chih-Hang Tung, and Douglas C.H. Yu – Taiwan Semiconductor Manufacturing Company

3. 2:20 p.m. - WLCSP+ and eWLCSP in Flexline: Innovative Wafer Level Package ManufacturingYaojian Lin, Eric Chong, Mark Chan, Kok Hwa Lim, and Seung Wook Yoon – STATS ChipPAC, Inc.

4. 3:30 p.m. - Impact of Dynamic Warpage of Mobile DRAM on PoP Stack Assembly YieldJonggi Lee, Kang Lee, Il Kim, Ho Moon, Hyung Baek, Ho Song, Eun Ahn, and Sa Kang – Samsung Electronics Company, Ltd.

5. 3:55 p.m. - Copper Foil Exposed Structure for Thin PoP Warpage Improvement Yeseul Ahn, JinSeong Kim, DongJoo Park, JaeJin Lee, GyuWan Han, JuHoon Yoon, and Chooneung Lee – Amkor Technology, Inc.

6. 4:20 p.m. - Low Cost High Performance Bare Die PoP with Embedded Trace Coreless Technology and “Coreless Cored” Build Up Substrate Manufacture ProcessLeilei Zhang and Joseph Greco – NVIDIA Corporation

7. 4:45 p.m. - A TSV-less PoP Packaging Structure for High Bandwidth MemoryDyi-Chung Hu, Puru Lin, and Yu-Hua Chen – Unimicron Technology Corporation

Committee: Materials & ProcessingRoom: Harbor Island 3

Session Co-Chairs:Myung Jin Yim - Intel CorporationTel. [email protected]

Bing Dang - IBM CorporationTel. [email protected]

1. 1:30 p.m. - Single-Release-Layer Process for Temporary Bonding Applications in the 3D Integration AreaAnne Jourdain, Alain Phommahaxay, Dimitrios Velenis, Andy Miller, Kenneth Rebibis, Gerald Beyer, and Eric Beyne – IMEC; Alice Guerrero, Dongshun Bai, Kim Yess, and Kim Arnold – Brewer Science, Inc.

2. 1:55 p.m. - Material Development for 3D Wafer Bond and De-Bonding ProcessTakashi Mori, Torahiko Yamaguchi, Yooichiroh Maruyama, Koichi Hasegawa, and Shiro Kusumoto – JSR Corporation

3. 2:20 p.m. - Influencing Factors in High Precision Fusion Wafer Bonding for Monolithic IntegrationThomas Uhrmann, Florian Kurz, Thomas Plach, Thomas Wagenleitner, Viorel Dragoi, Markus Wimplinger, and Paul Lindner – EVGroup

4. 3:30 p.m. - Effects of Thermo-Compression Bonding Parameters on Joint Formation of Micro-Bumps in Non-Conductive Film (NCF)Ji-won Shin, Young Soon Kim, Hyoung Gi Lee, and Kyoung-Wook Paik – KAIST; Un Byung Kang and Sun Kyung Seo – Samsung Electronics Company, Ltd.

5. 3:55 p.m. - Defect Mitigation of Plasma-Induced Delamination of TiW/Cu from SiNx layer in Thin Si Interposer Processing with Glass CarriersVijay Sukumaran, Thuy Tran-Quinn, Jorge Lubguban, Dave Webster, Brittany Hedrick, Harry Cox, James Wood, Hiroyuki Miyazoe, Hongwen Yan, Eric Joseph, and Hongqing Zhang – IBM Corporation

6. 4:20 p.m. - Demonstration of 20µm Pitch Micro-Vias by Excimer Laser Ablation in Ultra-Thin Dry-Film Polymer Dielectrics for Multi-Layer RDL on Glass InterposersYuya Suzuki – Zeon Corporation; Georgia Institute of Technology; Jan Brune, Rolf Senczuk, and Rainer Pätzel – Coherent LaserSystems GmbH & Co. KG; Ryuta Furuya – Ushio Inc.; Fuhan Liu, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology

7. 4:45 p.m. - Characterization of 3D Stacked High Resistivity Si Interposers with Polymer TSV Liners for 3D RF ModuleKwang-Seong Choi, Haksun Lee, Hyun-Cheol Bae, Yong-Sung Eom, and Jin Ho Lee – ETRI; Kangwook Lee, Takafumi Fukushima, and Mitsumasa Koyanagi – Tohoku University

Program Sessions: Thursday, May 28, 1:30-5:10 p.m.

Refreshment Break: 2:45-3:30 p.m.

20

Session 19: 3D Technology: Thermal and Performance Reliability

Session 20: Wafer Level Packaging and PoP

Session 21: 3D Materials and Processing

Page 21: 65th ECTC Advance Program

Committee: Emerging TechnologiesRoom: Nautilus 1 & 2

Session Co-Chairs:Vasudeva P. Atluri - Renavitas TechnologiesTel. [email protected]

Kevin J. Lee - Intel CorporationTel. [email protected]

1. 1:30 p.m. - A Fully Integrated High Power RF MEMS Switch in PackageSung Jun Kim, Yang Zhang, Minfeng Wang, Mark Bachman, and G. P. Li – University of California, Irvine

2. 1:55 p.m. - Nanomagnetic Structures for Inductive Coupling and Shielding for Wireless Charging ApplicationsDibyajat Mishra, Srikrishna Sitaraman, P. Markondeya Raj, Himani Sharma, and Rao Tummala – Georgia Institute of Technology; T. N. Arunagiri, Z. Dord, R. Mullapudi – Tango Systems

3. 2:20 p.m. - Micro-Fabricated Spherical Rubidium Vapor Cell and Its Integration in 3-Axis Atomic MagnetometerYu Ji, Jintang Shang, Qi Gan, and Lei Wu – Southeast University; Ching-Ping Wong – The Chinese University of Hong Kong

4. 3:30 p.m. - Full SiC Half-Bridge Module for High Frequency and High Temperature OperationSlavomir Kicin, Sami Pettersson, Francisco Canales, Didier Cottet, Enea Bianda, Giacomo Cavallini, and Joris Hamers – ABB Ltd.

5. 3:55 p.m. - Vertical Integration of Memristors onto Foundry CMOS Dies Using Wafer-Scale IntegrationJustin Rofeh, Avantika Sodhi, Melika Payvand, Miguel Angel Lastras-Montaño, Amirali Ghofrani, Advait Madhavan, Sukru Yemenicioglu, Kwang-Ting Cheng, and Luke Theogarajan – University of California, Santa Barbara

6. 4:20 p.m. - Heterogeneous Integration of Ultra-Miniaturized Compound Semiconductor Devices by Micro-Transfer-PrintingChristopher Bower, Matthew Meitl, Alin Fecioru, and David Kneeburg – X-Celeprint Ltd.; Salvatore Bonafede and David Gomez – X-Celeprint Inc.

7. 4:45 p.m. - Inkjet Printed Single Layer High-Density RDL for a MEMS DeviceMika-Matti Laurila, Ayat Soltani, and Matti Mantysalo – Tampere University of Technology

Committee: High-Speed, Wireless & Com-ponents • Room: Nautilus 3 & 4

Session Co-Chairs:Timothy G. Lenihan - TGL ConsultingTel. [email protected]

Craig Gaw - Freescale Semiconductor, Inc.Tel. [email protected]

1. 1:30 p.m. - Silicon Interposer: A Versatile Platform Towards Full-3D Integration of Wireless Systems at Millimeter-Wave FrequenciesOssama El Bouayadi, Laurent Dussopt, Yann Lamy, Christine Ferrandon, Cedric Dehos, Alexandre Siligaris, Gilles Simon, Pierre Vincent, and Brigitte Soulier – CEA-LETI

2. 1:55 p.m. - A Novel Strain Sensor Based on 3D Printing Technology and 3D Antenna DesignTaoran Le, Bo Song, Ryan A. Bahr, Stefano Moscato, Ching-Ping Wong, and Manos M. Tentzeris – Georgia Institute of Technology; Qi Liu – Zhenjiang University; Georgia Institute of Technology

3. 2:20 p.m. - Fully 3D Symmetrical TSV Monolithic Transformer for RFICS. H. Li – Industrial Technology Research Institute (ITRI); National Tsing Hua University; C. S. Lin, P. L. Tseng, P. J. Tzeng, S. S. Sheu, and T. K. Ku – Industrial Technology Research Institute; Shawn S. H. Hsu – National Tsing Hua University

4. 3:30 p.m. - Low-Profile Fully Integrated 60 GHz 18 Element Phased Array on Multilayer Liquid Crystal Polymer Flip Chip PackageTelesphor Kamgaing, Adel Elsherbini, Sasha Oster, and Emanuel Cohen – Intel Corporation

5. 3:55 p.m. - Through Glass Via (TGV) Disc Loaded Monopole Antennas for Millimeter-Wave Wireless Interposer CommunicationSeahee Hwangbo, Arian Rahimi, Cheolbok Kim, and Yong-Kyu Yoon – University of Florida; Hae-Yong Yang – ETRI

6. 4:20 p.m. - A Multilayer Organic Package with Four Integrated 60GHz Antennas Enabling Broadside and End-Fire Radiation for Portable Communication DevicesXiaoxiong Gu, Duixian Liu, Christian Baks, Bodhisatwa Sadhu, and Alberto Valdes-Garcia – IBM Corporation

7. 4:45 p.m. - Investigation of Modulation-Capable Silicon Waveguides for Efficient On-Wafer Terahertz InterconnectsJoshua Myers, Amanpreet Kaur, Jennifer Byford, and Prem Chahal – Michigan State University

Committee: Modeling & SimulationRoom: Nautilus 5

Session Co-Chairs:Xuejun Fan - Lamar UniversityTel. +1-409-880-7792 [email protected]

Sheng Liu - Huazhong University of Science and TechnologyTel. +86-27-87542604 [email protected]

1. 1:30 p.m. - A Fundamental Computational Study of 3-D Non-Planar Fracture in Solder JointsIbrahim Guven – Virginia Commonwealth University

2. 1:55 p.m. - Crystal Plasticity Finite Element Analysis of Electromigration Induced Deformation Behavior in Lead-Free Solder JointsJiamin Ni and Antoinette Maniatty – Rensselaer Polytechnic Institute; Yong Liu and Jifa Hao – Fairchild Semiconductor Corporation

3. 2:20 p.m. - Investigation on the Thermal Degradation Mechanism of Cu-Sn Intermetallic Compound in SAC Solder Joints with Cohesive Zone ModelingChaoran Yang and S. W. Ricky Lee – Hong Kong University of Science & Technology

4. 3:30 p.m. - Analysis of Copper Plasticity Impact in TSV-Middle and Backside TSV-Last Fabrication ProcessesWei Guo, Geert Van der Plas, Stefaan Van Huylenbroeck, Mario Gonzalez, Philippe Absil, and Eric Beyne – IMEC; Aditya P. Karmarkar, Xiaopeng Xu, and Karim El Sayed – Synopsys, Inc.

5. 3:55 p.m. - Multiphysics-Modeling of Corrosion in Copper-Aluminum Interconnects in High Humidity EnvironmentsPradeep Lall and Yihua Luo – Auburn University; Luu Nguyen – Texas Instruments, Inc.

6. 4:20 p.m. - Methods to Reduce Thermal Stress for TSV Scaling “TSV with Novel Structure: Annular-Trench-Isolated TSV”Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, and Masahiro Aoyagi – National Institute of Advanced Industrial Science and Technology (AIST)

7. 4:45 p.m. - Chip Package Interactions: Package Effects on Copper Pillar Bump Induced BEoL Delaminations & Associated Numerical DevelopmentsSebastien Gallois-Garreignot, Guojun Hu, Vincent Fiori, Marika Sorrieul, Caroline Moutin, and Clement Tavernier – STMicroelectronics

Program Sessions: Thursday, May 28, 1:30-5:10 p.m.

Refreshment Break: 2:45-3:30 p.m.

Session 22: Packaging for Internet of Things

Session 23: Emerging Wireless Technologies

Session 24: Advanced Modeling in Solder Joints, TSVs, and Copper Wire Bonding

21

Page 22: 65th ECTC Advance Program

Committee: Advanced PackagingRoom: Harbor Island 1

Session Co-Chairs:Jianwei Dong - Dow Electronic Materials Tel. [email protected]

Christopher Bower- X-Celeprint Ltd.Tel. [email protected]

1. 8:00 a.m. - Novel Embedded Z Line (EZL) Vertical Interconnect Technology for eWLBMaciej Wojnowski, Klaus Pressel, and Gottfried Beer – Infineon Technologies

2. 8:25 a.m. - Large Area Compression Molding for Fan-Out Panel Level PackagingTanja Braun, Karl-Friedrich Becker, Stefan Raatz, Volker Bader, Jörg Bauer, and Rolf Aschenbrenner – Fraunhofer IZM; Steve Voges, Tina Thomas, Ruben Kahle, and Klaus-Dieter Lang – Technical University Berlin

3. 8:50 a.m. - Integrated Module Structure of a Fan-Out Wafer Level Package for a Terahertz AntennaDaijiro Ishibashi, Shinya Sasaki, Yoshikatsu Ishizuki, Shinya Iijima, Yoshihiro Nakata, Yoichi Kawano, Toshihide Suzuki, and Motoaki Tani – Fujitsu Laboratories, Ltd.

4. 10:00 a.m. - 0.35mm Pitch Wafer Level Package Board Level Reliability: Studying Effect of Ball Depopulation with Varying Ball SizeBeth Keser, Rey Alvarado, Mark Schwarz, and Steve Bezuk – Qualcomm Technologies, Inc.

5. 10:25 a.m. - Development of Very Large Fan-In WLP/WLCSP for Volume ProductionVitor Chatinho – NANIUM S.A.

6. 10:50 a.m. - A Wafer Level Approach for LED Packaging Using TSV Last TechnologyMarion Volpert, Brigitte Soulier, Stephan Borel, Nacer Ait-Mani, Stephanie Gaugiran, A. Gasse, and David Henry – CEA-LETI

7. 11:15 a.m. - Silicon-Packaged GaN Power HEMTs with Integrated Heat SpreadersFlorian Herrault, Melanie Yajima, Alex Margomenos, Andrea Corrion, Keisuke Shinohara, and Miro Micovic – HRL Laboratories

Committee: InterconnectionsRoom: Harbor Island 2

Session Co-Chairs:James E. Morris - Portland State UniversityTel. [email protected]

Nathan Lower - Rockwell Collins, Inc.Tel. +1-319-295-6687 [email protected]

1. 8:00 a.m. - Nanoparticle Assembly and Sintering Towards All-Copper Flip Chip InterconnectsJonas Zürcher, Gerd Schlottig, and Thomas Brunschwiler – IBM Corporation; Yu Kerry – Intrinsiq Materials Ltd.; Mario Baum – Fraunhofer ENAS; Maaike M. Visser Taklo – SINTEF; Bernhard Wunderle – Technische Universität Chemnitz; Piotr Warszynski - Jerzy Haber Institute of Catalysis and Surface Chemistry PAS

2. 8:25 a.m. - A Novel Non-Solder Based Board-to-Board Interconnection Technology for Smart Mobile and Wearable ElectronicsSung Jin Kim, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Young Soo Kim and Chong K. Yoon – UNID Corporation, Ltd.

3. 8:50 a.m. - Diffusional Hillock Growth in Ag Stress Migration Bonding for Power Device InterconnectionsChulmin Oh, Shijo Nagao, and Katsuaki Suganuma – Osaka University

4. 10:00 a.m. - Experimental Thermal Characterization and Thermal Model Validation of 3D Packages Using a Programmable Thermal Test ChipHerman Oprins, Vladimir Cherman, Geert Van der Plas, Joeri De Vos, Teng Wang, Robert Daily, and Eric Beyne – IMEC; Federica Maggioni – IMEC; Katholieke Universiteit Leuven

5. 10:25 a.m. - Durability of Screen Printed Electrical Interconnections on Woven TextilesAbiodun Komolafe, Russel Torah, Kai Yang, John Tudor, and Steve Beeby – University of Southampton

6. 10:50 a.m. - Non-Destructive Stress Evaluation by Raman Spectroscopy of Flip Chip Thin Die on Organic Substrate Assembled by TCBToshihisa Nonaka, Ryuichi Sugie, Aki Suzuki, and Mototaka Ito – Toray Research Center, Inc.

7. 11:15 a.m. - Selective Electrophoretic Deposition of ACA Conductive ParticlesJunlei Tao, David Whalley, and Changqing Liu – Loughborough University; Mengyao Qin and Fengshun Wu – Huazhong University of Science and Technology; Helge Kristiansen – Conpart A.S.

Committee: Modeling & Simulation Joint with Materials & Processing • Room: Harbor Island 3

Session Co-Chairs:Gamal Refai-Ahmed - PreQual Technologies Corp.Tel. [email protected]

Yu-Hua Chen - UnimicronTel. +886-3-5995899#[email protected]

1. 8:00 a.m. - Hybrid TTSV Structure for Heat Mitigation and Energy Harvesting in 3-D ICTamal Ghosh, G. C. Gagan, Ashudeb Dutta, Vanjari Sivaramakrishna, and Shiv Govind Singh – Indian Institute of Technology, Hyderabad

2. 8:25 a.m. - Modeling, Design and Demonstration of Ultra-Miniaturized Glass PA Modules with Efficient Thermal DissipationMin Suk Kim, Sangbeom Cho, Junki Min, Markondeya Raj Pulugurtha, Nathan Huang, Srikrishna Sitaraman, Venky Sundaram, Yogendra Joshi, and Rao Tummala – Georgia Institute of Technology; Mario Velez – Qualcomm Technologies, Inc.; Arjun Ravindran – TDK-Epcos

3. 8:50 a.m. - Fast Thermal Coupling Simulation of On-Chip Hot Interconnect for Thermal-Aware EM MethodologyStephen Pan and Norman Chang – ANSYS

4. 10:00 a.m. - Dual-Side Cooling for a Three-Dimensional (3D) Chip Stack: Additional Cooling from the Laminate (Substrate) Side Keiji Matsumoto, Hiroyuki Mori, and Yasumitsu Orii – IBM Corporation

5. 10:25 a.m. - Barrier Material Selection for TSV Last, Flipchip & 3D - UBM & RDL IntegrationsFrederic Battegay and Mickael Fourel – STMicroelectronics

6. 10:50 a.m. - Effects of Cleaning Process on the Reliability of Ultra-Fine Gap for 3D PackageMu-Hsuan Chan, Chun-Tang Lin, Brock Hsue, Steve Chiu, and Yu-Po Wang – Siliconware Precision Industries Co., Ltd.

7. 11:15 a.m. - Preparation of Reversible Thermosets and Their Application in Temporary Adhesive for Thin Wafer HandlingL. Deng, X. Shuai, G. Zhang, and R. Sun – Chinese Academy of Sciences; H. Fang – Chinese Academy of Sciences; Sun Yat-Sun University; C. P. Wong – Georgia Institute of Technology; The Chinese University of Hong Kong

Program Sessions: Friday, May 29, 8:00-11:40 a.m.

Refreshment Break: 9:15-10:00 a.m.

22

Session 25: Fan-Out and Wafer Level Packaging

Session 26: Innovative Interconnection Technologies

Session 27: 3D Technology: Thermal Materials and Modeling

Page 23: 65th ECTC Advance Program

Committee: Emerging Technologies Joint with Interconnections • Room: Nautilus 1 & 2

Session Co-Chairs:C. S. Premachandran - GLOBALFOUNDRIES Tel. [email protected]

Changqing Liu - Loughborough UniversityTel. [email protected]

1. 8:00 a.m. - Planarity-Tolerant Fine-Pitch Reworkable Interconnections with Sharp Protrusions and Micro-BumpsYang Liu, Steven Wright, Jae-Woong Nah, Bing Dang, Yu Luo, and John Knickerbocker – IBM Corporation

2. 8:25 a.m. - Novel Copper Metallization Schemes on Ultra-Thin, Bare Glass Interposers with Through-ViasTimothy Huang, Bruce Chou, Jialing Tong, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology

3. 8:50 a.m. - Joining of Silver Nanoparticles by a Femtosecond Laser Irradiation MethodSu Ding, Yanhong Tian, Zhi Jiang, and Chenxi Wang – Harbin Institute of Technology

4. 10:00 a.m. - Challenges of Flip Chip Packaging with Embedded Fine Line and Multi-Layer Coreless SubstrateTom Tang, Albert Lan, and Jensen Tsai, Steven Lin, Yuchi Xiao, Wilson Chen, and Jake You – Siliconware Precision Industries Co., Ltd.

5. 10:25 a.m. - Feature Resolution Capability for Stencil Printed TLPS Paste Interconnect StructuresCatherine Shearer, Ken Holcomb, and Jim Haley – Ormet Circuits, Inc.

6. 10:50 a.m. - Thermomechanical Behavior of Nanotwinned Copper Interconnection Line in Wafer Level Packaging and the Influence on Wafer WarpageHeng Li, Chunsheng Zhu, Gaowei Xu, and Le Luo – Chinese Academy of Sciences; Shenwu Tian – Hubei University for Nationalities

7. 11:15 a.m. - Mechanical Properties of Intermetallic Compounds in Transient Liquid Phase Sinter JointsHannes Greve, Ali Moeini, and Patrick McCluskey – University of Maryland

Committee: Materials & ProcessingRoom: Nautilus 3 & 4

Session Co-Chairs:Kwang-Lung Lin - National Cheng Kung UniversityTel. [email protected]

Dwayne Shirley - Qualcomm Technologies, Inc.Tel. [email protected]

1. 8:00 a.m. - Thermal Cycling Reliability of Sn-Zn Lead-Free Solders in Sensor ApplicationM. Mostofizadeh and L. Frisk – Tampere University of Technology; D. Das and M. Pecht – University of Maryland

2. 8:25 a.m. - Bonding of SiC Chips to Copper Substrates Using Ag-In SystemShou-Jen Hsu and Chin C. Lee – University of California, Irvine

3. 8:50 a.m. - Developments of Bi-Sb-Cu Alloys as a High-Temperature Pb-Free SolderJunghyun Cho and Sandeep Mallampati – Binghamton University; Harry Schoeller – Universal Instruments Corporation; Liang Yin and David Shaddock – GE Global Research

4. 10:00 a.m. - WLCSP CTE Failure Mitigation Via Solder Sphere Alloy Hikaru Nomura, Shunsaku Yoshikawa, and Ken Tachibana – Senju Metal Industry Co. (SMIC); Derek Daily and Ayano Kawa – Senju Comtek Corp.

5. 10:25 a.m. - Effect of Fullerene C60 & C70 on the Microstructure and Properties of 96.5Sn-3Ag-0.5Cu SolderGuang Chen – Huazhong University of Science & Technology; Loughborough University; Fengshun Wu – Huazhong University of Science & Technology; Changqing Liu – Loughborough University; Y. C. Chan – The City University of Hong Kong

6. 10:50 a.m. - The Improvements of High Temperature Zn-Based Lead Free Solder Xiaodan Wu, Jianxing Li, and Tora Unuvar – Honeywell International, Inc.; Vemal Raja Manikam and Erik Nino Tolentino – On Semiconductor

7. 11:15 a.m. - NiSn4 in Solder Joints between Sn-3.5Ag and Ni, ENIG or ENEPIGSergey Belyakov and Christopher Gourlay – Imperial College London

Committee: OptoelectronicsRoom: Nautilus 5

Session Co-Chairs:Soon Jang - ficonTEC USATel. [email protected]

Henning Schroeder - Fraunhofer IZMTel. [email protected]

1. 8:00 a.m. - Semiconductor Optical Amplifier (SOA) Packaging for Scalable and Gain-Integrated Silicon Photonic Switching Platforms Russell Budd, Laurent Schares, Benjamin G. Lee, Fuad Doany, Christian Baks, Daniel M. Kuchta, Clint L. Schow, and Frank Libsch – IBM Corporation

2. 8:25 a.m. - Blue and White Light Emitting High Power Density LED ModulesMarc Schneider, Benjamin Leyrer, Bernhard Osswald, Christian Herbold, Franziska Herrmann, Kirsten Eilert, and Juergen Brandner – Karlsruhe Institute of Technology; Jin-Kai Chang, Yi-Chung Huang, and Wood-Hi Cheng – National Sun Yat-sen University

3. 8:50 a.m. - All Solid-State Multi-Chip Multi-Channel WDM Photonic ModuleIvan Shubin, Xuezhe Zheng, Hiren Thacker, Stevan Djordjevich, Shiyun Lin, Philip Amberg, Jon Lexau, Kannan Raj, John Cunningham, and Ashok Krishnamoorthy – Oracle

4. 10:00 a.m. - Silicon Photonics Packaging for Highly Scalable Optical InterconnectsAntonio La Porta, Jonas Weiss, Roger Dangel, Daniel Jubin, Norbert Meier, Jens Hofrichter, Charles Caer, Folkert Horst, and Bert Jan Offrein – IBM Corporation

5. 10:25 a.m. - 125-µm-pitch × 12-channel “Optical Pin” Array as I/O Structure for Novel Miniaturized Optical Transceiver ChipsToshinori Uemura, Akio Ukita, Koichi Takemura, Mitsuru Kurihara, Daisuke Okamoto, Jun Ushida, Kenichiro Yashiki, and Kazuhiko Kurata – Photonics Electronics Technology Research Association

6. 10:50 a.m. - Analysis of New Direct on PCB Board Attached High Power Flip-Chip LEDs Gordon Elger, Maximilian Schmid, and Alexander Hanß – Technische Hochschule ingolstadt; Markus Klein and Robert Derix – Philips Technologie GmbH

7. 11:15 a.m. - Optoelectronic Packaging on Flexible Substrates using Flip Chip-Based Optodic BondingYixiao Wang and Ludger Overmeyer – Leibniz Universität Hannover; Raimund Rother – Albert-Ludwigs-Universität Freiburg

Program Sessions: Friday, May 29, 8:00-11:40 a.m.

Refreshment Break: 9:15-10:00 a.m.

Session 28: Emerging Interconnects Session 29: Lead-Free Solder Joints Session 30: Silicon Photonics and Light Sources

23

Page 24: 65th ECTC Advance Program

Committee: Advanced PackagingRoom: Harbor Island 1

Session Co-Chairs:Joseph W. Soucy - Draper LaboratoryTel. [email protected]

Deborah S. Patterson - Patterson GroupTel. [email protected]

1. 1:30 p.m. - Thin Film Packaging Atmosphere Management by Solder Reflow Sealing Jean-Louis Pornin, Damien Saint-Patrice, Bruno Reig, and Stephane Fanget – CEA-LETI; Jeroen Bielen, Gudrun Henn, and Marcel Giesen – Epcos AG

2. 1:55 p.m. - Wafer-Level Packaging of Aluminum Nitride RF MEMS Filters Michael Henry, Travis Young, Andrew Hollowell, and Roy Olsson III – Sandia National Laboratories

3. 2:20 p.m. – Two-Die Wafer-Level Chip Scale Packaging (WL-CSP) Enables the Smallest TCXO for Mobile and Wearable ApplicationsNiveditha Arumugam, Ginel Hill, Guy Clark, Carl Arft, Charles Grosjean, Rajkumar Palwai, James Pedicord, Paul Hagelin, Aaron Partridge, Vinod Menon, and Pavan Gupta – SiTime Corporation

4. 3:30 p.m. - Application of TSV Integration and Wafer Bonding Technologies for Hermetic Wafer Level Packaging of MEMS Components for Miniaturized Timing DevicesKai Zoschke, Charles-Alix Manier, Martin Wilke, and Hermann Oppermann – Fraunhofer IZM; David Ruffieux – CSEM; James Dekker and Antti Jaakkola – VTT Technical Research Centre of Finland; Silvio Dalla Piazza – Micro Crystal AG; Giorgio Allegato – STMicroelectronics; Klaus-Dieter Lang – Technical University of Berlin

5. 3:55 p.m. - Design, Assembly and Reliability of a Hermetic Package for a 600°C Wireless Temperature Sensor Matthias Klein, Bert Wall, and Richard Gruenwald – Vectron International; Gudrun Bruckner – Carinthian Tech Research AG; Kunihiro Ueki – Kyocera Semiconductor Components Division

6. 4:20 p.m. - Thermomechanical Reliability of Gold Stud Bump Bonding for Large Volume MEMS DevicesMaaike M. Visser Taklo, Astrid-Sofie Vardøy, and Daniel Nilsen Wright – SINTEF; Alastair Attard, Zlatko Hajdarevic, and Stephan Bulacher – Besi Austria GmbH; Mario Saliba and Jan Wijgaerts – Henkel Corporation; Joshua Borg and David Oscar Vella – STMicroelectronics

7. 4:45 p.m. - Three-Dimensional Integration Technology for Sensor Application using 5µm Pitch Au Cone Bump ConnectionsMakoto Motoyoshi, Kohki Yanagimura, and Junnichi Takanohashi – Tohoku-MicroTec Co., Ltd.; Mariappan Murugesan and Mitsumasa Koyanagi – Tohoku University; Masahiro Aoyagi – Advanced Industrial Science and Technology

Committee: InterconnectionsRoom: Harbor Island 2

Session Co-Chairs:Gilles Poupon - CEA-LETITel. [email protected]

William Chen - Advanced Semiconductor Engineering, Inc.Tel. [email protected]

1. 1:30 p.m. - High Temperature Resistant Packaging for SiC Power Devices Using Interconnections Formed by Ni Micro-Electroplating and Ni Nano-ParticlesYasunori Tanaka, Keito Ota, Haruka Miyano, Yoshiaki Shigenaga, Tomonori Iizuka, and Kohei Tatsumi – Waseda University

2. 1:55 p.m. - Modeling, Design and Demonstration of Ultrashort and Ultrafine Pitch Metastable Cu-Sn Interconnections with High Throughput SLID AssemblyTingChia Huang, Vanessa Smet, P. Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Satomi Kawamoto – Namics Corporation

3. 2:20 p.m. - Development of Advanced Wire Bonding Technology for QFN Devices Hui Xu, Alireza Rezvani, Jon Brunner, John Foley, Ivy Qin, and Bob Chylak – Kulicke and Soffa Industries, Inc.

4. 3:30 p.m. - Evaluation of Ag Wire Reliability on Fine Pitch Wire BondingJiaqing Xi, Norbe Mendoza, Thomas Yang, Edward Reyes, Kevin Chen, and Steve Bezuk – Qualcomm Technologies, Inc.; Juln Lin, Shengqi Ke, and Eason Chen – Siliconware Precision Industries Co. Ltd.

5. 3:55 p.m. - Degradation of Cu-Al Wire Bonded Contacts under High Current and High Temperature Conditions Using In-Situ Resistance MonitoringRené Rongen, Arjan van IJzerloo, Amar Mavinkurve, and G. M. O’Halloran – NXP Semiconductors

6. 4:20 p.m. - Growth and Reactivity of Al-Cu Intermetallic Compounds under Ideal ConditionsBauer Robert, Yik Yee Tan, Heinrich Koerner, Juergen Walter, and Sergey Ananiev – Infineon Technologies

7. 4:45 p.m. - The Intermetallic Compound (IMC) Growth and Phase Identification of Different Kinds of Copper Wire and Al Pad ThicknessStuwart Fan and Louie Huang – Advanced Semiconductor Engineering, Inc.; Ming-Chi Ho and Ker-Chang Hsieh – National Sun Yat-Sen University

Committee: Assembly & Manufacturing Technology • Room: Harbor Island 3

Session Co-Chairs:Li Jiang - Texas InstrumentsTel. [email protected]

Vijay Khanna - IBM CorporationTel. [email protected]

1. 1:30 p.m. - Wafer-Level Wet Etching of High-Aspect-Ratio Through Silicon Vias (TSVs) with High Uniformity and Low Cost for Silicon Interposers with High Density Interconnect of 3D PackagingLiyi Li – Georgia Institute of Technology; Jiali Wu – Georgia Institute of

Technology; IBM Corporation; Ching-Ping Wong – Georgia Institute of

Technology; The Chinese University of Hong Kong

2. 1:55 p.m. - Simulation of Thermal Pulse Evolution During Laser Debonding Bucknell Webb and Paul Andry – IBM Corporation

3. 2:20 p.m. - Demonstration of a Novel Low Cost Single Material Temporary Bond Solution for High Topography Substrates Based on a Mechanical Wafer Debonding and Innovative Adhesive RemovalA. A. Phommahaxay, A. Jourdain, G. Verbinnen, S. Tan, A. Miller, and G.

Beyer – IMEC; A. Nakamura – Fujifilm Electronic Materials; Y. Kamochi, I.

Koyama, Y. Iwai, and M. Sawano – Fujifilm Corporation

4. 3:30 p.m. - Review of Wafer Dicing Techniques for Via-Middle Process 3DIC/TSV Ultrathin Silicon Device Wafers Andy Hooper, Jeff Ehorn, Mike Brand, and Cassie Bassett – Micron Technology, Inc.

5. 3:55 p.m. - Assembly Challenges in Developing 3DIC Package with Ultra High Yield and High ReliabilityRaghunandan Chaware, Ganesh Hariharan, Jeff Lin, Inderjit Singh, Glenn O’Rourke, Kenny Ng, and S. Y. Pai – Xilinx, Inc.; C. C. Li, Zill Huang, and S. K. Cheng – Taiwan Semiconductor Manufacturing Company

6. 4:20 p.m. - Metal Contamination Evaluation of a Reveal Process Using Direct Si/Cu Grinding and Residual Metal Reduction Naoya Watanabe and Masahiro Aoyagi – Advanced Industrial Science and Technology; Daisuke Katagawa – Apprecia Technology Inc.; Tsubasa Bandoh, Takahiko Mitsui, and Eiichi Yamamoto – Okamoto Machine Tool Works, Ltd.

7. 4:45 p.m. - Plasma Activated Chip-to-Wafer Direct Bonding Technology for Self-Assembly Based 3D IntegrationHideto Hashiguchi, H. Yonekura,Takafumi Fukushima, Mariappan Murugesan, Hisashi Kino, Kang-Wook Lee, Tetsu Tanaka, and Mitsumasa Koyanagi – Tohoku University

Program Sessions: Friday, May 29, 1:30-5:10 p.m.

Refreshment Break: 2:45-3:30 p.m.

24

Session 31: MEMS and Sensors Session 32: Packaging for Power and Wirebond Innovations

Session 33: 3D Technology: Latest Innovations

Page 25: 65th ECTC Advance Program

Committee: Materials & ProcessingRoom: Nautilus 1 & 2

Session Co-Chairs:Mikel Miller - Draper LaboratoryTel. [email protected]

Ivan Shubin - OracleTel. [email protected]

1. 1:30 p.m. - Novel WO3 Nanoparticles Modified Electroless Metallization to Retard Interfacial Reaction and Reinforce the Reliability of Solder InterconnectionXiao Hu and Y. C. Chan – City University of Hong Kong

2. 1:55 p.m. - Development of Interconnection Materials for Bi2Te3 and PbTe Thermoelectric Module by Using SLID TechniqueC. C. Li, Z. X. Zhu, H. W. Yang, J. H. Ke, and C. R. Kao – National Taiwan University; S. J. Hsu and C. C. Lee – University of California, Irvine; L. L. Liao, M. J. Dai, and C. K. Liu – Industrial Technology Research Institute; G. J. Snyder – California Institute of Technology

3. 2:20 p.m. - Effects of Film Viscosity on Electric Field-Induced Alignment of Graphene Flakes in B-Stage Graphene-Epoxy Composite FilmsSeung Yoon Jung and Kyung-Wook Paik – KAIST

4. 3:30 p.m. - Solution-Processed Solid-State Micro-Supercapacitors for On-Chip Energy Storage DevicesBo Song, Liyi Li, Zhenkun Wu, and Kyoung-sik Moon – Georgia Institute of Technology; Jiali Wu – IBM Corporation; Ching-Ping Wong – Georgia Institute of Technology; The Chinese University of Hong Kong

5. 3:55 p.m. - Demonstration of 2µm RDL Wiring Using Dry Film Photoresists and 5µm RDL Via by Projection Lithography for Low-Cost 2.5D Panel-Based Glass and Organic Interposers Ryuta Furuya – Ushio Inc.; Hao Lu, Fuhan Liu, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Hai Deng and Tomoyuki Ando – TOK Corporation

6. 4:20 p.m. - Fabrication of Ultra-Fine Vias in Low CTE Build-Up Films Using a Novel Dry Etching TechnologyYasuhiro Morikawa, Muneyuki Sato, Yosuke Sakao, Tetsushi Fujinaga, Noriaki Tani, and Kazuya Saito – ULVAC, Inc.

7. 4:45 p.m. - Vacuum Ultraviolet (VUV) and Vapor – Combined Surface Modification for Hybrid Bonding of SiC, GaN, and Si Substrates at Low Temperature and Atmospheric PressureAkitsu Shigetou – National Institute for Materials Science (NIMS); Jun Mizuno and Shuichi Shoji – Waseda University

Committee: Modeling & SimulationRoom: Nautilus 3 & 4

Session Co-Chairs:Pradeep Lall - Auburn UniversityTel. [email protected]

Yong Liu - Fairchild Semiconductor CorporationTel. [email protected]

1. 1:30 p.m. - Silicon Interposer Warpage Estimation Model for 2.5D IC Packaging Utilizing Passivation Film Composition and Stress TuningCheng-Hsiang Liu, Yuan-Hong Liao, Wan-Ting Chen, Chang-Lun Lu, and Shih-Ching Chen – Siliconware Precision Industries Co., Ltd.

2. 1:55 p.m. - A Systematic Exploration of the Delamination Mechanisms in Underfilled Flip-Chip PackagesTuhin Sinha, Taryn J. Davis, Thomas E. Lombardi, and Jeffrey T. Coffin – IBM Corporation

3. 2:20 p.m. - Optimization of Assembly Process of IGBT Module and Heatsink Based on Sequent Process Analysis MethodYang Zhou, Ling Xu, and Miaocao Wang – Huazhong University of Science & Technology

4. 3:30 p.m. - Accelerated Determination of Interfacial Fracture Toughness in Microelectronic Packages under Cyclic LoadingEmad A. Poshtan – Robert Bosch GmbH; Fraunhofer Institute ENAS; Chemnitz University of Technology; Sven Rzepka – Fraunhofer Institute ENAS; Christian Silber - Robert Bosch GmbH; Bernhard Wunderle – Chemnitz University of Technology

5. 3:55 p.m. - Effect of Temperature and Moisture Degradation on Cohesive Zone Models to Study Copper Leadframe/Mold Compound Interfacial Degradation Abhishek Kwatra, David Samet, and Suresh Sitaraman – Georgia Institute of Technology

6. 4:20 p.m. - Relative and Absolute Warpage Modeling on Molded PackagesJiantao Zheng, Eric Zhou, Manuel Aldrete, Rajneesh Kumar, Lejun Wang, and Ahmer Syed – Qualcomm Technologies, Inc.

7. 4:45 p.m. - Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design Yuci Shen and Xuejun Fan – Lamar University; Leilei Zhang – NVIDIA Corporation

Committee: Applied ReliabilityRoom: Nautilus 5

Session Co-Chairs:Darvin R. Edwards - Edwards EnterprisesTel. [email protected]

Deepak Goyal - Intel CorporationTel. [email protected]

1. 1:30 p.m. - Challenges for the Prediction of Solder Joint Life in Long Term VibrationPeter Borgesen, Luke Wentlent, Sa’D Hamasha, Younis Jaradat, and Farhan Batieha – Binghamton University; Awni Qasaimeh – Tennessee Technology University

2. 1:55 p.m. - Effect of Elevated Testing Temperature on Sn-Ag-Cu Interconnect High and Low G Board Level Mechanical Shock PerformanceTae-Kyu Lee, Weidong Xie, and Cherif Guirguis – Cisco Systems, Inc.

3. 2:20 p.m. - First Demonstration of Drop-Test Reliability of Ultra-Thin Glass BGA Packages Directly-Assembled on Boards for Smart Mobile ApplicationsBhupender Singh, Vanessa Smet, Gary Menezes, Venky Sundaram, Pulugurtha Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Jae Sik Lee, Brian Roggeman, Urmi Ray, and Riko Radojcic – Qualcomm Technologies, Inc.

4. 3:30 p.m. - Nanomechanical Characterization of SAC Solder Joints - Reduction of Aging Effects Using Microalloy AdditionsJeffrey Suhling, Md Hasnine, Barton Prorok, Michael Bozack, and Pradeep Lall – Auburn University

5. 3:55 p.m. - Effect of High Temperature Bake on Evolution of Interfacial Structure in Cu Wire Bonds and Its Impact on Cu/Al Interfacial CorrosionKejun Zeng and Amit Nangia – Texas Instruments, Inc.

6. 4:20 p.m. - Experimental and Numerical Investigations on Cu/Low-k Interconnect Reliability During Copper Pillar Shear TestClément Sart – STMicroelectronics; Institut Supérieur de Mécanique de Paris; École Centrale Paris; Sébastien Gallois-Garreignot, Vincent Fiori, Olivier Kermarrec, Caroline Moutin, Clément Tavernier, and Hervé Jaouen – STMicroelectronics

7. 4:45 p.m. - Investigation of WLCSP Corrosion Induced Reliability Failure on Halogens Environment for Wearable ElectronicsJung-Hsuan Chen, Yian-Liang Kuo, Pei-Haw Tsao, Jerry Tseng, Megan Chen, Mayetta Chen, Y. T. Lin, and Antai Xu – Taiwan Semiconductor Manufacturing Company

Program Sessions: Friday, May 29, 1:30-5:10 p.m.

Refreshment Break: 2:45-3:30 p.m.

Session 34: Novel Materials and Processes

Session 35: Package Warpage, Delamination, and Thermal Modeling

Session 36: Static and Dynamic Interconnect Reliability

25

Page 26: 65th ECTC Advance Program

Wednesday, May 27Session 37: Interactive Presentations 19:00 a.m. - 11:00 a.m.

Committee: Interactive Presentations

Session Co-Chairs:Nam Pham - IBM CorporationTel. [email protected]

Mark Eblen - Kyocera America, Inc.Tel. [email protected]

HOTROD (Flip Chip QFN) Non-Wets Resolution for PackagesFloro III Camenforte and James Baello – Texas Instruments, Inc.

20”x20” Panel Size Glass Substrate Manufacturing for 2.5D SiP ApplicationYu-Hua Chen – Unimicron Technology Corp.

Low Temperature Solid-State-Diffusion Bonding for Fine-Pitch Cu/Sn/Cu InterconnectJian Cai, Qian Wang, and Ziyu Liu – Tsinghua University; Junqiang Wang and Dejun Wang – Dalian University of Technology; Sun-Kyoung Seo and Tae-Je Cho – Samsung Advanced Institute of Science and Technology

Failure Mechanisms and Color Stability in Light-Emitting Diodes During Operation in High-Temperature Environments in Presence of ContaminationPradeep Lall and Hao Zhang – Auburn University; Lynn Davis – RTI International

Development of a Robust 2-D Thermal Wind Sensor using Glass Reflow Process for Low Power ApplicationsYan-Qing Zhu, Bei Chen, Ming Qin, Qing-An Huang, and Jian-Qiu Huang – Southeast University

Improved Connectorization of Compliant Polymer Waveguide Ribbons for Silicon Nanophotonics Chip Interfacing to Optical FibersYoichi Taira, Hidetoshi Numata, and Tymon Barwicz – IBM Corporation; Shotaro Takenobu – Asahi Glass

3D Heterogeneous Integration Structure Based on 40 nm and 0.18 µm Technology Nodes Yu-Chen Hu, Yu-Sheng Hsieh, and Kuan-Neng Chen – National Chiao Tung University; Anthony J. Gallegos, Wei-Chia Chen, and Terry Souza – Technic, Inc.

Ultra-Thin Glass Wafer Lamination and Laser De-Bonding to Enable Glass Interposer FabricationWen-Wei Shen and Cheng-Ta Ko – Industrial Technology Research Institute; National Chiao Tung University; Hsiang-Hung Chang and Wei-Chung Lo – Industrial Technology Research Institute; Leon Tsai and Aric Shorey – Corning Inc.; Alvin Lee, Jay Su, Baron Huang, and Dongshun Bai – Brewer Science, Inc.

Cooling Hot Spots by Hexagonal Boron Nitride Heat SpreadersShuangxi Sun – Chalmers University of Technology; Jie Bao – Shanghai University; Wei Mu, Yong Zhang, and Johan Liu – Chalmers University of Technology; Shanghai University; Yifeng Fu and Lilei Ye – Smart High Tech AB

Fan-Out Technologies for WiFi SiP Module Packaging and Electrical Performance SimulationChueh An Hsieh, Chung Hsuan Tsai, Huan Wun Lee, Tony Y. C. Lee, and Harrison Chang – Advanced Semiconductor Engineering, Inc.

Assembly and Integration of Optical Sensors Based on Quantum Dots-in-Well in Double-Barrier Photodetector ArrayW. Wang, H. D. Lu, and F.M. Guo – East China Normal University

A Micro Hemispherical Glass Shell Resonator for Online Liquid Density Sensing of MicrofluidicsYuzhen Zhang, Jintang Shang, and Bin Luo – Key Lab of MEMS of Education Ministry, Southeast University

Thermally Enhanced FOWLP - Development of a Power-eWLB DemonstratorAndré Cardoso, Mariana Pires, and Raquel Pinto – NANIUM S.A.; Gusztáv Hantos – Budapest University of Technology and Economics

Development of FOWLP with Mechanical ProtectionJosé Campos, Eoin O’Toole, Raquel Pinto, and Paula Gomes – NANIUM, S.A.

An Effective Method for Full Solder Intermetallic Compound Formation and Kirkendall Void Control in Sn-Base Solder Micro-JointsHongqing Zhang, Eric Perfecto, Victoria Calero-DdelC, and Frank Pompeo – IBM Corporation

Characteristics and Process Stability of Complete Electrical Interconnect Structures of a Low Cost Interposer TechnologyMichael Dittrich, Alexander Steinhardt, and Andy Heinig – Fraunhofer EAS; Maciej Wojnowski and Klaus Pressel – Infineon Technologies

Wafer Edge Defect Study of Temporary Bonded Thin WafersSumant Sood, Rohit Bhat, Heiko Eisenbach, Marc Filzen, and Prashant Aji – KLA-Tencor; Thomas Uhrmann, Julian Bravin, Jürgen Burggraf, Markus Wimplinger, and Paul Lindner – EV Group

Development of High Yield, Reliable Fine Pitch Flip Chip Interconnects with Copper Pillar Bumps and Thin Coreless SubstrateWeidong Liu, Guofeng Xia, Tiansheng Liang, Taotao Li, Xiaolong Wang, Jianyou Xie, Shiguang Chen, and Daquan Yu – HuaTian Technology Co. Ltd.

Investigation of Thermo-Mechanical Stresses and Reliability of 3D Die-Stack Structures by Synchrotron X-Ray Micro-DiffractionTengfei Jiang, Chenglin Wu, Jay Im, Rui Huang, and Paul Ho – University of Texas, Austin; Peng Su – Cisco Systems, Inc.; Patrick Kim – Micron Technology, Inc; Cassie Bassett, Kevin Sichak, Jaspreet Gandhi, and Jian Li – Micron Technology, Inc.

Organic Multi-Chip Module for High Performance SystemsLei Shan, Young Kwark, Christian Baks, Michael Gaynes, and Timothy Chainer – IBM Corporation; Hajime Saiki, Atsushi Kuhara, Gil Aguiar, Noritaka Ban, and Yoshiki Nukaya – NTK Technologies

Formulation of Underfill Materials for Simultaneous Underfilling and Stack BondingChia-Chi Tuan, Kyoung-Sik Moon, and Ching-Ping Wong – Georgia Institute of Technology

Advances in Embedded Traces for 1.5µm RDL on 2.5D Glass InterposersFuhan Liu, Chandrasekharan Nair, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology

Thermal Modeling and Experimental Study of 3D Stack Package with Hot Spot ConsiderationNaoaki Nakamura, Yoshihisa Iwakiri, and Hiroshi Onuki – Fujitsu Advanced Technologies Ltd.; Shunichi Kikuchi – Fujitsu

Ltd.

Wednesday, May 27Session 38: Interactive Presentations 22:00 p.m. - 4:00 p.m.

Committee: Interactive Presentations

Session Co-Chairs:Patrick Thompson - Texas Instruments, Inc.Tel. [email protected]

Michael Mayer - University of WaterlooTel. [email protected]

Highly Flexible Transparent Conductors Based on 2D Silver Nanowire Networks Xinning Ho, Junie Tey, Chek Kweng Cheng, and Jun Wei – Singapore Institute of Manufacturing Technology

Study of New Alloy Composition of Solder Balls – Identifying Material Properties as Key Leading Indicators Toward Improved Board Level PerformanceRey Alvarado, Beth Keser, Steve Bezuk, Mark Schwarz, and Eric Zhou – Qualcomm Technologies, Inc.; Henry Wang and Kok-Lin Heng – Accurus Scientific Co.

Superior Thermal Conductivity of Carbon Nanoscroll-Based Thermal Interface MaterialsYu Wang and Yingyan Zhang – University of Western Sydney

Designing for the Internet of Things: A Paradigm Shift in ReliabilityMudasir Ahmad – Cisco Systems, Inc.

Micromachined Cavity-Based Bandpass Filter and Suspended Planar Slow-Wave Structure for Vacuum-Microelectronic Millimeter-Wave/THz Microsystem Embedded in LTCC Packaging SubstratesMin Miao – Beijing Information Science & Technology University; Yufeng Jin – Peking University

Low Temperature Die Attach Based on Submicrometer Ag Particles and the High Temperature Reliability of Sintered Joints Hao Zhang, Shunsuke Koga, Jinting Jiu, Shijo Nagao, Yasuha Izumi, Emi Yokoi, and Katsuaki Suganuma – Osaka University

Rapid Formation of Full Cu-In Intermetallic Compound (IMC) Joints Under Electric CurrentBaolei Liu, Yanhong Tian, Yang Liu, and Chenxi Wang – Harbin Institute of Technology

Influence of UBM Metallurgy on Sn Textures and EM Failure and Voids FormationHongqing Zhang and Minhua Lu – IBM Corporation

The Technology of Au-Au Bonding in the CoF Package of Ultra-Thin ChipZhangqi Hu, Jian Cai, Qian Wang, Chuan Chen, and Han Guo – Tsinghua University; C. Q. Cui, Jian Wang, and Fengwei Wang – AKM Electronics Technology (Suzhou) Company Ltd.

Development and Application of a Micro-Infrared Photoelasticity System for Stress Evaluation of Through-Silicon Vias (TSV) Fei Su, Tianbao Lan, and Xiaoxu Pan – Beijing University of Aeronautics and Astronautics

Achieving Low-Porosity Sintering of Nano Ag Paste via Pressureless ProcessNing-Cheng Lee, Sihai Chen, Guangyu Fan, Xue Yan, Chris LaBarbera, and Lee Kresge – Indium Corporation

Three Dimensional Graphene-Based Composite for Flexible and Stretchable Electronic Applications Bo Song, Zhenkun Wu, Yuntong Zhu, Kyoung-sik Moon, and Ching-Ping Wong – Georgia Institute of Technology

Interactive Presentations: Wednesday, May 27, 9:00 - 11:00 a.m. and 2:00 - 4:00 p.m.

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Through Silicon Via Process for Effective Multi-Wafer IntegrationAkihiro Horibe, Kuniaki Sueoka, Toyohiro Aoki, Kazushige Toriyama, Hiroyuki Mori, and Yasumitsu Orii – IBM Corporation

Advanced Multi-Sites Testing Methodology after Wafer Singulation for WLPs ProcessSean Yang, Ben Tsai, C. C. Lin, Eric Yen, J. K. Lee, Wayne Hsieh, and Vans Wu – Advanced Semiconductor Engineering, Inc.

Reliability Improvement of Solder Anisotropic Conductive Film (ACF) Joints By Controlling ACF Polymer Resin Properties Yoo-Sun Kim, Seung-Ho Kim, Jiwon Shin, and Kyung-Wook Paik – KAIST

Optimization and Challenges of Backside Via Flatness Reveal ProcessKang Wei Peng, Cheng Hao Ciou, Ching Wen Chiang, Chung Chih Yen, Wei Jen Chang, Ching Yu Huang, Kuang Hsin Chen, Teny Shih, Hsien Wen Chen, and Shih Ching Chen – Siliconware Precision Industries Co., Ltd.

Wafer Level Fabrication of a Glass-Embedded High-Aspect-Ratio Passive Components Using a Glass Reflow ProcessMengyin Ma, Jintang Shang, and Bin Luo – Key Lab of MEMS of Education Ministry, Southeast University

Unit Antenna Based Wireless Power Transfer Systems Nurcan Keskin and Huaping Liu – Oregon State University

Performance Analysis of Single- and Multi-Walled Carbon Nanotube Based Through Silicon ViasArsalan Alam, Manoj Kumar Majumder, Archana Kumari, Ramesh Kumar Vobulapuram, and Brajesh Kumar Kaushik – Indian Institute of Technology, Roorkee

Thermal Stress Destruction Analysis in Low-k Layer by Via-Last TSV Structure Hideki Kitada – Fujitsu Ltd.

Low Stress Bonding for Large Size Die ApplicationKei Murayama, Mitsuhiro Aizawa, and Takashi Kurihara – Shinko Electric Industries Company, Ltd.

Growth Kinetics of Cu3Sn in Intermetallics Joints during Isothermal Annealing Process Liping Mo and Changqing Liu – Loughborough University; Fengshun Wu and Weisheng Xia – Huazhong University of Science and Technology

Modeling, Design and Demonstration of Low-Temperature, Low-Pressure and High-Throughput Thermocompression Bonding of Copper Interconnections without SoldersNinad Shahane, Vanessa Smet, Venky Sundaram, Pulugurtha Markondeya Raj, and Rao Tummala – Georgia Institute of Technology; Gustavo Ramos, Arnd Kilian, and Robin Taylor – Atotech Deutschland GmbH

Dependency of the Porosity and the Layer Thickness on the Reliability of Ag Sintered Joints during Active Power Cycling Constanze Weber, Matthias Hutter, and Stefan Schmitz – Fraunhofer IZM; Klaus-Dieter Lang – Technical University Berlin

A Physiological Sound Sensing System Using Accelerometer Based on Flip-Chip Piezoelectric Technology and Asymmetrically Gapped CantileverChaojun Liu – Huazhong University of Science & Technology; Yong Xu – Wayne State University; Yating Hu – Middle Tennessee State University; Sheng Liu – Wuhan University

Organic Gate Insulator Materials for Amorphous Metal Oxide TFTsWilliam Sheets, Su Jin Kang, Hsing-Hung Hsieh, Zhihua Chen, Shaofeng Lu, Xiang Yu, Yu Xia, D. Scott Bull, and Antonio

Facchetti – Polyera Corporation

Thursday, May 28Session 39: Interactive Presentations 39:00 a.m. - 11:00 a.m.

Committee: Interactive PresentationsSession Co-Chairs:John Hunt - ASE US Inc.Tel. +1 [email protected]

Rao Bonda - Amkor TechnologyTel. [email protected]

An Improved Peel Stress-Based Correlation to Predict Solder Joint Reliability of Lidded Flip Chip Ball Grid Array PackagesGuangxu Li and Siva Gurrum – Texas Instruments, Inc.

Impact of Uneven Solder Thickness on IGBT Substrate Solder Joint ReliabilityHua Lu and Chris Bailey – University of Greenwich; Liam Mills – Semelab Ltd.

The Equivalent Acceleration Assessment of JEDEC Moisture Sensitivity Levels Using PeridynamicsSungwon Han, Seyoung Lim, Yuchul Hwang, Jangyong Bae, and Sungsoo Lee – Samsung Electronics Company, Ltd.; Erkan Oterkus and Cagan Diyaroglu – University of Strathclyde; Erdogan Madenci and Selda Oterkus – University of Arizona

Simulation Driven Design of Novel Integrated Circuits - Part 2: Constitutive Material Modeling of ThermosetsPrzemyslaw Gromala, Berkan Oeztuerk, and Balaji Muthuraman – Robert Bosch GmbH; Kaspar Jansen and Leo Ernst – Delft University of Technology

A Hybrid Approach to Characterize Adhesion Strength of Interfaces in an Organic SubstrateBharat Penmecha, Reda Alazar, Dilan Seneviratne, Pilin Liu, and Pramod Malatkar – Intel Corporation

New Final Finish Stack Including a Custom Nanocrystalline Ag Alloy for Mobile Connector Systems with High Cycling Wear and Powered Environmental Exposure RequirementsKathy Bui and Trevor Goodrich – Xtalic Corporation

Assessment of Dielectric Encapsulation for High Temperature High Voltage ModulesRabih Khazaka – CEA-LETI

Molecular Dynamics Simulations of Thermal Conductivity in Composites Consisting of Aluminum Oxide Nanoparticles Surrounded by Polyethylene OxideBarbara Poliks, Cheng Chen, Bruce White, and Bahgat Sammakia – Binghamton University

A Fracture Mechanics Based Parametric Study of the Cu-Cu Direct Thermo-Compression Bonded Interface Using 2D and 3D Finite Element Method Ah-Young Park and Seung Bae Park – Binghamton University; Satish Chaparala – Corning, Inc.

Effective Coefficient of Thermal Expansion (CTE) of Bilayer/Trilayer in Semiconductor Package SubstratePeng Chen, Prasanna Raghavan, Kyle Yazzie, and Huiyang Fei – Intel Corporation

Study of Cracking of Thin Glass Interposers Intended for Microelectronic Packaging SubstratesScott McCann, Venkatesh Sundaram, Rao Tummala, and Suresh Sitaraman – Georgia Institute of Technology

Noise Coupling Emulation between TSV and Active Circuit through Metal Oxide PatchManho Lee, Jonghyun Cho, Jaemin Lim, and Joungho Kim – KAIST

The Use of Temporary Bonding in Manufacturing Flexible and Rigid SubstratesJohn Moore, Jared Pettit, Alman Law, and Alex Brewer – Daetec LLC

Modeling, Design and Demonstration of Trench-Based Electromagnetic Shielding in Miniaturized RF Glass PackagesSrikrishna Sitaraman, Junki Min, Markondeya Raj Pulugurtha, Min Suk Kim, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology

Effect of Functionalized Multiwalled Carbon Nanotubes on the Coefficient of Thermal Expansion of Bismaleimide-Triazine Resins (BT Resins)Xiaoliang Zeng, Shuhui Yu, and Rong Sun – Chinese Academy of Sciences; Jianbin Xu and Ching-Ping Wong – The Chinese University of Hong Kong

Wear Resistance of Laser-Sintered Gold-Composite Film for Electrical-Contacts by Using Ni/CNT Dispersed PasteMitsugu Yamaguchi, Kazuhiko Yamasaki, and Katsuhiro Maekawa – Ibaraki University; Shinji Araga – Ibaraki Giken Ltd.; Mamoru Mita – M&M Research Laboratory

Fabricating Polymer Insulation Layer by Spin-Coating for Through Silicon ViasGuoping Zhang – Shenzhen Institutes of Advanced Technology

Fundamental Investigation of Lid Interactions with TIM1 and Adhesive Materials for Advanced Flip Chip PackagingLyndon Larson, Yin Tang, Adriana Zambova, Cassie Hale, and Dave Plante – Dow Corning; Sushumna Iruvanti, Taryn Davis, Richard Langois, Elaine Cyr, and Hai Longworth – IBM Corporation

A Feasible Method to Predict Thin Package Actual Warpage Based on FEM Model Integrated with Empirical Data Wei Lin – Amkor Technology, Inc.

Empirical Investigations on Die Edge Defects Reductions in Die Singulation Processes for Glass-Panel Based Interposers for Advanced PackagingFrank Wei – Disco Corporation; Venky Sundaram, Scott McCann, Vanessa Smet, and Rao Tummala –Georgia Institute of Technology

Thursday, May 28Session 40: Interactive Presentations 42:00 p.m. - 4:00 p.m.

Committee: Interactive PresentationsSession Co-Chairs:Nancy Stoffel - GE Global ResearchTel. [email protected]

Mark Poliks - i3 Electronics, Inc. Tel. [email protected]

Metamaterial Periodic Structure Used for Microfluidic SensingJennifer Byford, Kyoung Park, and Premjeet Chahal – Michigan State University

Optical Waveguide Crosstalk SPICE Modeling for Package System Signal Integrity SimulationZhaoqing Chen – IBM Corporation

The Design of Quasi-Optical Terahertz Components Using Evolutionary AlgorithmsJoshua Myers, Jennifer Byford, and Premjeet Chahal – Michigan State University

Design for Reliability with a New Chip to Package Interaction Modeling MethodologyShiguo (Richard) Rao – Vitesse Semiconductor Corp.; Dongkai Shangguan – National Center for Advanced Packaging; Xiaopeng Xu, Lin Li, Bei Deng, and Ricardo Borges – Synopsys Inc.

The Dynamics of Warpage for Thinned Si Wafer after Wafer Level PackagingChunsheng Zhu, Heng Lee, Jiaotuo Ye, Gaowei Xu, and Le Luo – Chinese Academy of Sciences

Wideband 40GHz TSV Modeling Analysis under High Speed on Double Side Probing MethodologyChiu Hsiang Wang, Jui Chiu Huang, Yuan Hung Lin, Kwan Chin Fan, and Hsin Hung Lee – Siliconware Precision Industries Co., Ltd.

On the Failure Mechanism in Lead-Free Flip-Chip Interconnects Comprising ENIG Finish during ElectromigrationMarek Gorywoda – Hochschule Hof; Rainer Dohle, Andreas Wirth, Bernd Burger, and Joerg Gossler – Micro Systems Engineering GmbH

Interactive Presentations: Wednesday, May 27, 2:00 - 4:00 p.m. and Thursday, May 28, 9:00 - 11:00 a.m.

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Electromigration and Thermal Migration in Pb-Free InterconnectsMinhua Lu, Thomas Wassick, Gerald Advocate, and Ben Backes – IBM Corporation

Principal Components Regression Model for Prediction of Life-Reduction in SAC Leadfree Interconnects During Long-Term High Temperature StoragePradeep Lall, Sree Mitun Duraisamy, Jeff Suhling, and John Evans – Auburn University

Effects of Board Design on Failure Mechanisms of PCB/BGA Assemblies under Drop ImpactGrace Lolita Tsebo Simo and Hossein Shirangi – Robert Bosch GmbH; Mathias Nowottnick – University of Rostock; Sven Rzepka – Fraunhofer ENAS

Payload Power Amplifier with Average Power Tracking in Ka-Band Satellite DownlinkSeong-Mo Moon, Dong-Hwan Shin, and In-Bok Yom – ETRI; Moon-Que Lee – University of Seoul

A Prognostic Method to Assess Solder Joint Reliability Based on Digital Signal CharacterizationJeongAh Yoon, Insun Shin, Juyoung Park, and Daeil Kwon – UNIST

Dual-Frequency Antennas Embedded into the Floor for Efficient RF “Energy Evaporation”Chiara Mariotti, Marco Virili, and Luca Roselli – University of Perugia; Ricardo Gonçalves and Nuno B. Carvalho – University of Aveiro; Pedro Pinho – University of Lisbon

Affordable Terahertz Components Using 3D Printed TechnologyAmanpreet Kaur, Joshua Myers, Jennifer Byford, and Premjeet Chahal – Michigan State University

Design, Manufacture, and Reliability Assessment of Thermally Compression Bonded Bump-on-Trace Fine Pitch Copper Pillar Organic HDI PackageSwapan Bhattacharya, Brian Lewis, Han Wu, Kelley Hodge, Fei Xie, Paul Houston, and Daniel Baldwin – Engent, Inc.; Guy Burgess and Ted Tessier – FlipChip International

High Density Small Form Factor 3D Die Stack SiP (System in Package) with Ag Film over Wire (FOW) Technology on BGA/LGA Substrate with Conformal Shield (CS) for Internet of Things (IoT) ApplicationJemmy Sutanto, Mike DeVita, Ted Adlam, Bob Bancod, and Robert Lanzone – Amkor Technology, Inc.

Scanning Acoustic Microscopy and Shear Wave Imaging Mode Performances for Failure Detection in High-Density Microassembling TechnologiesLaurent Bechou, Zahia Remili, Yves Ousten, and Bruno Levrier – IMS Laboratory; Ephraim Suhir – Portland State University

Investigation of High Frequency Characteristics of Ag-Based WirebondsLih-Tyng Hwang and Ian Feng – National Sun Yat-Sen University; Brian Chou – Precision Packaging Materials Corp

Side Impact Reliability of SMT Micro-SwitchesJingshi Meng and Abhijit Dasgupta – University of Maryland

Crosstalk Challenge and Mitigation through Strategic Pin Placement for 25Gbps and BeyondShen Dong, Hong Shi, Suresh Ramalingam, and Nanju Na – Xilinx, Inc.

Design and Performance of a Flexible Metal Mountable UHF RFID Tag Navjot Kaur, Diana Segura Velandia, William Whittow, Paul P. Conway, and Andrew A. West – Loughborough University; Dave Barwick, Ehidiamen Iredia, Neil Parker, and Neil Porter – The Centre for Process Innovation (CPI)

Effect of Ball Bond Geometry on Bond Strength and Process Parameters in Wire Bonding Using Accelerated Optimization MethodJimy Gomes and Michael Mayer – University of Waterloo

A Do-It-Yourself FemtoduinoJack Ou, Alberto Maldonado, and Aram Yegiazaryan – Sonoma State University

Characterization of Electrical Properties of Glass and Transmission Lines on Glass Up to 50 GHzWasif Khan, Jialing Tong, Srikrishna Sitaraman, Venky Sundaram, Rao Tummala, and John Papapolymerou – Georgia Institute of Technology

Wafer Level High Temperature Reliability Study by Backside Probing for a 50µm Thin TSV Wafer C. S. Premachandran, Rakesh Ranjan, Rahul Agarwal, Yap Sing Fui, Sarasvathi Thangaraju, Arfa Gondal, Patrick Justison, and Natarajan Mahadeva Iyer – GLOBALFOUNDRIES

Friday, May 29Session 41: Student Interactive Presentations8:30 a.m. - 10:30 a.m.

Committee: Interactive PresentationsSession Co-Chairs:Ibrahim Guven - Virginia Commonwealth UniversityTel. [email protected]

Michael Mayer - University of WaterlooTel. [email protected]

A Low-Cost Fabrication Route for Silicon Microchannels and Microgratings with Flow-Enabled Polymer Self-Assembly Patterning and Wet Etching Liyi Li, Bo Li, and Zhiqun Lin – Georgia Institute of Technology

Atomic Flux Divergence Based AC Electromigration Model for Signal Line Reliability AssessmentZhong Guan and Malgorzata Marek-Sadowska – University of California, Santa Barbara

The Influence of High Melting Point Elements on the Reliability of Solder during Thermal ShockYing Zhong and Chunqing Wang – Harbin Institute of Technology; Xiujuan Zhao and J. F. J. M. Caers – Philips Applied Technologies

Die-Attachment Technologies for High-Temperature Applications of Si and SiC-Based Power DevicesAdeel Ahmad Bajwa, Eike Möller, and Jürgen Wilde – University of Freiburg

On the Design of High Performance Spiral Inductors for Communication System in a Package (CSIP)Dogukan Yildirim and Guann-Pyng Li – University of California, Irvine

Design and Fabrication of Suspended Low-Insertion-Loss Filters by Wafer Level Packaging TechnologyTao Zheng, Mei Han, Gaowei Xu, and Le Luo – Chinese Academy of Sciences

Realization of Wet Etching Based TSV with 4-Wiring Interconnections and Its Reliability EvaluationJiaotuo Ye, Xiao Chen, and Chunsheng Zhu – Chinese Academy of Sciences; Gaowei Xu and Le Luo – Shanghai Institute of Microsystem and Information Technology

Anti-Tarnishing Evaluations of Silver Solid Solution Phase with IndiumYongjun Huo and Chin C. Lee – University of California, Irvine

Modeling, Design, and Demonstration of 2.5D Glass Interposers with 16x28 Gbps Signaling Brett Sawyer, Bruce C. Chou, Saumya Gandhi, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Jack Mateosky – Ciena Corporation

Void Formation in Cu-Sn Micro-ConnectsGlenn Ross, Vesa Vuorinen, and Mervi Paulasto-Kröckel – Aalto University

Room Temperature Desorption of Self Assembled Monolayer from Copper Surface and Low Temperature Thermocompression BondingTamal Ghosh, Killi Krushnamurthy, Ch. Subrahmanyam, Vanjari Sivaramakrishna, Ashudeb Dutta, and Shiv Govind Singh – Indian Institute of Technology, Hyderabad

Low Temperature, Low Pressure CMOS Compatible Cu-Cu Thermo-Compression Bonding with Ti Passivation for 3D IC IntegrationAsisa Kumar Panigrahi, Satish Bonam, Tamal Ghosh, Vanjari Sivaramakrishna, and Shiv Govind Singh – Indian Institute of Technology, Hyderabad

A Compact Integrated Frequency Configurable Filter on PCBYu Guo – Nanjing University; Huai Gao – Suzhou Innotion Technology Co. Ltd.; G. P. Li – University of California, Irvine

3D Hemispherical Glass Shell Resonators Fabricated by Negative Pressure MoldingBin Luo, Jintang Shang and Yuzhen Zhang – Key Lab of MEMS of Education Ministry, Southeast University

A New Multi-Wafer Aligning Method to Fabricate High Aspect Ratio Microtraps Alireza Narimannezhad, Joshah Jennings, Marc H. Weber, and Kelvin G. Lynn – Washington State University

Substrate Integrated Waveguide (SIW) in Glass Interposers with Through-Package-ViasJialing Tong, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Aric Shorey – Corning Inc.

Synthesis of Magneto-Dielectrics from First Principles and Antenna DesignKyu Han, Madhavan Swaminathan, Pulugurtha Raj, Himani Sharma, and Rao Tummala – Georgia Institute of Technology; Brandon Rawlings, Songnan Yang, and Vijay Nair – Intel Corporation

Complementary Class-E Amplifier for Wireless Power TransferNurcan Keskin and Huaping Liu – Oregon State University

Heterogeneous Nucleation of Bulk Cu6Sn5 in Sn-Ag-Cu-Al and Sn-Cu-Al Solders

Jingwei Xian, Christopher Gourlay, Sergey Belyakov, Ben Britton, Zhenqi Li, and Zhaolong Ma – Imperial College London

Sputtered Ti/Cu as a Superior Barrier and Seed Layer to Enable High-Density RDL Structures for Interposers Chandrasekharan Nair, Fuhan Liu, Venky Sundaram, and Rao Tummala – Georgia Institute of Technology; Fabio Pieralisi, Uwe Muehlfeld, Markus Hanika, and Sesh Ramaswami – Applied Materials

Demonstration of Ultra-Thin and High-Density Tantalum Capacitors on Glass Substrates for High-Frequency and High-Efficiency Power ApplicationsParthasarathi Chakraborti, Saumya Gandhi, Himani Sharma, Raj Pulugurtha Markondeya, and Rao Tummala – Georgia Institute of Technology

Filler Size Dependence of Optical Reflectance for High Performance Polymer-Based ReflectorsYue Shao – University of California, Irvine

Modeling and Simulation for the Thermo-Mechanical Interfacial Reliability of Through-Silicon-Vias for 3D IC Integration

Hao Jiang, Gang Cao, Zhang Luo, Chunlin Xu, and Cao Li – Huazhong University of Science & Technology; Guoping Wang and Sheng Liu – Wuhan University

Analysis of Measurement Reliability of Hot-Film Air Flow Sensor Influenced by Air ContaminantChunlin Xu, Xing Guo, and Hao Jiang – Huazhong University of Science & Technology; Sheng Liu – Wuhan University; Wan Cao – FineMEMS Inc.

Review on Retrofit G4 LED Lamps: Technology, Challenges, and Future TrendsPan Liu, Henk van Zeijl, Robert Sokolovskij, Manjunath Venkatesh, Ralph Kurt, and Guoqi Zhang – Delft University of Technology

Reliability Study of Micro-Pin Fin Array Silicon DeviceDavid Woodrum and Suresh Sitaraman – Georgia Institute of Technology

Interactive Presentations: Thursday, May 28, 2:00 - 4:00 p.m. and Friday, May 29, 8:30 - 10:30 a.m.

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HOW TO REGISTER FOR ECTCBy Internet: Submit your

registration electronically via www.ectc.net. Your registration must be

received by the cutoff date, May 8, 2015, to qualify for the early

registration discounts.

You may contact our registration staff at [email protected] for

additional information. Payment can be made by Visa, MasterCard or

American Express.

Hotel Reservations1) Contact the Sheraton San Diego Hotel and Marina at +1-877-734-2726 and reference the ECTC Conference to receive the conference rate of US$189 per night.

or …2) Log onto www.ectc.net and click on the Location tab near the top of the page to find a special online hotel registration link.

Note about Hotel RoomsAttendees should note that only reputable sites should be used to book a hotel room for the 2015 ECTC. Be advised that you may receive emails about booking a hotel room for ECTC 2015 from 3rd party companies. These emails and sites are not to be trusted. The only formal communication ECTC will convey about hotel rooms will come in the form of ECTC e-blasts or ECTC emails from our Executive Committee. ECTC’s only authorized site for reserving a room is through our website (www.ectc.net). You may, however, use other trusted sites that you personally have used in the past to book travel. Please be advised, there are scam artists out there and if it’s too good to be true it likely is. Should you have any questions about booking a hotel room please contact ECTC staff at: [email protected]

Today’s hi-tech companies are being even more selective in choosing the conferences and trade shows where they will exhibit their products and services. Each year more companies have determined that ECTC provides them the best opportunity to identify superior prospects, and this year is no exception. The primary reason is that the engineers and managers who attend ECTC are the decision-makers in the world’s leading electronics equipment and component manufacturing companies. The attendees are attracted by ECTC’s strong technical program evidenced by the fact that authors in the field concur that ECTC offers the best forum for presenting their work.

Exhibit hours will be from 9:00 a.m. to noon and 1:30 to 6:30 p.m. on Wednesday, May 27, and 9:00 a.m. to noon and 1:30 to 4:00 p.m. on Thursday, May 28. Registration has been very active this year and in fact all of the booths in the exhibit hall have been reserved. Following is a list of exhibitors as of February 15, 2015. The exhibit brochure, a current exhibitor list, and a booth layout showing the available booths can be found on the ECTC web site at www.ectc.net under Technology Corner Exhibits. If you need additional information or have questions, call Joe Gisler at +1-480-288-6660 or email him at [email protected].

3D Systems Packaging Research CenterAGC Electronics America

AI Technology, Inc.Air-Vac Engineering

Alpha Novatech, Inc.Amicra Microtechnologies GmbH

Amkor Technology, Inc.ASE Group

AT & S AmericasBergquist Company (The)

Binghamton UniversityCamTek USA

CEA-LETICoreTech Systems (Moldex 3D)

CORWIL Technology Corp.CPS Technologies Corp.

CST of America, Inc.CVInc.

Dassault Systèmes SIMULIADECA Technologies

DISCO Hi-Tec America, Inc.Dow Corning Corp.

Dow Electronic MaterialsDynaloy

EnzoTechnology Corp.E-System Design

EV GroupFicontech (USA) Corp.

Finetech, Inc.Flip Chip International, LLC

Fraunhofer Center for Applied Microstructure Diagnostics CAM

Fraunhofer Institute for Reliability and Microintegration IZM

FRT of AmericaFS Inspection

FujiFilm Electronic MaterialsHD Microsystems

Henkel Electronic Materials LLCHeraeus

Huntsman Advanced MaterialsHysitron

i3 ElectronicsIBM Microelectronics - Packaging Development

IEN Ga TechIMAT, Inc.

InsidixInterconnect Systems, Inc.

JIACO InstrumentsJSR Micro, Inc.

Kingyoup Optronics Co., Ltd.KLA Tencor

Kyocera America, Inc.

LasertecLPKF Laser

Mentor GraphicsMini-Systems, Inc. (MSI)

MJS Designs, Inc.MRSI Systems

NAGASE & Co., Ltd.NAMICS Technologies, Inc.

NANIUM S.A.Neu Dynamics

Nikon Metrology, Inc.Nitto Denko America

Nordson DAGENTK Technologies, Inc.

Ormet Circuits, Inc.PAC TECH USA - Packaging Technologies, Inc.

Palomar TechnologiesPanasonic Factory Solutions

Panasonic IndustrialPlasma-Therm LLC

Promex Industries, Inc.Pure Technologies

QualiTauQuik-Pak

Royce InstrumentsRTI International

Samtec, Inc.Sanyu Rec

Savansys SolutionsSemiconductor Equipment Corp.

Senju ComtekSET - Smart Equipment Technology

Shin-Etsu MicroSi, Inc.Shinko Electric America

SonoscanSPTS TechnologiesSTATS ChipPAC

TechnicTechSearch International, Inc.

TecniscoTokyo Ohka Kogyo Co., Ltd.

Toray International America, Inc.Towa USATresky AG

Triton Micro Technologies, Inc.XIA LLCXYZTEC

YincaeYOLE DEVELOPPEMENT

ZiptronixZuken

Zymet, Inc.

2015 TECHNOLOGY CORNER EXHIBITS

Page 30: 65th ECTC Advance Program

30

65th Electronic Components & Technology Conference

2015 ECTC Conference Registration Information

Conference Registration Advance Registration Door Registration

IEEE Member Attendee (full conference) US $695 US $795

Speaker or Chair (full conference) $575 $695

One-Day Registration $525 $525

Speaker One-Day Registration $395 $395

Non-IEEE member Attendee (full conference) $840 $960

Speaker or Chair (full conference) $575 $695

One-Day Registration $525 $525

Speaker One-Day Registration $395 $395

Exhibit Booth Attendant $0 $0

Student Attendee or Speaker (full conference) $300 $300

Exhibits Only Not attending conference $25 $25

Professional Development Courses (PDCs)Note: all PDCs include a luncheon

IEEE Member Full PDC (both a.m. and p.m.) $575 $675

Single PDC (both a.m. or p.m.) $400 $475

Non-IEEE member Full PDC (both a.m. and p.m.) $625 $675

Single PDC (both a.m. or p.m.) $450 $475

Student Full PDC (both a.m. and p.m.) $125 $125

Other Registration Options

Extra Proceedings $100 $100

Extra Luncheon Tickets $50 $50

Cancellation Fee $50 $50

Please log onto: www.ectc.net/registration to register for the 2015 ECTC.There will be no refunds or cancellations after May 8, 2015. Please note that a US $50 cancellation fee will be in effect for all cancellations

made on or prior to May 8, 2015. Substitutions can be made at any time.

For additional information about registration or ECTC please contact us at:Renzi & Company, Inc. c/o 2015 ECTC

1304 Roundhouse Lane, #311Alexandria, VA 22314

email: [email protected]

*If you join IEEE BEFORE you register for the 2015 ECTC, you can save on registration fees and get Components, Packaging and Manufacturing Technology Society (CPMT) Society add-on membership free for one year!

To take advantage of this offer, simply follow:

http://www.ieee.org/go/CPMT_professional

At destination, create your IEEE Web Account. Once complete, proceed to the Shopping Cart and enter CPMT2015FREE in the promotion code box. Click “Apply” and the Shopping Cart will be updated to show the discount. Use your new IEEE membership id number and register for ECTC

at the discounted IEEE Member Rate.

*Non-IEEE members can join IEEE and save $100 or more on ECTC registration and receive CPMT Society membership free for 2015.IEEE members can join the CPMT Society free for the remainder of 2015 with ECTC registration.

Page 31: 65th ECTC Advance Program

31

May 26, 2015Morning Professional Development Courses

8:00 a.m. - 12:00 Noon1 Achieving High Reliability of

Lead-Free Solder Joints – Material Considerations

2 Fan-Out Wafer Level Packaging3 Package Failure Analysis

– Failure Mechanisms and Analytical Tools

4 Next Frontier in Electronics: Systems Scaling for Small and Ultra-Small Smart Mobile, Wearable, Medical, and IOP Systems

5 Polymers and Nano-Composites for Electronic and Photonic Packaging

6 Integrated Thermal Packaging and Reliability of Power Electronics

7 Fundamental Concepts of Reliability and Mechanics in Electronic Packaging

8 Fundamentals of Electrical Design and Fabrication Processes of Interposers, Including Their RDLs

Afternoon Professional Development Courses1:15 p.m. - 5:15 p.m.

9 Flip Chip Technologies 10 Wafer Level Chip Scale

Packaging11 Moisture and Media Influence

on Microelectronic Package Reliability

12 Thermal and Mechanical Simulation Techniques for IC Package Yield, Reliability, and Performance

13 Polymers for Electronic Packaging

14 Novel Interconnect and System Integration Technologies

15 Package Failure Mechanisms, Reliability, and Solutions

16 3D IC Integration and 3D IC Packaging

Special Session10:00 a.m. - 11:30 a.m.

“Sustainability in Microelectronics”

Technical Subcommittee Special Session

2:00 p.m. - 3:30 p.m.“Advancements in Bio-Medical Technology & Associated Packaging”

CPMT Women’s Panel and Reception

4:00 p.m. - 5:00 p.m.“Own Your Professional Success

– What You Should Do”

Panel Session7:30 p.m. - 9:00 p.m.“Nanopackaging: Hype, Hope, or Happening?”

May 27, 2015Technical Sessions

8:00 a.m. - 11:40 a.m.1 Flip Chip Packaging2 3D Technology: TSV

Fabrication and Reliability3 Solder Joint Reliability4 Adhesives, Underfills, and

Thermal Interface Materials5 Novel Manufacturing Solutions6 3D Technology: High-Speed

Components and Modeling

Interactive Presentation Sessions 37 & 38

9:00 a.m. - 11:00 a.m.2:00 p.m. - 4:00 p.m.

Technical Sessions1:30 p.m. - 5:10 p.m.

7 Interposer Technology8 3D Technology: TSV Bonding

Process Development and Characterization

9 Advancements in Substrate Technologies

10 Advanced Reliability Tests and Failure Analysis Methodologies

11 Thermal Compression Bonding: Challenges and Process Improvement

12 Advances in Signal Integrity

Plenary Session7:00 p.m. - 8:30 p.m.

“The Internet of Things and the Future of Interconnected

Electronics”

May 28, 2015Technical Sessions

8:00 a.m. - 11:40 a.m.13 3D Integration, TSV, and

Reliability14 Flip Chip: Bonding, Chip-

Package Interaction, and Electromigration

15 3D Technology: Materials and Reliability

16 Wearable, Bendable, Flexible Electronics

17 Advances in Power Integrity and Electromagnetic Interference

18 Advanced Optical Interconnects

Interactive Presentation Sessions 39 & 40

9:00 a.m. - 11:00 a.m.2:00 p.m. - 4:00 p.m.

Technical Sessions1:30 p.m. - 5:10 p.m.

19 3D Technology: Thermal and Performance Reliability

20 Wafer Level Packaging and PoP21 3D Materials and Processing22 Packaging for Internet of Things23 Emerging Wireless

Technologies24 Advanced Modeling in Solder

Joints, TSVs, and Copper Wire Bonding

CPMT Seminar8:00 p.m. - 9:30 p.m.

“Liquid and Phase-Change Cooling for High-Performance

Systems”

May 29, 2015Technical Sessions

8:00 a.m. - 11:40 a.m.25 Fan-Out and Wafer Level

Packaging26 Innovative Interconnection

Technologies27 3D Technology: Thermal

Materials and Modeling28 Emerging Interconnects29 Lead-Free Solder Joints30 Silicon Photonics and Light

Sources

Student Interactive Presentations Session 418:30 a.m. - 10:30 a.m.

Technical Sessions1:30 p.m. - 5:10 p.m.

31 MEMS and Sensors32 Packaging for Power and

Wirebond Innovations33 3D Technology: Latest

Innovations34 Novel Materials and Processes35 Package Warpage,

Delamination, and Thermal Modeling

36 Static and Dynamic Interconnect Reliability

CONFERENCE OVERVIEW

Session Summary by Interest Area3D/TSV Topics

S2, S6, S7, S8, S13, S15, S19, S21, S24, S27, S33

Advanced PackagingS1, S7, S13, S19, S20, S25, S31

Applied ReliabilityS3, S10, S15, S19, S36

Assembly & Manufacturing TechnologyS5, S11, S20, S33

Emerging TechnologiesS16, S22, S28

High-Speed, Wireless & ComponentsS6, S12, S23

InterconnectionsS2, S8, S14, S26, S28, S32

Materials & ProcessingS4, S9, S21, S27, S29, S34

Modeling & SimulationS6, S12, S17, S24, S27, S35

OptoelectronicsS18, S30

Interactive PresentationsS37, S38, S39, S40, S41

Page 32: 65th ECTC Advance Program

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