6.ece301 - dataflow modeling ( includes array data type)
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VITU N I V E R S I T Y
ECE 301 - VLSI System Design(Fall 2011)
Verilog HDL
Prof.S.Sivanantham
VIT UniversityVellore, Tamilnadu. India
E-mail: [email protected]
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After completing this lecture, you will be able to:
Describe what is the dataflow modeling Describe how to use continuous assignments
escr e ow o spec y e ays n con nuous ass gnmen s
Describe the data types allowed in Verilog HDL
Describe the operands may be used associated with aspecified operator
ECE301 VLSI System Design FALL 2011 S.Sivanantham
Slides are adopted from Digital System Designs and Practices Using Verilog HDL and FPGAs , John Wiley
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Rationale of dataflow: any digital system can be constructedy nterconnect ng reg sters an a com nat ona og c put
between them for performing the necessary functions.
.
Logic synthesis tools can be used to create a gate-level
circuit from a dataflow design description. RTL (register transfer level) is a combination of dataflow
and behavioral modeling.
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Continuous assignment: the most basic statement of dataflowmo e ng.
It is used to drive a value onto a net.
.
Any logic function can be realized with continuous
assignments.
It can only update values of net data types such as wire,triand, etc.
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A continuous assignment begins with the keywordassign.ass gn net_ va ue = express on;
assign net1 = expr1,net2 = expr2,...,netn = exprn;
net_lvalue is a scalar or vector net, or their concatenation. RHS operands can be variables or nets or function calls.
Registers or nets can be scalar or vectors.
e ay va ues can e spec e .
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An implicit continuous assignment
is the shortcut of declaring a net first and then writing acontinuous assignment on the net.
.
can only have one implicit declaration assignment per net.
wire out; // regularcontinuous assignment
assign out = in1 & in2;
wire out = in1 & in2; // implicit continuous assignment
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An implicit net declaration
is a feature of Verilog HDL. will be inferred for a signal name when it is used to the
.
wire in1, in2;
assign out = in1 & in2;
Note that: out is not declared as a wire, but an implicitwire declaration for out is done by the simulator.
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Three ways of specifying delays
Regular assignment delay Implicit continuous assignment delay
e ec ara on e ay
Regular assignment delays
.
The inertial delay model is used (default model).
assign #10 out = in1 & in2;
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Implicit continuous assignment delays
An implicit continuous assignment is used to specify boththe delay and assignment on the net.
.
// implicit continuous assignment delaywire #10 out = in1 & in2
// regular assignment delay
wire out;
assign #10 out = in1 & in2;
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Net declaration delays
A net can be declared associated with a delay value. Net declaration delays can also be used in gate-level
.
// net delays
wire #10 out;
assign out = in1 & in2;
// regular assignment delay
wire out;assign #10 out = in1 & in2;
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The essence of dataflow modeling is
expression = operators + operands
Operands can be any one of allowed data types.
pera ors ac on e operan s o pro uc es re resu s.
Operands:- constants- integers- real numbers
- time- bit-select- art-select
- nets- registers
- memories- function calls
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O erators
Arithmetic Bitwise Reduction Relational
+: add
- : subtract
* : multiply
/ : divide
% : modulus
~ : NOT
&: AND
| : OR
^: XOR
~ , ^~: XNOR
&: AND
|: OR
~&: NAND
~|: NOR
^: XOR
>= : greater than or equal
: greater than
: right shift
==: equality
&&: AND
|| : OR
! : NOT
===: equality
!==: inequality
{ , }: concatenation
{c{ }}: replication
? : conditional
>: arithmetic right shift
Equality
=: nequa y
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Operators Symbols
- ~
Precedence
Multiply, divide, modulus
* / %Exponent **
, -
> >Shift
Relational < >=== = === ==qua y
Reduction & ~&
^ ^~
Logical~
&&
||
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Conditional ?: Lowest
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The operands in an expression can be any of:
constants,
parameters,
ne s,
variables (reg, integer, time, real, realtime),
- ,
part-select,
arra element and
function calls
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Three types of constant in Verilog HDL are
nteger,
real, and
Integer constant
simple decimal form-123 // is decimal -123
12345 // is decimal 12345
base format notation16habcd // a 16-bit hexadecimal number
2006 // unsized number--a 32-bit decimal number
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, .
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Real constant
ec ma notat on1.5 //.3 // illegal ---
.
scientific notation
15E12-26.176_45_e-12
String constant
quotes (""). It may not be split into multiple lines. -
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.
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Two classes of data types:
nets: Nets mean any hardware connection points.
variables: Variables represent any data storage elements.
ar a e a a ypes
reg
time
real
realtime
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A reg variable
holds a value between assignments.
may be used to model hardware registers.
nee no ac ua y represen a ar ware s orage e emen .
reg a, b; // reg a, and b are 1-bit regreg : a a_a; an - reg, e ms sreg [0:7] data_b; // an 8-bit reg, the msb is bit 0reg signed [7:0] d; // d is an 8-bit signed reg
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The integer variable
contains integer values.
has at least 32 bits.
s rea e as a s gne reg var a e w e s e ng .integer i,j; // declare two integer variables
integer data[7:0]; // array of integer
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The time variable
is used for storing and manipulating simulation timequantities.
task.
holds only unsigned value and is at least 64 bits, with thelsb being bit 0.
time events; // hold one time value
_
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The real and realtime variables
cannot use range declaration and
their initial values are defaulted to zero (0.0).rea even s; ec are a rea var a e
realtime current_time; // hold current time as real
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A vector(multiple bit width) describes a bundle of signals asa as c un t.
[high:low] or [low:high]
.
Both nets andreg data types can be declared as vectors.
The default is 1-bit vectoror calledscalar.
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- -
Bit-Select and Part-Select
integer and time can also be accessed by bit-select orpart-select.
-select or part-select.
Constant part select: data_bus[3:0], bus[3] Variable part select:
[+:width]: data_bus[8+:8]
s ar ng_ -:w : a a_ us -:
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Array and Memory Elements
all net and variable data types are allowed to be declaredas multi-dimensional arrays.
is a net or reg data type.
wire a[3:0]; // a scalar wire array of 4 elementsreg d[7:0]; // a scalar reg array of 8 elementswire [7:0] x[3:0]; // an 8-bit wire array of 4 elements
reg [31:0] y[15:0]; // a 32-bit reg array of 16 elementsinteger states [3:0]; // an integer array of 4 elementstime current[5:0]; // a time array of 6 elements
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Memory
Memory is used to model a read-only memory (ROM), arandom access memory (RAM), and a register file.
a portion of a word of memory.
reg [3:0] mema [7:0]; // 1-d array of 4-bit vectorreg [7:0] memb [3:0][3:0]; // 2-d array of 8-bit vectorwire sum [7:0][3:0]; // 2-d array of scalar wire
mema[4][3] // the 3rd bit of 4th elementmema[5][7:4] // the higher four bits of 5th element
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mem : e ower wo s o e emensum[5][0] // [5][0]th element
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Bitwise operators
They perform a bit-by-bit operation on two operands.
A z is treated as x in bit-wise operation.
e s or er operan s zero-ex en e o ma c e engof the longer operand.
Symbol
~
&
Operation
Bitwise negation
Bitwise and
|^
~^, ^~
Bitwise orBitwise exclusive or
Bitwise exclusive nor
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An Exam le --- A 4-to-1 MUX
module mux41_dataflow(i0, i1, i2, i3, s1, s0, out);
input i0, i1, i2, i3;input s1, s0;output out; s0
s1i0
Using asic an , or , not ogic operators.assign out = (~s1 & ~s0 & i0) |
(~s1 & s0 & i1) |s1 & ~s0 & i2
_
out
i1
(s1 & s0 & i3) ;endmodule
un4_outout
i2
un6_out
i3
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un8_out
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Arithmetic operators any operan t as a va ue x, t en t e resu t s x.
The operators + and can also used as unary operators tore resent si ned numbers.
Modulus operators produce the remainder from thedivision of two numbers.
,negative numbers. Symbol
+
Operation
Addition
-
*
/
u rac on
Multiplication
Division
** Ex onent ower
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% Modulus
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Concatenation operators
The operands must be sized. Operands can be scalar nets or registers, vector nets or
- -, , , . Example: y = {a, b[0], c[1]};
Replication operators They specify how many times to replicate the number
inside the braces. Exam le: = a 4 b 0 c 1
Symbol
{ , }
Operation
Concatenation
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{const_expr{}} Replication
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--- -
module four_bit_adder(x, y, c_in, sum, c_out);
// I/O port declarationsinput [3:0] x, y; // declare as a 4-bit array
_output [3:0] sum; // declare as a 4-bit arrayoutput c_out;
[3:0]x[3:0]
[3:0]
// Specify the function of a 4-bit adder.assign {c_out, sum} = x + y + c_in;
endmodulesum_1[4:0]
+sum[3:0]
[4:0][3:0] [3:0][3:0]
c_out[4]
sum[3:0][3:0]
c_in
y[3:0][3:0]
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--- -
module twos_adder(x, y, c_in, sum, c_out);por ec ara ons
input [3:0] x, y; // declare as a 4-bit arrayinput c_in;output [3:0] sum; // declare as a 4-bit arrayoutput c_out;wire [3:0] t; // outputs of xor gates
'assign t = y ^ {4{c_in}};assign {c_out, sum} = x + t + c_in;
endmodule
t3:0
+sum3:0
[3:0][3:0]
[3:0]
[4:0][3:0] [3:0][3:0]sum[3:0]
[3:0]
y[3:0][3:0]
x[3:0] [3:0]
ECE301 VLSI System Design FALL 2011 S.Sivanantham
sum_1[4:0]
c_out[4]
c_in
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Reduction operators
perform only on one vector operand.
carry out a bit-wise operation on a single vector operand- .
work bit by bit from right to left.
&
~&
Reduction and
Reduction nand
~|
^
e uct on or
Reduction nor
Reduction exclusive or
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~^, ~ Reduction exclusive nor
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--- -
module parity_gen_9b_reduction(x, ep,op);// I/O port declarations
input [8:0] x;output ep, op;
assign ep = ^x; // even parity generatorassign op = ~ep; // odd parity generator
endmodule
[0]
[1]
[2]
[3]
op[5][6]
[7]
[8]
op
epx[8:0] [8:0]
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ep
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--- - -
module all_bit_01_detector_reduction(x, zero,one);// I/O port declarations
input [7:0] x;output zero, one; [0]
[1]
assign zero = ~(|x); // all-bit zero detectorassign one = &x; // all-bit one detector
endmodule
[3]
[4]
[5]
[6]
[7]
zero
un _zero
[0]
[1]
x[7:0][7:0]
[2]
[3][4]
[5]
[6]
[7]
one
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one
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Logical operators
They always evaluate to a 1-bit value, 0, 1, or x.
If any operand bit is x or z, it is equivalent to x and.
Symbol Operation!
&&
||
Logical negation
Logical and
Logical or
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Relational operators
They return logical value 1 if the expression is true and 0
if the expression is false.
(x) or z bits in the operands.
Symbol
>
=
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Equality operators compare t e two operan s t y t, w t zero ng
the operands are of unequal length. return lo ical value 1 if the ex ression is true and 0 if the
expression is false. The operators (==, !=) yield an x if either operand has x or z
. The operators (===, !==) yield a 1 if the two operands match
exactly and 0 if the twoSymbol Operation
operan s not matcexactly. ==!====
Logical equalityLogical inequality
Case equality
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!== Case inequality
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--- -
013 2
B0
B1B3
B2
A>B
IA=BIAB
OA=B
OA b) || ((a == b)&& (Iagtb == 1)); // greater than
= < == ==
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endmodule
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// example to illustrate logic and arithmetic shiftsmo u e ar me c_s x,y,z ;input signed[3:0] x;output [3:0] y;output signed[3:0] z;assign y = x >> 1; // logical right shiftassign z = x >>> 1; // arithmetic right shiftendmodule
Note that: net variables x and z must be declared with the ke wordsi ned .
Replaced net variable with unsigned net (i.e., remove the keywordsigned)and see what happens.
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Conditional Operator
Usage: condition_expr ? true_expr: false_expr;
The condition_expr is evaluated first.
e resu s rue en e rue_expr s execu e ;otherwise the false_expr is evaluated.
if condition ex r true ex r _ _else false_expr;
a 2-to-1 multiplexer
assign out = selection ? in_1: in_0;
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The Conditional O erator --- A 4-to-1 MUX
module mux4_to_1_cond (i0, i1, i2, i3, s1, s0, out);or ec ara ons rom e agram
input i0, i1, i2, i3;input s1, s0;output out;
un1_s1_1
s0s1
// Using conditional operator (?:)assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;endmodule
un1 s1 2
ed
e
d out
i3
_ _
out
d
ed
i2i1
i0
un1_s0_1
ECE301 VLSI System Design FALL 2011 S.Sivanantham
un1 s0 2