6.xi constraints 1762

6.xi Timing and Constraints 2

IntroductionPERIOD ConstraintsOFFSET ConstraintsFROM:TO ConstraintsModular Design Constraints


Design Flow

NGC/EDIF netlist

NGDBUILDFlatten Hierarchical Design

MAPLogical to Physical translationGroup LUTs and FFs into CLBs

TRCEStatic Timing Estimates

BITGENGenerates configuration file

.BIT

UCFUser Constraints File

.NGD

.PCF.NCD

PARLayout of Physical Design Routes Physical Design

.NCD

Optional: Reports block delays


Internal clock speed for one or more clocksI/O speedLogic using multi-cycle clocksPad to Pad timingPad Locations & Logic Locations

OUT1

X

Y

Z<0:9>

OUT22 Levels of Logic

Clk & CE Speed I/O Speed

Pin 2 Pin Speed

I/O Speed

PinLocations

PinLocations

LogicLocations

1 Level of Logic

QD QD

CLK


Timing ConstraintsSpecify delay along logic paths

Allows both high level and highly detailed timing controlLocation Constraints

Specify location of components on FPGASpecify mapping constraints IN

ST MY_FMAP B

LK NM=ABC

INST FLOP1 B

LK NM=ABC

INST FLOP2 B

LK NM=ABC


What is the motive behind timing analysisMeet the desired frequency by:

Coverage (100% is ideal case)Slack (Timing budget must account for jitter, noise,etc)Special Case analysis (Multi-Cycle, False path)

How is this accomplished?Constraints!

TimingPlacement


They can be input in a separate filecalled a .UCF (User Constraints File)They can be added to HDL source codeif your compiler supports themTiming constraints may be applied to aSchematic using the TIMESPEC symbol(FROM:TO s)

Note: This is the order of priority between these files.

TIMESPEC


FPGA Editor

PHYSICAL DOMAIN

LOGICAL DOMAIN

User netlistand logicalconstraints

Mapped design and physical constraints

DESIGN TRANSLATION

PAR TRCE NGDANNO DRC

NGC/EDIF netlist UCFUser Constraints File

NGDBUILD

MAP

.PCF.NCD


Where do you find syntax?Constraints Guide (SW Manuals)http://www.xilinx.com/support/sw_manuals/xilinx6/index.htm

Constraints EditorThis is a great tool to write out constraints for youwith the correct syntax

Online Timing presentationTech tips -> Timing and Constraint -> RelatedFeatures


What constraints are important to be familiarwith?

PERIODOFFSETCreating Groups (TNM, TNM_NET, TIMEGRP)FROM:TOTIMESPEC

Using PERIOD andOFFSET constraints


Setup CalculationAn internal setup violation occurs when the datachanges at the destination FF after the clock arrives.

Hold CalcuationAn internal hold violation occurs when the datachanges at the destination FF before the clockarrivesThe data delay is less than the positive clock skew

2ns


PERIOD is the duration of the clock and can beconfigured to have different duty cyclesDerived clocks can be defined as a function of anotherclock (*,/) and will have cross clock domain analysisdone.PERIOD is preferred over FROM:TO constraints; Thetools will have a faster runtime. PERIOD should covermost of design.PERIOD only covers from Sync. Elements to Sync.Elements, like Flip flops to flip-flops


The PERIOD constraint covers paths between synchronouselements clocked by the reference netThe PERIOD constraint does NOT analyze delay paths:

From input pads to output pads (purely combinatorial)From input pads to synchronous elementsFrom synchronous elements to output padsBetween unrelated clocks

= Constrained Data Path

BUFG

CLKA

ADATA

OUT2

OUT1Q

FLOP3

DQ

FLOP1

D

Q

FLOP5

DQ

FLOP4

DBUS [7..0]

CDATA

Q

FLOP2

D

BUFG

CLKB = Unconstrained Data Path


BUFG

CLK

FF1 FF2

The PERIOD constraint takes the following into account:Data path delayClock skew on global and local clocksClock phase including DCM phase and negative edge clockingClock duty cycles

HOLD violation check is done forall paths


Clock skew = destination clock path delay - source clockpath delayPositive clock skew is truncated to 0 in the timing report forsetup paths

Positive clock skew is used in hold time calculations


Q

ff_0f

D Q

ff_90

D

DCM

CLKIN

CLK0

CLK90

clk20g

clk20_90g

clk20Tiopi = 0.825

net = 0.798

Tdcmino = -4.197

net =0.852net =0.860 net = 0.639

Tgi0o =0.860

net = 0.639

Destination Clock Delay - Source Clock Delay(0.825 + 0.798 + -4.197 + 0.860 + 0.860 + 0.639) -(0.825 + 0.798 + -4.197 + 0.852 + 0.860 + 0.639) = 0.008 ns


PERIOD analyzes the following:Synchronous element to synchronous element data path calculationsAutomatically deals with inverted clock pinsDeals with non 50% duty cycles clocks

If the Source Clock Timing Constraint is related to the Destination ClockTiming Constraint, the Destination Clock Timing Constraint

will cover crossclock domain analysis.

Period#1 Period#2

Period#2 will control this path,if derived. (TS_Period#1 * 2)


PERIOD will trace THROUGH the Address pins of all RAM, andTO the D/WE pins of Sync RAM (THROUGH WE of Async RAM)

WE

ADDRESS

DWE

WCLK

ADDRESS

Sync RAM

ASync RAM


User entered constraint on DCM clock inputNET "clk20" TNM_NET = "clk20";TIMESPEC "TS_clk20" = PERIOD "clk20" 20 ns HIGH 50 %;

Translate step generates DCM clock constraintsCLK0: TS_clk20_0=PERIOD clk20_0 TS_clk20*1.000000 HIGH 50.000000%

CLK90: TS_clk20_90=PERIOD clk20_90 TS_clk20*1.000000 PHASE + 5.000000 nSHIGH 50.000000%

DCM

CLKIN

CLK0

CLK90

clk20clk20_0

clk20_90


TIMESPEC TSidentifier =PERIODTNM_reference period {HIGH | LOW}

[high_or_low_time]Covers all synchronous to synchronous pathswith the same reference netexamplenet clk TNM = clk_in ;TIMESPEC TS_clk_in = PERIOD clk_in 10 ns HIGH50%;


By netNET CLK300 PERIOD = 3.334 ns ;

NET CLK200 PERIOD = 5 HIGH 20 ;

By group: (The Recommended Way)NET CLK50 TNM_NET = CLK50_GRP ;#OR NET CLK50_I TNM = CLK50_GRP;

NET CLK25 TNM = CLK25_GRP ;

TIMESPEC TS_CLK_FULL = PERIOD CLK50_GRP 20;

TIMESPEC TS_CLK_HALF = PERIOD CLK25_GRP TS_CLK_FULL * 2 ;

(Note: Must use signal after global buffer for TNM groups. See TNM/TIMEGRPSection for details)

BUFG

TNM=CLK50_GRPTNM_NET=CLK50_GRP


Recommended wayAllows PERIOD to be passed through DCM byNGDBuildAllows constraints to be related using theTIMESPEC name


Clocks are related by using the period constraintClocks are not related based upon the designTranslate process creates period constraints on the outputDCM clocks relative to the user defined period constraint onthe DCM input clock

RelatedTIMESPEC "TS_clk20" = PERIOD "clk20_grp" 20 ns;TS_clk20_0=PERIOD clk20_0_grp TS_clk20*1.0;TS_clk20_90=PERIOD clk20_90_grp TS_clk20*1.0 PHASE + 5.0;

UnrelatedTS_clk20_0=PERIOD clk20_0_grp 20 ns;TS_clk20_90=PERIOD clk20_90_grp 20 ns PHASE + 5.0;


Updated!

Data path with Cross ProbingLinks to Floorplanner orSynthesis Tool(In Timing Analyzer)

Updated Logic LevelsOnly levels of logic, not Clockto Out and Setup

Slack equation

Basic element type is listed

Clock names and time ofactive edge. Includes ClockPhase

Web link to graphicalpicture of delay type! (InTiming Analyzer)


New!

CLK0

CLK90

0 10 20 30 40

5 15 25 35

Q

ff_0f

D Q

ff_90

D

DCM

CLKIN

CLK0

CLK90

clk20g

clk20_90g

15 ns

Clock edge andtime of activeedge

Requirement isdifferencebetween clockedges


The path requirement will automatically be reduced by half if a two-phaseclock is detected

Single-Phase Maximum

Two-Phase Maximum ================================================================================Timing constraint: TS_CLK = PERIOD TIMEGRP "CLK" 6 nS HIGH 50.000000 % ;

3 items analyzed, 0 timing errors detected. Minimum period is 2.618ns.--------------------------------------------------------------------------------Slack: 1.691ns (requirement - (data path - negative clock skew)) Source: a2

Destination: a3

Requirement: 3.000ns Data Path Delay: 1.309ns (Levels of Logic = 2) Negative Clock Skew: 0.000ns Source Clock: CLK_BUFGP falling at 3.000ns Destination Clock: CLK_BUFGP rising at 6.000ns

Data Path: a2 to a3

Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tcko 0.320 a2

net (fanout=1) 0.778 a2

Tdick 0.211 a3

---------------------------- ------------------------------ Total 1.309ns (0.531ns logic, 0.778ns route)

(40.6% logic, 59.4% route)

6ns is the maximum allowed PERIOD declared in the UCF

Two-phase clock is indicated here

This indicates the magnitude of the path delay between flops. There is no adjustment to this figure.

This indicates that the worst-case period for thisENTIRE spec is 2.618ns (1.309ns x 2). If there had been a single-phase path in this PERIOD spec that was 3ns, it would have been reported as the worst-case value, if it were 2ns, itwould not.

This is the remaining slack (6ns/2 - 1.309ns = 1.691ns).

TRCE cut the spec in half (6ns/2=3ns) for this path


CLK(at source FF)

0 2 4 6 8 10 12

2ns

DATA(at source output FF)

CLK(at destination FF)

DATA(at destination input FF)

Q

Source

D Q

Destination

D

CLK

DATA

2 ns

1 ns

DATA_IN(at source input FF)

DATA_OUT(at destination output FF)

DATA1DATA0

DATA1DATA0

DATA1DATA0

DATA1 DATA2

DATA_IN DATA_OUT


Hold Errors shown after the associated PERIOD constraint

Clock to Out is part ofdata delay

FF Hold Time, often thisis negative

Hold equation =Data - Clock Skew

Clock skew is greaterthan data delay


New

Support forfamilies that havethe InteractiveDatasheetInformation insoftware help

not web


User entered constraint on DCM clock inputNET "clk20" TNM_NET = "clk20";TIMESPEC "TS_clk20" = PERIOD "clk20" 20 ns HIGH 50 %;

Translate step generates DCM clock constraintsCLK0: TS_clk20_0=PERIOD clk20_0 TS_clk20*2.000000 HIGH 50.000000%CLK90: TS_clk20_90=PERIOD clk20_90 TS_clk20*2.000000 PHASE + 5.000000 nS

HIGH 50.000000%

DCM

CLKIN

CLK0

CLK90

clk20clk20_0

clk20_90

If this property is set to TRUE, the PERIOD specificationscreated at the DCM output will be adjusted accordingly


Timing Report documentation was re-writtenDocumentation shows an actual report with explanationsabout each section


OFFSETs allows the user to specify the internal data delayfrom/to the I/Os with respect to the clock

OFFSET IN BEFOREOFFSET OUT AFTER

Alternatively, OFFSETs allows the user to specify externaldata and clock relationships for the timing on paths to and fromthe I/Os. The software determines the internal requirements

OFFSET IN AFTEROFFSET OUT BEFORE

Clock delay is used in the equation


FPGA

CLK

d1

d2 d3

d4

DEV1 DEV2

OFFSET IN OFFSET OUT

Internal delays determined by the tools


The OFFSET constraints defines the relationshipbetween the data and the initial edge of the clock at thepins of the FPGA

The OFFSET Constraint does not optimize paths clocked byan internally generated clock.

The initial edge of the clock is defined with the PERIODconstraint using HIGH/LOW keyword

Initial edge rising (default)TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %;

Initial edge fallingTIMESPEC TS_clock = PERIOD clock_grp 10 ns LOW 50 %;


The OFFSET IN constraint covers paths from the input pads tosynchronous elements taking clock delay into account.The OFFSET IN constraint does NOT optimize paths clocked byinternally generated clocks


BUFG

CLKA

ADATA

OUT2

OUT1Q

FLOP3

DQ

FLOP1

D

Q

FLOP5

DQ

FLOP4

DBUS [7..0]

CDATA

Q

FLOP2

D

BUFG



Setup = Data Delay + FF Setup - Prorated (Clock Delay)The longer the clock delay, the smaller the external setup timetherefore clock delay is good for fast setup timesTRCE/Timing Analyzer uses a prorating factor on the clock delayand a maximum delay for the data delay.A setup violation in the device could be caused by the the datadelay, at the maximum (slow) and the clock delay, running fasterthan the maximum.

What is the prorating factor?85% for Global Routes80% for Local Routes

Note: Prorating is only done for VirtexII and newer families.


Hold reported in datasheet section of the report and in the detailedsection with the fastpaths option enabled.Hold = Clock Delay + FF Hold - Prorated (Data Delay)

The longer the data delay, the smaller the hold time therefore data delay isgood for hold timesTRCE/Timing Analyzer uses a prorating factor on the data delay and themaximum delay for the clock delay.A hold violation in the device could be caused by the clock delay can be atthe maximum (slow) and the data delay running faster than the maximum.

What is the prorating factor?85% for Global Routes80% for Local Routes

Note: Prorating is only done for VirtexII and newer families.


NET CLK PERIOD = 20nS HIGH;NET Din OFFSET = IN 2nS BEFORE CLK;

CLK

UPSTREAM DEVICE FPGA

In other words: The designer guarantees that the data will be valid here, at its input data pad, 2ns BEFORE the reference clockedge arrives here, at its clock pad.

2ns

Datacreatedfromupstreamdevice onthis fallingedge.

Data registered into FPGA on

this falling edge.

Din

CLK

Valid

Reference clock edgespecified with HIGH

keyword in clock PERIOD


The initial edge of the clock defines time 0nsPERIOD defines the rising edge is the initial edge at time 0nsThe OFFSET constraint is in reference to time 0nsData is valid 3ns before the initial edge of the clock

Slack = (Requirement - (Data Path - Clock Path - Clock Arrival))Clock Arrival will be 0 ns since initial edge is rising edge

clock_in

dataTIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %;OFFSET = IN 3 ns BEFORE clock;

3ns 10 ns


3ns 10 ns

data

clk90

Data is valid 3ns before rising edge of clockTIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %;

OFFSET = IN 3 ns BEFORE clock;

Slack = (Requirement - (Data Path - Clock Path - Clock Arrival))Clock Arrival will be 2.5 ns

clock_in


3ns 10 ns

data

clk0



Slack = (Requirement - (Data Path - Clock Path - Clock Arrival))Clock Arrival will be Fixed Phase Shift Amount

clock_in


data_fallingdata_rising

2ns 3ns 10 ns 3ns

Data valid 3ns before rising and falling edgeTIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %;


OFFSET = IN -2 ns BEFORE clock TIMEGRP falling_ffs_grp;Note: Data is valid 2ns after the initial (rising )edge therefore use -2

Slack = (Requirement - (Data Path - Clock Path - Clock Arrival))Clock Arrival will be 0 ns for rising edge and 5 ns for falling edge

clock_in


Slack equation

Data Path Delay

Clock Path Delay

Clock name andtime of active edge


CLK20

CLK20_90

0 5 10 15 20 25 30 35 40

DATA

TIMESPEC TS_CLK20 = PERIOD CLK20_grp 20 HIGH 50%;NET DATA OFFSET = IN -2 BEFORE CLK20;

2ns

Clock edge andtime of active edge


NET CLK PERIOD = 20nS HIGH;NET Din OFFSET = IN 16nS AFTER CLK;

CLK

UPSTREAM DEVICE FPGA

In other words: The Data to be registered in the FPGA will be available on the FPGA s input Pad 16ns AFTER the reference clock pulse is seen by the Upstream Device. For the purposes of the OFFSET constraint syntax, assume no skew on CLK between the chips. A PERIOD constraint is required to indicate when the subsequent clock pulse will be seen by the FPGAto clock in the Data.

16ns

Data Outof DEV1 onthis edge.

Data registeredin FPGA onthis edge.

Din

CLK

Valid

Reference clock edgespecified with HIGH

keyword in clock PERIOD


The OFFSET OUT constraint covers paths from synchronouselements to output pads taking clock delay into account.The OFFSET OUT constraint does NOT optimize paths clockedby internally generated clocks


BUFG

CLKA

ADATA

OUT2

OUT1Q

FLOP3

DQ

FLOP1

D

Q

FLOP5

DQ

FLOP4

DBUS [7..0]

CDATA

Q

FLOP2

D

BUFG



NET CLK PERIOD = 20nS LOW;NET Din OFFSET = OUT 5nS AFTER CLK

In other words: The Data to be registered in the Downstream Device will be available on the FPGA s data output pad 5ns AFTERthe reference clock pulse is seen by the FPGA, at its clock pad.

DOWNSTREAM DEVICEFPGA

5nsData createdfrom FPGA onthis fallingedge.

Data registeredinto downstream

device onthis rising edge.

Valid

Falling reference clockedge specified with LOWkeyword in clock PERIOD


TIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %;OFFSET = OUT 3 ns AFTER clock;

The initial edge of the clock defines time 0nsPERIOD defined with HIGH means the rising edge is theinitial edge at time 0nsThe OFFSET constraint is in reference to time 0nsData is valid 3ns after the initial edge

Slack = (Requirement - (Clock Arrival + Clock Path + Data Path))Clock Arrival will be 0 ns since initial edge is a rising edge

data

3ns 10 ns

clock_in


5ns 10 ns

data

clk90

Data is valid 5ns after rising edge of clockTIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %;

OFFSET = OUT 5 ns AFTER clock;

Slack = (Requirement - (Clock Arrival + Clock Path + Data Path))Clock Arrival will be 2.5 ns

clock_in


5ns 10 ns

data

clk0



Slack = (Requirement - (Clock Arrival + Clock Path + Data Path))Clock Arrival will be Fixed Phase Shift Amount

clock_in


data_fallingdata_rising

8ns

3ns 10 ns

3ns

Data is valid 3ns after rising and falling edgeTIMESPEC TS_clock = PERIOD clock_grp 10 ns HIGH 50 %;


OFFSET = OUT 8 ns AFTER clock TIMEGRP falling_ffs_grp ;

Slack = (Requirement - (Clock Arrival + Clock Path + Data Path))Clock Arrival will be 0 ns for rising edge and 5 ns for falling edge

clock_in


Slack equation

Data Path Delay

Clock Path Delay



CLK20

CLK20_90

0 5 10 15 20 25 30 35 40

DATA

TIMESPEC TS_CLK20 = PERIOD CLK20_grp 20 HIGH 50%;NET DATA OFFSET = OUT 17 AFTER CLK20;

17nsDATA



Valid

NET CLK PERIOD = 20nS HIGH;NET Din OFFSET = OUT 15nS BEFORE CLK;

This says, Data will be valid here, 15nS BEFORE the clock arrives here! ..In other words: The Data to be registered in the Downstream Device will be available on the FPGA s output Pad 25ns BEFOREthe clock pulse is seen by the Downstream Device. For the purposes of the OFFSET constraint syntax, assume no skew onCLK between the chips. A PERIOD constraint is required to indicate when the reference clock pulse was seen by the FPGAto clock out the Data.

15nsData Outof FPGA onthis edge.

Data IntoDEV2 onthis edge.

d4

FPGA


The following two UCF files are equivalent:NET CLOCK PERIOD=40;##External (shown in diagram)TIMEGRP ADD_IN_GRP OFFSET = IN 14 AFTER CLOCK;TIMEGRP ADD_OUT_GRP OFFSET = OUT 25 BEFORE CLOCK;

NET CLOCK PERIOD=40;##Internal (not shown in diagram):TIMEGRP ADD_IN_GRP OFFSET = IN 26 BEFORE CLOCK;TIMEGRP ADD_OUT_GRP OFFSET = OUT 15 AFTER CLOCK;

QDD Q

Determined by tools

QD

CLOCK

QD

XILINX DEVICEUpstream Device

Downstream Device

14ns 40ns 25nsDetermined by tools

The BEFOREand AFTER

variations of theOFFSET arerelated by thetotal period


Global: All inputs/outputs are offset relative to a clock.For example: OFFSET = IN 2ns BEFORE clk1

Indicates that all inputs will have data present at the pad at least 2ns beforethe reference edge of clk1 arrives at the pad.

Grouped: User specified group of padsFor example: TIMEGRP my_input_pad OFFSET = IN 2n BEFORE clk1

Indicates that all inputs will have data present at the pad at least 2ns beforethe reference edge of clk1 arrives at the group my_input_pad of pads.

Net-Specific: A specific input/output is offset relative to a clock.For example: NET DATA_IN OFFSET = IN 2ns BEFORE clk1

Indicates that DATA_IN will have data present at the pad at least 2ns beforethe triggering edge of clk1 arrives at the data_in pad.


You can also add a clock register time group.

TIMEGRP BEF = FFS(Out*);TIMEGRP DATA_GROUP OFFSET = IN 10 BEFORE CLK BEF;This restricts the constraint to registers B, E, and F.

TIMEGRP DATA_GRP = PADS(DATA*);NET CLK PERIOD = 20nS; TIMEGRP DATA_GRP OFFSET = IN 10 BEFORE CLK;

Data Path Groups allow the user to define a specific set of input pads to which anOFFSET constraint applies. Consider the following example.

A B

D

C

Data1

Data2

Data3

Input

E

F

G

Out1

Out2

Out3

Result


Clock register time groups allows the user to define a specificset of registers to which an OFFSET constraint applies basedon a clock edge. Consider the following example.

CLK

A B CDATA

You can define time groups for the registers A,B, and C, even though these registers have the same dataand clock source. TIMEGRP AB = RISING FFS; TIMEGRP C = FALLING FFS; This allows the userto perform two different timing analysis for the registers.

NET CLK PERIOD = 20nS; OFFSET = IN 4nS BEFORE CLK TIMEGRP AB;OFFSET = IN 6nS BEFORE CLK TIMEGRP C;


Global OFFSET constraintsOFFSET = in 5 ns before clockOFFSET = out 7 ns after clock

Specific OFFEST constraintsTIMEGRP my_pads_grp OFFSET = in 5 ns before clk;

my_pads_grp_ is a user defined group.

NET my_input_net OFFSET = in 5 ns before clk;

NOTE: OFFSET constraints have to reference a clock net that exist ata pad. Internally generated clocks can not be used in OFFSETspecification

OFFSET = out 7 ns after clock;


Wildcard Grouping SpecificationNET ADDR_<*> TNM = ADDR_IN_GRP;

TIMEGRP ADDR_IN_GRP OFFSET = IN 15 AFTER clk50;

NET ADDR_<*> TNM = ADDR_OUT_GRP;

TIMEGRP ADDR_OUT_GRP OFFSET = OUT 35 BEFORE clk50;

Global ControlOFFSET = IN 35 ns BEFORE COMP clk50 ;

OFFSET = OUT 30 ns AFTER COMP clk50 ;


Handled as clock phase instead of clock delayMust have following two DCM attributes:

PHASE_SHIFT={-255/255}CLKOUT_PHASE_SHIFT=FIXED or VARIABLE

NGDBUILD adds phase to the PERIOD constraintusing the PHASE keywordExample from NGDBUILD report file

CLK0: TS_fixed_phase_clk_0=PERIOD fixed_phase_clk_0TS_dcm_clk_in*1.000000 PHASE + 0.781250 nS HIGH 50.000000%


Slack is 8.414ns

Fixed PhaseShift accountedin Clock ArrivalTime

DCM delay does notcontain Fixed Phase Shift:(-3.301 + 0.781 = -2.520)

Total Clock Delay


QD

CLK

DATA

QD

Create PeriodNET CLK TNM_NET = CLK_GRP;TIMESPEC "TS_CLK" = PERIOD CLK_GRP" 5 ns HIGH 50%;

Create GroupsINST DATA_IN[*] TNM = DATA_IN;TIMEGRP FF_RISING = RISING CLK_GRP ;TIMEGRP FF_FALLING = FALLING CLK_GRP;

Create OFFSET constraintTIMEGRP DATA_IN OFFSET IN = 1 BEFORE CLK TIMEGRP FF_RISING;TIMEGRP DATA_IN OFFSET IN = -1.5 BEFORE CLK TIMEGRP FF_FALLING;

CLK

0 2.5 5

DATA_IN

1ns -1.5ns


QD

CLK

DATA

QD


Create GroupsINST DATA_IN[*] TNM = DATA_IN;

TIMEGRP FF_FALLING = FALLING CLK_GRP;

Create OFFSET constraintOFFSET IN = 1 BEFORE CLK;TIMEGRP DATA_IN OFFSET IN = -1.5 BEFORE CLK TIMEGRP FF_FALLING;

CLK

0 2.5 5

DATA_IN

1ns -1.5ns



Create GroupsINST DATA_OUT[*] TNM = DATA_OUT;TIMEGRP FF_RISING = RISING CLK_GRP ;TIMEGRP FF_FALLING = FALLING CLK_GRP;

Create OFFSET constraintTIMEGRP DATA_OUT OFFSET OUT = 1.25 AFTER CLK TIMEGRP FF_RISING;TIMEGRP DATA_OUT OFFSET OUT = 3.75 AFTER CLK TIMEGRP FF_FALLING;

CLK

CLK

0 2.5 5

DATA_OUT

1.25ns 3.75nsQD

DATA_HI

QD DATA_LO

DATA_OUT



Create GroupsINST DATA_OUT[*] TNM = DATA_OUT;TIMEGRP FF_FALLING = FALLING CLK_GRP;

Create OFFSET constraintOFFSET OUT = 1.25 AFTER CLK;

TIMEGRP DATA_OUT OFFSET OUT = 3.75 AFTER CLK TIMEGRP FF_FALLING;

CLK

CLK

0 2.5 5

DATA_OUT

1.25ns 3.75nsQD

DATA_HI

QD DATA_LO

DATA_OUT


IO Timings are reported in the Datasheet ReportSetup/Hold for Inputs

Setup = data path - clock path - clock arrival + uncertainty

Hold = clock path + clock arrival + uncertainty - data path

Clock to Out for OutputsClk2Out = clock path + data path + uncertainty

Numbers do include any clock phaseNumbers do include clock delay

This includes delay introduced by DESKEW_ADJUST

Setup and Hold are calculated using MAX-MAX* numbers

Note: MAX* are prorated values for VirtexII and newer families


Offset only covers IO timing with External clocksUse FROM-TO constraint to cover IO clocked byinternal clocks (clocks generated by LUT or FF)Create Groups

INST DATA_OUT[*] TNM = DATA_OUT;

Create FROM:TO constraintTIMESPEC TS_DATA = FROM FFS TO DATA_OUT 3;

Creating Groups andUsing FROM:TOconstraints


A FROM-TO constraint defines the delay between two groups oflogic

Logic paths typically start and stop at pads, registers, latches, RAM,multipliers, CPUs and high speed IOs (MGT)

It is used to constrain the following types of paths:Multi-cycle paths --If not expected to meeting the original single cycleclock periodData paths between unrelated clocksFalse Paths --If paths/net that are known not to have a timing requirement

No HOLD violation check is done for FROM:TO paths


Timing constraints are applied to logic pathsLogic paths typically start and stop at pads, and synchronous elementsThe tool recognizes the following keywords to define endpoints or time groups:PADS All I/O padsFFS All flip-flopsLATCHES All latchesRAMS All RAM elementsBRAMS_PORTA All Port A Dual Block RAM elementsBRAMS_PORTB All Port B Dual Block RAM elementsHSIOS All High Speed I/O elements (RocketI/O)CPUS All PowerPC elementsMULTS All Multiplier elements

Keywords can be used globally, and to create design sub-groups


User created groupsCombinations of existing groupsGroups by pattern matching on net namesGroups by hierarchy

Use the TNM/TNM_NET attribute to create User DefinedGroupsAll elements tagged with the same TNM/TNM_NET nameare considered a group


[NET|INST|PIN] object_name TNM = predefined_group identifier ;

object_name is the name of the element or signal to be grouped

predefined_group is an optional keyword

identifier can be any combination of letters, number, or underscoresDo not use reserved words such as FFS, LATCHES, RAMS...

This variable is case sensitive (TNM=abc

TNM=ABC)

TNM can be applied to any net, element pin, primitive or macroPronounced Tee-Name


NET clock TNM=clk_group;

Any Keyword element can be made into a group for timingpurposesIn this example the net clock is traced forward to the two flip-flops(FFS).These flip-flops are timing-named (TNM) with the nameclk_group .clk_group can now be referenced by this TNM in TIMESPECs

OUT1

QD QD

CLOCK

OUT2


NET clock TNM=clk_group;

These timing groups can overlap, meaning a FFS, LATCHES,etc. can belong to multiple groups if necessary to describe yourdesign s timing

Time constraints are case sensitive (TNM=abc

TNM=ABC)Groups are ideal for identifying groups of logic that work atdifferent speeds .(multi-cycle paths and other slowexceptions).


NET MYDATA TNM=DATA_GRP;The two RAMS and Flip Flop are include inthe DATA_GRP group

NET MYDATA TNM=RAMS FI_CORE;Only the two RAMS are included in theFI_CORE group because of the predefinedgroup: RAMS

MYDATA


NET clock TNM_NET=clk_group;

TNM_NET is equivalent to TNM on a net except

for pad nets.If you place a TNM on a pad net, it will trace backwards to the padand not trace forward through the buffer to the next synchronouselement. TNM_NET was created for this purpose.If you place a TNM_NET on a pad net, it will trace through thebuffer to the next synchronous element.TNM_NET is extremely useful for synthesis designs. The ports aredirectly connected to pads.TNM_NET can be used in UCF or NCF only.


NET PADCLK TNM = PADGROUP;will contain the IPAD symbol only

NET INTCLK TNM = FFS FLOPGROUP;will include FF1 and FF2 into the group called FLOPGROUP

NET PADCLK TNM_NET = FFS FLOPGROUP;also includes FF1 and FF2 into the group called FLOPGROUP

FF1

FF2

PADCLK INTCLK

BUFGIPADC

C


The TNM attribute on a macro places all elements IN themacro (at all levels of hierarchy) into the same groupPaths are traced downward rather than forward along anet


INST macro1 TNM = LATCHES latchgroup;

all LATCHES in the macro called macro1 will be in agroup called latchgroup

INST mymac TNM = RAMS memories;

all RAMS in the macro called mymac will be in agroup called memories

INST tester TNM = coverall;

PADS, LATCHES, RAMS, and FFS will be in a groupcalled coverall;


Each element may belong to more than one groupGroups elements of one group without the elements that belongto another groupSyntax:

TIMEGRP group1 = existing_grpA EXCEPT existing_grpB ;

group1 is the new group being defined that includesexisting_grpA minus common elements between existing_grpAand exisiting_grpBexisiting_grpA and existing_grpB can be any valid TNM,predefined group, or TIMEGRP attribute


TIMEGRP newgrp_name = existing_grp1 existing_grp2 [existing_grp3 . . . ] ;

newgrp_name is a unique new group nameexisting_grp are existing groups

Includes predefined groups, groups created with TNMs or the TIMEGRPattribute.Names of the existing groups must match the existing group namesexactly (ie case sensitive).Order in the existing_grp list is not important


Combining Groups:TIMEGRP manyffs = ffs1 ffs2 ffs3 ;

TIMEGRP biggergroup=smallgroup1 mediumgroup2;

Grouping by exclusion (EXCEPT):TIMEGRP group1= group2 group3 EXCEPT group4 group5;

TIMEGRP selective= setB setC setD setE EXCEPT setA;

TIMEGRP some_types= type2 EXCEPT type1 type2 type3;


The (*) and (?) wildcard characters can be used to selectelementsThe (*) specifies an unlimited number of charactersThe (?) specifies a single characterExample:

*DATA? : means any name that begins with any number ofcharacters, followed by DATA and ends with a single character.Includes: Does NOT include:

MYWRONGDATA1 BAD_DATA_56

MYDATA4 MYDATASYSBASEDATAB HIDATABASE9


Higher Priority then PERIOD and OFFSET constraintsPull a paths out of lower priority constraintsGive a tighter constraint to a specific pathIt s used to constraint the following types of paths:

False PathsMulti-cycle path

Source flop and destination flop have the same clock but therequirement is different then the period constraint.

Cross clock domain pathsSource and destination flops have different clocks.


The FROM:TO constraint covers paths between groups takingclock skew into account.


BUFG

CLKA

ADATA

OUT2

OUT1Q

FLOP3

DQ

FLOP1

D

Q

FLOP5

DQ

FLOP4

DBUS [7..0]

CDATA

Q

FLOP2

D

BUFG



TIMESPEC TS_F2F=FROM FFS TO FFS 30;

The word TIMESPEC defines the type of specificationThe Spec s name must start with TS any alpha-numeric after TSis fine. Recommendation: Make the name something you willremember later.FROM --designates the origin group of the pathTO --designates the destination group of the path30; in ns by default, is the specification. You can use MHz, oreven another time spec like TS_C2S/2 or TS_C2S*2 to relate thetiming constraints


Clock skew is used in FROM-TO constraintsClock skew = (destination clock delay - source clock delay)Positive clock skew is truncated to 0 in the timing report forsetup paths

Positive clock skew is used in hold time calculations

TRACE/Timing Analyzer will automatically account for clockskew on all clocks


UCF TIMESPEC command using default keywords:TIMESPEC TS_C2S=FROM FFS TO FFS 30;

TIMESPEC TS_P2S=FROM PADS TO FFS 25;

TIMESPEC TS_P2P=FROM PADS TO PADS 26;

TIMESPEC TS_C2P=FROM FFS TO PADS 9;

TS_C2P

TS_C2S TS_P2S

TS_P2P

OUT1QD QD

CLK

OUT2


Purely combinatorial delay paths start and end at I/O pads andare often left unconstrained by usersPlacing a FROM:TO constraint on pads-to-pads is necessary ifthere is a timing requirement

TIMESPEC TS_P2P = FROM PADS TO PADS 15 ns;


BUFG

CLKA

ADATA

OUT2

OUT1Q

FLOP3

DQ

FLOP1

D

Q

FLOP5

DQ

FLOP4

DBUS [7..0]

CDATA

Q

FLOP2

D

BUFG



Slack equation

Source and Destinationelements are PADS

Data Path Delay


Use register s output net names to create groups.TIMESPEC TS_MYBUS =FROM FFS(DATA0<*>) TO FFS(MY_REG*) TS_CLK*2;

DATA0(3:0)

TS_MYBUS

CNT16

QD

QD

QD

QD

MY_REG_0

MY_REG_1

MY_REG_2

MY_REG_3

reg0

reg1

reg2

reg3


Use the symbol/instance name (INST) to create groups.INST CNT16/* TNM=CNT25;

INST reg* TNM=MYREG;

TIMESPEC TS_MYBUS= FROM CNT25 TO MYREG TS_CLK*2;

DATA0

TS_MYBUS

CNT16 QD

QD

QD

QD

MY_REG_0

MY_REG_1

MY_REG_2

MY_REG_3

reg0

reg1

reg2

reg3


Slow Exceptions are FROM-TOs that define a different delay forportion of the design. The majority of the design uses PERIOD.Preferred methodology --PAR and TRCE will execute faster.

IN

CLK

OUT

30 ns

D Q D Q D Q

60 ns

IN

CLK

OUT

30 ns

D Q D Q D Q

60 ns

Example 1: Using FROM-TO s only -- Not recommended method

Example 2: Using PERIOD with a FROM-TO Slow Exception -- BEST

FROM flop1 TO flop2 30 FROM flop2 TO flop3 60

FROM flop2 TO flop3 60NET CLK PERIOD=30


Forward trace on the clock enable to create a slow exceptionNET CLK_EN TNM = SLOW;NET CLK TNM = FAST;TIMESPEC TS01=PERIOD FAST 30;TIMESPEC TS02=FROM SLOW TO SLOW TS01*2;

TNM=FAST TNM=FASTTNM=SLOW

TNM=FASTTNM=SLOW

Timespecs applying to elements with more than one TNM will be resolved witha priority system .discussed later.

IN

CLK

CLK_EN

OUT

30 ns

D Q D Q

CE

D Q

CE

60 ns

TS02


Constrains the path through specific logic.The TPTHRU attribute is attached to net/instance/macroNET $3M17/ON_THE_WAY TPTHRU = ABC;

TIMESPEC TS_FIFOS=FROM RAMS(FIFORAM<*>) THRU ABC TOFFS(MY_REG*) 25;

FIFORAM

MYFIFO

QD

QD

QD

MY_REG_0

MY_REG_1

MY_REG_2

reg0

reg1

reg2

TPTHRU=abc


You can create subgroups based on names with EXCEPTkeywordExample: (Assume this design has several data busses that all start withDATA . Use the EXCEPT command to create a group with all the pads except

the data pads.)

TIMEGROUP CTRL_PADS = PADS EXCEPT (DATA*);

TIMEGROUP DATAPINS = PADS(DATA*);

TIMESPEC TS_IO1=FROM CTRL_PADS TO FFS 20;

TIMESPEC TS_IO2=FROM FFS TO CTRL_PADS 20;

TIMESPEC TS_IO3=FROM CTRL_PADS TO CTRL_PADS 30;

TIMESPEC TS_IODATA=FROM DATAPINS TO FFS 15;


Define groups with RISING and FALLING keywordsTIMEGRP RFFS = RISING FFS;TIMEGRP FFFS = FALLING FFS;

Define timing constraintsTIMESPEC TS_R2F=FROM RFFS TO FFFS 30;

Remember, the PERIOD constraint will automatically account for two-phase clocks.

QD QD


Allows definition of non-synchronous points into synchronouspoints for multi-cycle constraints and timing analysis.

Commonly used with three-state buffers.Example: NET $3M17/BLUE TPSYNC = BLUE_S ; TIMESPEC TS_1A=FROM FFS TO BLUE_S 15 ;

comb_b

RAM/FFS/PADS/LATCH

QD

TS_1A

$3M17/BLUE


Allows the definition of non-synchronous elements asthrough points in a multi-cycle constraint

Commonly used in designs with bi-directional bus with sets ofregisters in different blocks.

NET DATA_BUS<*> TPTHRU = DATABUS;

TIMESPEC TS_TIG=FROM FFS THRU DATABUS TOFFS 23;

DATA_BUS(7:0)

ControlRegister

StatusRegisters

Control_Enable Status_Enable


Slack equation

Requirement istwice TS_clk(10ns)

Data Path Delay


Define clock groupsNET CLK_A TNM=A_GRP;

NET CLK_B TNM=B_GRP;

Define timing constraints (Recommended Way)TIMESPEC TS_CLKA=PERIOD A_GRP 20;

TIMESPEC TS_CLKB=PERIOD B_GRP TS_CLKA*2;

OrTIMESPEC TS_CLKA=PERIOD A_GRP 20;

TIMESPEC TS_CLKB=PERIOD B_GRP 20;

TIMESPEC TS_CLKA2B=FROM A_GRP TO B_GRP 20;

OUT1

QD

CLK_A

CLK_B

D

QD

QDQ


CLKDV/CLKFX frequencies can be unrelated to the inputclock, even when Translate relates themIf there are paths between the two unrelated clockdomains, they should be TIGed.

NET CLK_0 TNM = CLK0_GRP;NET CLK_FX TNM = CLKFX_GRP;

TS_TIG0 = TIMESPEC FROM CLK0_GRP TO CLKFX_GRP TIG;TS_TIG1 = TIMESPEC FROM CLKFX_GRP TO CLK0_GRP TIG;

QD

CLK_0

DATAQD

CLK_FX

UNRELATED


Create PeriodNET CLK MAXSKEW = 2ns;

NET CLK TNM = CLK_GRP;TIMESPEC "TS_CLK" = PERIOD CLK_GRP" 5 ns HIGH 50%;

Create GroupsINST DATA_OUT[*] TNM = DATA_OUT;

Create FROM-TO constraintTIMESPEC TS_DDR_OUT = FROM CLK_GRP TO DATA_OUT 1.25;

CLK

0 2.5 5

DATA_OUT

1.25ns 3.75ns CLK

QD DATA_HI

QD

DATA_LO

DATA_OUT


The TIG constraint removes any constraints frombeing applied to the specified pathPaths can be specified between groups

Shows up in timing report

Nets can be specifiedDoes not show up in timing report

Example:

TIMESPEC TS_IGNORE = FROM GROUP1 TO GROUP2 TIG ;

NET SLOW_NET TIG;


{NET|PIN|INST} name TIG = group1 [ group2

];

name is the element, net, or instance name that is to be ignoredgroup_name is an option field which ignores the net, instance, or pin inthe listed group.All paths that fan forward from the net or instance will not have anytiming constraints applied to them

The paths will be treated as if they don t exist


Ignore a signal of the designNET CHIP_MODE TIG;

Ignore a signal from a specific timespecNET SLOW_SIG TIG=TS_01;

Ignore false paths between synchronous elementsTIMESPEC TS_TIG1=FROM FFS(REGA*) TO FFS(REGB*) TIG;

Note: May have to use TNM or TNM_NET to create groups.


Signal Skew may be constrained using the MAXSKEWconstraint

NET $1I3245/$SIG_6 MAXSKEW=3;I.e. specifies a maximum of 3ns difference between thesource of net $1I3245/$SIG_6 and all its destinations ispermissible

May use to control skew of logic driven clocks (or any clockusing non-global resources)Cannot constrain skew of global nets (Makes no sense asskew is fixed)


Instead of the MAXSKEW constraint, there a clock skewconstraint: USELOWSKEWLINES- NET $1I3245/$SIG_6 USELOWSKEWLINES;USELOWSKEWLINES will force PAR to place a net on thelow-skew routing lines in the Virtex/Virtex-E/II/IIP/Spartan-IIarchitectureIf the net drives only clock loads, it will force PAR to place anet on unused BUFG resources


It is legal to constrain the same paths more than onceKnown as a constraint conflictMultiple sources constraining the same pathMultiple constraints on one net within one source

Resolution of conflicting constraints from multiple sources:Lowest Priority - input netlist or .ncf file

- .ucf fileHighest Priority - .pcf file (usually from MAP)

Note: this priority only applies to timespecs with identical TSidentfiers (e.g.TS_03 = )

You can explicitly assign priorities within same constraint typeSyntax

(SOME_NORMAL_TIMESPEC) PRIORITY integerLow numbers specify high priority (1 to 2 million)


When two constraints constrain the same path, the path willbe analyzed by the constraint with higher precedenceTIMESPEC "TS_clk" = PERIOD "clk" 7 ns;

TIMESPEC "TS_TIG" = FROM "neta_grp" TO FFS TIG;

A FROM-TO has a higher precedence than a PERIODconstraint

Two identical constraint typesConstraint later in .PCF takes all paths


Within a particular source:Highest Priority Timing ignores (TIG)

FROM-THRU-TO specs Source and destination defined by user Source or destination defined by user Source and destination are pre-defined groups

FROM-TO specs Source and destination defined by user Source or destination defined by user Source and destination are pre-defined groups

OFFSET specs Specific data IOB Time group of data IOBs All data IOBs

Lowest Priority PERIOD specs


OFFSETsglobal

OFFSET = in 5 ns before clk;

specificTIMEGRP my_pads OFFSET = in 5 ns before clk;

PERIODWith DCM

TIMESPEC TS_myperiod = PERIOD clk_grp 5 ns HIGH 50%;

Without DCM (relate clocks)TIMESPEC TS_myperiod = PERIOD clk_grp 5 ns HIGH 50%;TIMESPEC TS_my2period = PERIOD clk_grp TS_myperiod*1 HIGH50%;

FROM:TOTIMESPEC TS_myperiod = FROM grp1 to grp2 TIG;


The tools will allow the user to prorate timing delaycharacteristics based on known environmentalparameters. This is available only in the Virtex family.Voltage: Allows the user to specify the operatingvoltage.UCF syntax: VOLTAGE = value [units]

Temperature: Allows the user to specify the operatingtemperature.UCF syntax: TEMPERATURE = value [C|F|K] Celsius

is the default.

Using LOC, BLKNM, andother physical constraints


LOC constraint used to locate/assign pins:From a Schematic attach the attribute LOC=P12 to the pinsyou wish to lock downI/O constraint based on net name in the .UCF fileNET IOBLOCK/DATA0_IN LOC=P12;

I/O constraint based on the instance name in the .UCF fileINST IOBLOCK/DATA_IN_PAD LOC=P12;

PAR produces a .PAD file. The .PAD file can be used to verify theassigned pins.Constraints Editor, Pin-out Area Constraints Editor (PACE), andFloorplanner can be used to locate/assign pins.


LOC constraint used to locate:BUFTs, FFs, MAPs, CLBs, PADs, WANDs,decoders, global buffersingle components (e.g. CLBs)INST U45 LOC=CLB_R1C5;

ranges of components (but not IOs)INST U46 LOC=CLB_R2C2:CLB_R4C6;

multiple sites for single componentINST U50 LOC=CLB_R1C1, CLB_R2C1;

I/O constraint based on net nameNET IOBLOCK/DATA0_IN LOC=P12;


Area groups are used to specify a group of logical blocks that arepacked into separate physical areas by the mapper- INST <logical_block> AREA_GROUP = <group_name>;

For the 4KX architecture, TBUFs and CLBs are supported in anarea group.For Virtex E/II/IIP/Spartan-II architecture, both TBUFs and SLICESare supported.If the AREA_GROUP is attached to a hierarchical block, all logicalblocks within that block are assigned to the group.If a symbol contains a LOC and is part of an area group, the LOCconstraint will take priority and the symbol will be removed fromthe area group.Timegrps can be used to create area groups, more detail to follow


After defining the area group, the range of the group, and compression of thegroup into a percentage of the total CLBs can be defined- AREA_GROUP <group_name> RANGE = <range>;- AREA_GROUP <group_name> COMPRESSION = <percent>;

- The <range> defines the physical area for the area group.- If the logic in the group exceeds the range, map will error.- The <percent> defines the percentage of CLBs within the particular <range>to compress the logic of the area group into.Area groups with a compression factor are not affected by the -c option in mapArea groups without a compression factor are affected by the -c option in map


INST state_machine_X AREA_GROUP=group1;

AREA_GROUP group1 RANGE=CLB_R1C1:CLB_R10C10;

AREA_GROUP group1 RANGE=TBUF_R1C0:TBUF_R10C10;

AREA_GROUP group1 COMPRESSION=0;

- Assign all logical blocks in state_machine_X to the area group group1

- Place CLB logic in the physical area between CLB 1,1 and CLB 10, 10- Place TBUFs in the physical area between TBUF 1,0 and TBUF 10, 10- Do not compress unrelated logic within this area group. Note that sincecompression is defined, ungrouped logic will not be combined with logic ingroup1


a variety of mechanisms for defining and manipulating themembers of timing groups for the definition of area groups.TIMEGRP timing-group-name AREA_GROUP = area-group-name ;

Where timing-group-name is the name of a previously-definedtiming groupWhere area-group-name is the name of a new area group to bedefined from the timing group contents.

During NGDBUILD, the area group definition will beexpanded into explicit AREA_GROUP properties on allmembers of the named timing group. It can be referencedin RANGE and other constraints in the usual fashion.


PROHIBIT Disallows the use of these sites within PAR:CLBs, PADs, BUFTs, decoders, global buffer, functionblocks/macrocellssingle components (e.g. CLBs)CONFIG PROHIBIT=CLB_R1C5;

ranges of components (but not IOs)CONFIG PROHIBIT=CLB_R2C2:CLB_R4C6;

I/O constraint based on net nameCONFIG PROHIBIT=P12;

Note: CONFIG PROHIBIT has specific limits depending upon the device.Please reference the Libraries Guide for these limits.


Force logic into the same CLB/SLICE.Sometimes MAP doesn t make the best decisions. This allowsthe user to map logic together.

SyntaxINST state_reg_1 BLKNM=STATE1;INST state_reg_2 BLKNM=STATE1;INST my_logic BLKNM=STATE1;

This will force my_logic, state_reg_1, state_reg_2, and into thesame CLB/SLICE ( STATE1 ).

Note: The remaining resources are still up for grabs by MAP (in this case, oneof the FG s is still available).


Physical implementation may be controlled in the UCF file, such as:FAST : Set Faster IO Slew rate

e.g. INST $1I87/OBUF FAST

PART : Define Part-type to be usede.g. CONFIG PART=4005E-PQ160C-5;

BUFG : Force signal to onto global net (CPLD only)e.g. INST clkgen/fastclk BUFG;

INIT : Define initial RAM/ROM Contents (primitives only)e.g. INST $1I3245/ROM2 INIT = 5555;

Such Physical constraints may be Architecture dependent


fastpaths optionBreaks up the timing report into sections forsetup and hold for all constraintsAllows user look at data paths to see whichpaths almost had a hold violation

Offset VALID keywordAllows user to specify the duration of the datawindow

Clock Uncertainty


VALID specifies the duration of the incoming datawindowIf not specified, it defaults to the OFFEST timeValid must be specified for hold checkingVALID must be larger or equal to the offset timeExample:

OFFSET = IN 5 ns VALID 9 ns BEFORE ClkExt


Clock uncertainty used to increase timing accuracy byaccounting for system and board level clock jitterIncludes:

Clock input jitter (New PERIOD Constraint Keyword)System Jitter (New Constraint)DCM Jitter (Automatically calculated for Whitney and beyond)DCM Phase Error (Automatically calculated for Whitney andbeyond)

Used in internal reg/reg and external setup/hold calculationsUncertainty reported for each path covered by OFFSETconstraintUncertainty reported even if value is zeroUncertainty components are not reported separately


Constraint Example:TIMESPEC "TS_SysClk" = PERIOD "SysClk" 20 ns HIGH 50 % INPUT_JITTER 100ps;

What s wrong with this report ? Nothing !Clock Uncertainty = 0.071ns but specified as 100 ps INPUT_JITTERRegister to register clock uncertainty is a complex equation of jittercomponents


UCF Constraint Example:System_Jitter = 150 ps;

What s wrong with this report ? Nothing !Clock Uncertainty reported as 0.075 ns, Jitter was specified as 150psI/O clock uncertainty is also a complex equation of jitter components


Most generic timing constraints for fastest PARruntimeNET CLK1 PERIOD = 40;

OFFSET = OUT 13 AFTER CLK1;

TIMESPEC TS01 = FROM PADS TO PADS 40;


ClocksNET CLK TNM=CLK;

NET CLK2 TNM=CLK2;

TIMESPEC TS_CLK01=PERIOD CLK 40;

TIMESPEC TS_CLK02=PERIOD CLK2 TS_CLK01*1.25;

Ignore paths between 2 async clocksTIMESPEC TS_TIG1=FROM CLK TO CLK2 TIG;

TIMESPEC TS_TIG2=FROM CLK2 TO CLK TIG;

Generic path to outputsTIMESPEC TS_IO1=FROM FFS TO PADS 20;

Two cycle path to slow outputsTIMESPEC TS_IO2=FROM FFS TO PADS(SLOW*) TS_IO1*2;


Offset for late input signalNET LATE_INPUT OFFSET=IN 30 AFTER CLK;

Ignore static input signalNET CHIP_MODE TIG;

Static control registersINST CONTROL_BLOCK/CTRL_REG* TNM=CTRL_REG;

TIMESPEC TS_CLK03 = FROM CTRL_REG TO FFS=TS_CLK01*2;

Fast OBUF attached to componentINST RAM_CS FAST;

Prohibit PinsCONFIG PROHIBIT = P6;


All Constraints accessible from single constraints fileAll Xilinx features may be constrained from constraints fileFull TimeSpec support provided from Constraints fileImproved TimeSpec capability providedThe Constraints Guide has a full list of all supportedconstraints and examples of syntax athttp://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0001_1.html


Developmental System Reference Guide at:http://toolbox.xilinx.com/docsan/xilinx5/data/docs/dev/dev0001_1.html

Constraints Guide at:http://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0001_1.html

Libraries Guide at:http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0001_1.html

http://support.xilinx.com

How to Properly Constrain a DesignUsing Timing Tools


Global constraintsPeriod

Use a period constraint for your input clocks. Let ngdbuild createconstraints for clocks generated by a DCM

Relate clocks if possible

Offsets

Use specific constraintsFROM:TO

Specific paths

Multi-cycle pathsCross clock domain paths

OffsetsSpecific paths


(PERIOD)Period constraint should account for the following

System frequencyClock jitter% for other variations

PERIOD = (System frequency clock jitter - % for variation)

ReferencesSolution 13645Tech Exclusive

"Jitter" -http://support.xilinx.com/support/techxclusives/jitter-techX10.htm

Does Your Design Have Enough Slack?" -http://support.xilinx.com/support/techxclusives/slack-techX21.htm

On line presentation


(OFFSET)

OFFSET IN should account forUpstream trace delayUpstream device clock to outSystem frequency

OFFSET IN = (System frequency) (Upstream clock-to-out +Trace)

OFFSET OUT should account forDownstream trace delayDownstream device setupSystem frequency

OFFSET OUT =(System frequency) (Downstream setup +Trace)


Re-design the failing sectionAdd pipeline registersUse one-hot state machinesUse CASE statements instead of if/else trees

Change synthesis constraints to getbetter results


Designs using the DCMFollow the timing in the Source Sync Datasheet

Designs using local clockingUse PERIOD, OFFSET IN for inputs

Manually calculate hold times with pro-rated number on dataManually adjust setup times with pro-rated number on clock

Use OFFSET OUT if clock comes from an external pinUse FROM-TO on data path, MAXSKEW on clock net ifclock comes from an internal source


Designers design with Asynchronous Reset, then want toconstrain it synchronouslyBy default, the async reset timing path is turned offThere are two async reset paths

The async path through the register (Trq)The async reset recovery time (Trck/Tiorcko)

Typically, customers want the async turn off timeSetup time for FF to come out of reset (Trck)


CLK

RESET

FF OUTPUT

Trck

RESET FF INPUT VALUE

Use PCF constraint after SCHEMATIC ENDto enable any delay valueSCHEMATIC END;ENABLE=Trck;


Which clock wins?Last period constraint in the PCF

Use the PRIORITY keywordNET CLK0 TNM_NET = CLK0_GRP;TIMESPEC "TS_CLK0" = PERIOD CLK0_GRP" 10 ns;NET CLK2X TNM_NET = CLK2X_GRP;TIMESPEC "TS_CLK2X" = PERIOD CLK2X_GRP" TS_CLK0/2 PRIORITY 1;

Note: This does not work in 5.1i. It is fixed in 5.1i SP1

CLK0 = 100 Mhz

CLK2X = 200 Mhz

Frequency = ???


When all the known timing constraints are entered, do asanity checkCreate a timing report with unconstrained paths

Command line: -u n where n is the number of pathsTiming Analyzer: Select Report Unconstrained paths

Unconstrained paths are grouped by clock making it easyto see the paths


Note: This may greatly increase runtime

Paths that end at asynchronous elementclocked by clk20g aregrouped togetherregardless of clockrelationships

Period, OFFSETIN, OFFSET OUTfor clk30g


Suggestions on howto constrain a pathAvailable on allunconstrained paths


All paths are constrainedCheck for unconstrainedpaths in Timing Analyzer or trce

All paths meet timingPositive slack

Skew analysisPerform hold time checks for all logicRun -fastpaths to see which paths almost had ahold violation


Design is correctly constrained but has timing errorsWhat tools are available to help fix the errors?

Timing AnalyzerConstraints Improvement WizardCross Probing to the Floorplanner

Select the design.ncd in Timing Analyzer to start FloorplannerOr load the same design.ncd in Timing Analyzer andFloorplanner

Cross Probing to the SynthesisSee XAPP406 (http://support.xilinx.com/xapp/xapp406.pdf)

Timing Driven Pack in MAP


Generate a timing reportAnalyze -> Against Timing Constraints

Display an existing timing reportFile -> Open

Highlights failing constraints in redIs this a valid path?

Is this a valid requirement for source and destination clocks?Are Logic Levels correct or can they be reduced?

Shows timing pathsSorts timing paths

To determine unique timing failures

Sort by Source or Destination NameFiltering in or out paths of interest

Remove paths that do not matter


Shows timing paths in the FloorplannerNeed to turn on net highlighting in the Floorplanner

Edit -> Preferences -> RatnestSelect Display nets connected to selected logic

Open the design in the FloorplannerClick on Hyperlinks

in the Timing Report to highlight in theFloorplanner


Clicking on the DataPath will highlight thepath in the Floorplanner


Timing constraints directly influence packing decisions(Packing is the operation of combining LUTs, FFs, etc. to form slices)

Placer generates intermediate placement

Path slack is calculatedSlack used to determine optimized packing configurations


Non-Timing Driven Path


Typical Pack

Timing Driven Pack


User timing constraints are recommendedAuto timespec capability will be used in lieu of user generated constraints

Use timing switch on map command lineAvailable in ProjNav from map properties dialog afterenabling Advanced Property Display Level


Tradeoffs:Runtime is always negatively impacted

Can grow by over 2-3x

Memory usage increasesBe careful of trying to chase performance via command line settings.Analyze first!

Benefits:Benchmark data for typical designs shows overall 5-8%improvement in QORA few very large, very tightly packed designs show >10-15%improvement in performance


Bad PackingTwo LUTs that are packed together and nets go to different locations

Bad PlacementLogic placed far away from each other

Poor IO TimingFF in IOB to meet IO timing or in CLB to meet internal timing

High Fanout NetNet going to different places on the chip

Too many levels of logicToo much logic delay to meet timing


Most of the path in the same areawith one part in a different areaExample

A blue LUT is packed with a red LUTThe blue LUT needs to be in themiddle of the device, the red LUTneeds to be at the bottomCreates a placement problem


Use map -timing to get a better packing based on timingUse AREA GROUPS on different parts of design to preventpacking

Do not need range constraint to affect packingINST modulea AREA_GROUP = modulea;INST moduleb AREA_GROUP = moduleb;

Note: AREA_GROUP will be discussed in the Physical Constraint section


Logic is scattered throughout the designExample:

The blue LUTs are not in atight groupNet lengths are alwaysmultiple CLBs long


Use a higher PAR effort levelUse AREA GROUPS to locatedifferent parts of the design

Use PACE or the Floorplanner tocreate an AREA GROUP floorplan


The register is located inthe CLB array, not in theIOBExample:

The blue FF is in the CLBarray, not packed in the IOB


Place the FF in the IOBUse map switchmap -pr i|o|b (input, output or both)Use IOB constraintINST data_r IOB=TRUE


A single net goes to differentparts of the designExample:

The blue FF drives logic in thered logic and the green logic


Duplicate the source of the net in the source codeMake sure the new net goes to logic that is placed together


A path goes through toomany logic levelsExample

The yellow components arelocated near each other.Nets have similar lengths

How to Properly Constrain aModular Design

Using Timing Tools


Constraints to be familiar withOFFSETs

Constrain input and output paths (Pad to Register, Resister toPad)OFFSET constraints tell the tool what the external data andclock relationship is.

PERIODConstrains register to register paths

FROM:TOConstrain more specific paths like multi-cycle, cross clockdomain, and false paths.


In a typical non modular design the source anddestination of all data starts or ends at a realcomponents such as a PADs, FFs, RAMs,Multipliers .

In a Modular design the source and destination of dataentering or leaving a module can be a Pseudo sourceor a Pseudo load.

Any path that starts or ends at a Pseudo driver orPseudo load will be left unconstrained


Constrained Paths (OFFSET IN)

OFFSET INTop level OFFSET IN constraint still covers PAD-to-FLOP pathsand the clock paths in a module.The source of data has to be a PAD and not a Pseudo Driver.

FLOP FLOP

IOPAD

Clock PAD


Constrained Paths (OFFSET OUT)

OFFSET OUTTop level OFFSET OUT constraint still covers Flop-To-PAD pathsand the clock path in a moduleDestination of data has to be a PAD and not a Pseudo Load.

FLOP FLOP

Module

Clock PAD

IOPAD


Constrained Paths

OFFSETsIf the source of data entering a module is a Pseudo driver then thatinput data path will not be covered by your top level offset constraintIf the destination of data leaving a module is a Pseudo load thenthat output data path will not be covered by your top level offsetconstraint

Pseudo Driver FLOP FLOP Pseudo Load


Constrained PathsAsynchronous Paths

Top level PAD-to-PAD constraints still cover paths that start at a PAD andend at a PAD

Asynchronous Paths that start or end at a Pseudo driver or Pseudo loadwill not be constrained by the top level PAD-to-PAD constraint.

Pseudo Driver

Pseudo Driver

Pseudo Load

IOPAD IOPAD


Constrained PathsPeriod

Register-to-register paths are covered by the top level periodconstraintPseudo Driver to System flops are left unconstrainedSystem Flops to Pseudo Loads are left unconstrained

Pseudo Driver Pseudo LoadFLOPFLOP


Synchronous paths that start or stop at a PIN of amodule be constrained with an OFFSET constraint

TIMEGRP pseudo driver OFFSET = IN 5 ns after clk;

Asynchronous paths that start or stop at a PIN of amodule can be constrained with an FROM:TOconstraint.

TIMESPEC TS_asynch_path = FROM grp1 TO grp2;


To identify a specific pin on the module forreference in an OFFSET of FROM:TO constraintuse a TPSYNC constraint.

NET module_port TPSYNC = synch_point ;TIMEGRP synch_point OFFSET = IN 5n before clk

Pseudo Driver FLOP

Modular_port

Module

TYPSYNC point


OFFSET IN (Will constrain the green path)

NET IN_port TPSYNC = pseudo_in_grp ;TIMEGRP pseudo_in_grp OFFSET = IN 2 ns before clk;

OFFSET OUT (Will constrain the red path)

NET OUT_port TPSYNC = pseudo_out_grp ;TIMEGRP pseudo_out_grp

OFFSET = out 2 ns after clk;

FLOPFLOPPseudo Driver Pseudo Load

IN_port OUT_port

Module

Clock PAD


FROM:TO (will constrain the red path)

NET IN_port1

TPSYNC = asynch_in_grp ;NET IN_port2 TPSYNC = asynch_in_grp ;

NET OUT_port TPSYNCH = asynch_out_grp;TIMESPEC TS_asynch_path = FROM asynch_in_grp TOasynch_out_grp ;

Pseudo Driver

Pseudo Driver

Pseudo Load

IN_port1

IN_port2

OUT_port

Module


Launch Constraints Editor (CE) and load theactive module ngd and ucf file.CE will show all the port of the active modulein the ports tab

Ports on the module that are connect to PADswithin the module will have a pin location thatwas defined in the initial budgetingPorts on the module that are connected to aPseudo driver or a Pseudo load will be markedas N/A in the location column.


Other information for Constraints


. 1) create_clock -period 125 -waveform {0 62.5} find(port,"CLK") 2) set_input_delay 125 -clock "CLK" find(port,"NOTRST")

3) set_output_delay 125 -clock "CLK" find(port,"GAG<0>")

1) TIMESPEC TS_CLK = PERIOD : "CLK": 125 : HIGH : 62.5; 2) NET "CLK" TNM = "CLK"; 3) NET "NOTRST" OFFSET = IN : 125 : AFTER : "CLK"; 4) NET "GAG<0>" OFFSET = OUT : 125 : BEFORE : "CLK";

.dc file

.ncf file

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6.xi constraints 1762

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