7/10/2007dsd,usit,ggsipu1 basic concept of sequential design

7/10/2007 DSD,USIT,GGSIPU 1

Basic concept of Sequential Design


Sequential code

• Code written within the following statements execute sequentially.

• Process

• Functions

• Procedures


Process

• A process is a sequential section of VHDL code.• It is characterized by the presence of following

statements:• If Statements• Case Statements• Null Statements• Loop Statements

– Exit Statements– Next Statements– While loops– For loops


Process (cont..)

• A Process must be installed in the main code, and is executed every time a signal in the sensitivity list changes (or the condition related to WAIT is fulfilled).

• Syntax:[label:] Process (sensitivity list)

[variable name type [range] [:=initial value;]]Begin

(sequential code)End Process [label];


Process Statements Label: process (sensitivity_signal_list)

-- constant_declaration

-- variable_declaration

--Subprogram declaration

-- signal declaration are not permitted here

Begin

--Sequential statements

End process LABEL;


• Used in architectures

• Every process statement within an architecture is executed once at the beginning of simulation, and thereafter, only when a signal in its sensitivity list changes value (I.e., when there is an event on one or more of the signal in the sensitivity list).

• The statements within processes must be sequential statements.


• Variables declared within processes are static. They are initialized only once at the beginning of simulation and retain their values between process activations.

• The other form of process statements as no sensitivity list.


If StatementsIf_statement <= [if_label:]

if Boolean_expression then{sequential statement}

elsif Boolean_expression then{sequential statement}

else{sequential statement}

end if [if_label];


Caution for using if…..else statement

• Avoid using more than three levels of if…else……end if statements.

• If more than three levels are required, encapsulate the inner nested levels with procedure calls.

• Indent each level of if statement.• When defining the condition, use parentheses

levels of operations on the condition. Group the operations in a logical and readable order.


Single bit comparator

Single bit comparator

A(1)

A(0)

gr: a(1) >a(0)

sm: a(1) <a(0)

eq: a(1)=a(0)


Truth table

A(1) A(0) Gr Sm Eq

0 0 0 0 1

0 1 0 1 0

1 0 1 0 0

1 1 0 0 1


Boolean equation

• Gr <= a(1) and (not a(0))

• Le <= a


VHDL Code• entity singlebitcomparator is• Port ( a : in std_logic_vector(1 downto 0);

en: in std_logic;

• gt : out std_logic;• sm : out std_logic;• eq : out std_logic);• end singlebitcomparator;

• architecture Behavioral of singlebitcomparator is• begin• process (en,a)• begin• if (a(1)>a(0)) then• gt <= '1'; sm <= '0'; eq <= '0';• elsif (a(1) < a(0)) then• gt <= '0'; sm <= '1'; eq <= '0';• else• gt <= '0'; sm <= '0'; eq <= '1';• end if;• end process;• end Behavioral;


Waveform of single bit comparator


4-bit comparator

4-bit comparator

1-bit comp

1-bit comp

1-bit comp

1-bit comp

A

B


Boolean equation for 4-bit comparator

• Let A=a3a2a1a0

• Let B=b3b2b1b0

• Intermediate signal : i3,i2,i1 and i0

• AeqB= i3i2i1i0• AgtB = a3(b3bar)+i3a2(b2bar)+i3i2a1(b1bar)+i3i2i1a0(b0bar)

• AltB = Not(AeqB+AgtB)


VHDL code of 4-bit comp• entity comp4bit is

• Port ( x : in std_logic_vector(3 downto 0);

• y : in std_logic_vector(3 downto 0);

• en: in std_logic;

• greater : out std_logic;

• smaller : out std_logic;

• equal : out std_logic);

• end comp4bit;

• architecture Behavioral of comp4bit is

• component singlebitcomparator is

• Port ( a : in std_logic_vector(1 downto 0);

• en: in std_logic;

• gt : out std_logic;

• sm : out std_logic;

• eq : out std_logic);

• end component singlebitcomparator;

• signal temp : std_logic_vector(10 downto 0);


• begin

• u1: singlebitcomparator port map(a(1)=>x(3),a(0)=>y(3),en=>en,gt=>temp(0),sm=>temp(1),eq=>temp(2));

• u2: singlebitcomparator port map(a(1)=>x(2),a(0)=>y(2),en=>temp(2),gt=>temp(3),sm=>temp(4),eq=>temp(5));

• u3: singlebitcomparator port map(a(1)=>x(1),a(0)=>y(1),en=>temp(5),gt=>temp(6),sm=>temp(7),eq=>temp(8));

• u4: singlebitcomparator port map(a(1)=>x(0),a(0)=>y(0),en=>temp(8),gt=>temp(9),sm=>temp(10),eq=>equal);

• greater <= temp(0) or temp(3) or temp(6) or temp(9);

• smaller <= temp(1) or temp(4) or temp(7) or temp(10);

• end Behavioral;


Waveform of 4-bit comparator


4x1 Multiplexerlibrary ieee;use ieee.std_logic_1164.all;

entity mux4_1_if isport (a: in std_logic_vector(3 downto 0);s: in std_logic_vector(1 downto 0);y: out std_logic);end mux4_1_if;

architecture mux_behave of mux4_1_if isbeginprocess (s)beginif s = "00" theny <= a(0);elsif s = "01" theny <= a(1);elsif s = "10" theny <= a(2);else y <= a(3);end if;end process;end mux_behave;


Case statements

A case statement selects for execution one of a number of alternative sequences of statements.

The syntax for a case statement is as follows :case expression is

when value => assignments;when value => assignments;

end case;


Rule for the Case statement

• The case expression must be discrete type.• Every possible value of the case expression must

be covered in one and only one when clause (I.e cannot duplicate a value in another “when” clause).

• If the when others clause is used, it must appear as a single choice at the end of the case statement.

• NULL may be used, when no action is required to take place.e.g. When OTHERS => NULL;


• Case choice must be a locally static expression.

• Array case expression must have a static subtype. Thus, the type of the case expression must not be based on generics.

Rule for the Case statement….


Tips for programming using CASE

• Choices in a case statement should be separated by one blank line and should be indented.

• The sequence of statements should be immediately follow the case alternative specification and be indented by at least two spaces.

• Keep the expression for the case statement SIMPLE.


Example 4:1 Mux using Case statement

library ieee;use ieee.std_logic_1164.all;

entity mux4_1_case isport (a: in std_logic_vector(3 downto 0);s: in std_logic_vector(1 downto 0);y: out std_logic);end mux4_1_case;

architecture mux_behave of mux4_1_case isbeginprocess (s)begincase s iswhen "00" => y<=a(0);when "01" => y <= a(1);when "10" => y <= a(2);when others => y <= a(3);end case;end process;end mux_behave;


Comparing “if” and “case” statements

• “if” statement produces priority-encoded logic

• “case” statement produces parallel logic• Corresponds to “with---select” in

concurrent statements.• “case” statement does not result in

prioritized logic structure unlike the if statement.


Loop

• Loop statement are used to execute a sequence of statements zero or more times.

• Loop is intended exclusively for sequential code.• For/loop : The loop is repeated a fixed number

of times.[label:] FOR identifier IN range LOOP

(sequential statements)

END LOOP [label];


Loop Statement

• Three forms of loop statements:– The simple loop– The while loop– The for loopLoop_statement::=[loop_label:][iteration_scheme] loop

sequence_of_statementsEnd loop [loop_label];


The Simple Loop

• The simple loop does not have an explicit iteration scheme.

• The implicit iteration scheme is while true, thus looping forever.

• The usual way to exit an infinite loop is to use the exit statement.

• The simple loop is not synthesizable.


The while loop

• The while loop iterates as long as the condition expressed in the while statement is true.

• This is often used to execute a set of sequential statements while a signal or a variable meets a certain criteria.

• The while loop is not synthesizable.


The for loop

• The loop parameter type for the for iteration loop scheme is the base type of the discrete range, and is not explicitly defined as a type. The type is implicitly defined from the range.

• Syntax:

[label:] FOR identifier IN range LOOP(sequential statements)

END LOOP [label];


1. The loop parameter is not explicitly defined, but implicitly defined.

2. The loop parameter’s range is tested at the beginning of the loop, not at the end.

3. The loop parameter is an object whose type is the base type of the discrete range.

4. Inside the loop, the loop parameter is a constant. Thus, it may be used but not altered.


5. The loop parameter’s discrete range may be dynamic.

6. The discrete range of the loop is evaluated before the loop is first executed.

7. The loop counter only exists within the loop

Rules of for loop(cont..)


Example of For/loop

FOR I in 0 to 5 loop

x (i) <= enable AND w(i+2);

y(0,i) <= w(i);

End LOOP;

NOTE: Range must be static.


Loop (cont.)

• WHILE/LOOP : The loop is repeated until a condition no longer holds.

[label:] WHILE condition LOOP

(sequential statements);

end LOOP [label];


• Example WHILE/LoopWhile (I <10) Loop

wait until clk’event and clk=‘1’;

(other statement)

End loop;


Exit Statement Exit statement:is a sequential statement that can be

used only inside a loop Syntax:

exit [loop-label] [when condition];Example:

SUM:= 1; J := 0; L3: loop J:= J + 21; SUM := SUM * 10;

if SUM > 100 then exit L3;--only exit is also possible --if no loop label is specified, the innermost loop is exited

end if; end loop L3;


Next Statement Next Statement: skipping the remaining statements

in the current iteration of the specified loop; - execution resumes with the first statement in the

next iteration of this loop, if one exists- can be used only inside a loop - sequential statement - if no loop label is specified, the innermost loop is

assumed Syntax

next [loop-label] [When condition];


Next Statement (Example-1)

Next statement can also cause an inner loop to be exited example:

L4: for K in10 downto1 loop…….

L5:loop ………. next L4 when WR_Done := ‘1’;

………… end loop L5;……..

end loop L4;


Example (exit and Next)

For I in data’range loop

case data(I) is

when ‘0’ => count:= count +1;

when others => exit;

end case;

End loop;


Example (next)

For I in 0 to 15 loop

next when I= skip; -- jump to next iteration

7/10/2007dsd,usit,ggsipu1 basic concept of sequential design

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