7/23 coldfire 5211 signals and io multiplexing computer science & engineering department arizona...

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7/23 Coldfire 5211 Signals and IO Multiplexing Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee [email protected] (480) 727-7507

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Page 1: 7/23 Coldfire 5211 Signals and IO Multiplexing Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee yhlee@asu.edu

7/23

Coldfire 5211 Signals and IO Multiplexing

Computer Science & Engineering DepartmentArizona State University

Tempe, AZ 85287

Dr. Yann-Hang [email protected](480) 727-7507

Page 2: 7/23 Coldfire 5211 Signals and IO Multiplexing Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee yhlee@asu.edu

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Coldfire 5211 Processor

64-pin LQFP (Low Profile Quad Flat Pack packages )

81-ball MAPBGA (Multi-array Plastic Ball Grid Array)

16Kb SRAM 128Kb flash

Page 3: 7/23 Coldfire 5211 Signals and IO Multiplexing Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee yhlee@asu.edu

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5211 64-pin Package

There are many I/O functions to connect to external signals and the number of pins in a chip is limited

Multiplex multiple I/O functions to one pin primary function, alternate functions, general-purpose I/O

Pin function is set by the operating mode Pin layout shows primary functions

Page 4: 7/23 Coldfire 5211 Signals and IO Multiplexing Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee yhlee@asu.edu

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Coldfire GPIO

I/O pins are grouped into 8-bit ports. Some ports do not use all 8 bits. Each port has registers that configure, monitor, and control the port pins.

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Coldfire Port Registers

Port Output Data Registers (PORTn) store the data to be driven on the corresponding port n pins when the

pins are configured for digital output. Port Data Direction Registers (DDRn)

control the direction of the port n pin drivers

pad control

pin assignment

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Coldfire Port Registers

Port Pin Data/Set Data Registers (PORTnP/SETn) reflect the current pin states and control the setting of output pins

Port Clear Output Data Registers (CLRn) Writing 0s to a CLRn register clears the corresponding bits in the

PORTn register. Pin Assignment Registers (PnPAR_)

allow each pin controlled by each register bit to be configured between the multiplexed functions

Pad Control Registers pin slew rate register pin drive strength register (10mA or 2mA)

Page 7: 7/23 Coldfire 5211 Signals and IO Multiplexing Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee yhlee@asu.edu

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Example: UART Pin Initialization

To configure the pins for UART0 and UART1 to their primary functions

#define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100059]))#define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x10005A]))#define MCF_GPIO_PUAPAR_RXD0_RXD0 (0x04)#define MCF_GPIO_PUAPAR_TXD0_TXD0 (0x01)

void mcf5211_uart_init(void) {

/* Enable the proper UART pins */MCF_GPIO_PUBPAR = 0

| MCF_GPIO_PUBPAR_RXD1_RXD1 | MCF_GPIO_PUBPAR_TXD1_TXD1;

MCF_GPIO_PUAPAR = 0 | MCF_GPIO_PUAPAR_RXD0_RXD0 | MCF_GPIO_PUAPAR_TXD0_TXD0;

/* Enable the default UART terminal port */ uart_init(sys_clk_khz, BAUD, 0);}

Page 8: 7/23 Coldfire 5211 Signals and IO Multiplexing Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee yhlee@asu.edu

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Example: LED on DTIN pins

/* Display the lower 4 bits of 'number' on the 4 LEDs connected to DTIN[3:0] * * LED: LED4 LED3 LED2 LED1 * PIN: TIN3 TIN2 TIN1 TIN0 * BIT: 3 2 1 0 */ void leds_init() {

MCF_GPIO_PTCPAR = 0 /* Enable signals as GPIO */ | MCF_GPIO_PTCPAR_TIN3_GPIO | MCF_GPIO_PTCPAR_TIN2_GPIO | MCF_GPIO_PTCPAR_TIN1_GPIO | MCF_GPIO_PTCPAR_TIN0_GPIO;

MCF_GPIO_DDRTC = 0 /* Enable signals as digital outputs */ | MCF_GPIO_DDRTC_DDRTC3 | MCF_GPIO_DDRTC_DDRTC2 | MCF_GPIO_DDRTC_DDRTC1 | MCF_GPIO_DDRTC_DDRTC0;} void leds_dsiplay (unit8 number){

MCF_GPIO_PORTTC = number; /* Set output values */}