750 mhz to 1150 mhz quadrature demodulator with fractional ... · 750 mhz to 1150 mhz quadrature...
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750 MHz to 1150 MHz Quadrature Demodulator with Fractional-N PLL and VCO
Data Sheet ADRF6801
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES IQ demodulator with integrated fractional-N PLL LO frequency range: 750 MHz to 1150 MHz Input P1dB: 12.5 dBm Input IP3: 25 dBm Noise figure (DSB): 14.3 dB Voltage conversion gain: 5.1 dB Quadrature demodulation accuracy
Phase accuracy: 0.3° Amplitude accuracy: 0.05 dB
Baseband demodulation: 275 MHz, 3 dB bandwidth SPI serial interface for PLL programming 40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS QAM/QPSK RF/IF demodulators Cellular W-CDMA/CDMA/CDMA2000 Microwave point-to-(multi)point radios Broadband wireless and WiMAX
GENERAL DESCRIPTION The ADRF6801 is a high dynamic range IQ demodulator with integrated PLL and VCO. The fractional-N PLL/synthesizer generates a frequency in the range of 3.0 GHz to 4.6 GHz. A divide-by-4 quadrature divider divides the output frequency of the VCO down to the required local oscillator (LO) frequency to drive the mixers in quadrature. Additionally, an output buffer can be enabled that generates an fVCO/2 signal for external use.
The PLL reference input is supported from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO.
The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential I and Q output paths have excellent quadrature accuracy and can handle baseband signaling or complex IF up to 120 MHz.
The ADRF6801 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is specified over the −40°C to +85°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
MUX
RSETGND
LON
LOP
MUX
TEMPSENSOR
GNDVCCBBGND
VCCLO
BUFFER
BUFFER
QBBN
VCCLO
–+ CHARGE PUMP
250µA,500µA (DEFAULT),750µA,1000µA
PRESCALER÷2
VCO LDO2.5V LDO
LECLK SPI
INTERFACE
DATA
MUXOUT
REFIN
ADRF680134
GND LOSEL35
19
QBBP18
17
16
DECL140
VTUNE39
DECL2VCC2910 5
DECL32
VCC11
8
6
GND 7
14
GND 15
13
12
38
GND 11
37
36GND
31IBBNIBBP
3233
28
VCCRF27
RFIN26
GNDRF25
GND24
GND23
VCCBB22
GND
GND
21
20
29
30
PHASEFREQUENCYDETECTOR
THIRD-ORDERFRACTIONAL
INTERPOLATOR
FRACTIONREG MODULUS INTEGER
REG
N COUNTER
GND4
CPOUT3
×2
÷2
÷4
DIVIDER÷1OR÷2
VCOCORE
0957
6-00
1
BUFFERCTRL
QUAD÷2
3.3V LDO
Figure 1.
ADRF6801 Data Sheet
Rev. A | Page 2 of 34
TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9
Synthesizer/PLL .......................................................................... 12 Complementary Cumulative Distribution Functions (CCDF) ....................................................................................................... 13
Circuit Description ......................................................................... 14 LO Quadrature Drive ................................................................. 14 V-to-I Converter ......................................................................... 14 Mixers........................................................................................... 14 Emitter Follower Buffers ........................................................... 14 Bias Circuitry .............................................................................. 14
Register Structure ....................................................................... 14 Applications Information .............................................................. 21
Basic Connections ...................................................................... 21 Supply Connections ................................................................... 21 Synthesizer Connections ........................................................... 21 I/Q Output Connections ........................................................... 22 RF Input Connections ............................................................... 22 Charge Pump/VTUNE Connections ...................................... 22 LO Select Interface ..................................................................... 22 External LO Interface ................................................................ 22 Setting the Frequency of the PLL ............................................. 22 Register Programming ............................................................... 22 EVM Measurements .................................................................. 23
Evaluation Board Layout and Thermal Grounding ................... 24 ADRF6801 Software .................................................................. 28
Characterization Setups ................................................................. 30 Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY 6/2018—Rev. 0 to Rev. A Change to Register Structure Section .......................................... 14 Changes to Register Programming Section ................................ 22 1/2011—Revision 0: Initial Version
Data Sheet ADRF6801
Rev. A | Page 3 of 34
SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25°C; fREF = 26 MHz, fLO = 900 MHz, fBB = 4.5 MHz, RLOAD = 450 Ω differential, all register and PLL settings use the recommended values shown in the Register Structure section, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RF INPUT AT 900 MHz RFIN pins
Internal LO Frequency Range With VCO amplitude = 63 (R6 [DB15 to DB10]) 750 1125 MHz With VCO amplitude = 24 (R6 [DB15 to DB10]) 750 1150 MHz Input Return Loss Measured at 900 MHz <−20 dB Input P1dB 12.5 dBm Second-Order Input Intercept (IIP2) −5 dBm each tone >65 dBm Third-Order Input Intercept (IIP3) −5 dBm each tone 25 dBm Noise Figure Double sideband from RF to either I or Q output 14.3 dB With a −10 dBm interferer 5 MHz away 18.9 dB LO-to-RF Leakage At 1×LO frequency, 50 Ω termination at the RF port −75 dBm
I/Q BASEBAND OUTPUTS IBBP, IBBN, QBBP, QBBN pins Voltage Conversion Gain 450 Ω differential load across IBBP, IBBN (or QBBP, QBBN) 5.1 dB Demodulation Bandwidth 1 V p-p signal 3 dB bandwidth 275 MHz Quadrature Phase Error 0.3 Degrees I/Q Amplitude Imbalance 0.05 dB Output DC Offset (Differential) ±5 mV Output Common-Mode Voltage VPOS − 2.4 V Gain Flatness Any 5 MHz (<100 MHz) 0.2 dB p-p Maximum Output Swing Differential 450 Ω load 4 V p-p Differential 200 Ω load 2.4 V p-p Maximum Output Current Each pin 12 mA p-p
LO INPUT/OUTPUT LOP, LON Output Level Into a differential 50 Ω load, LO buffer enabled (LO
frequency = 900 MHz, output frequency = 1800 MHz) −2.5 dBm
Input Level Externally applied 2×LO, PLL disabled 0 dBm Input Impedance Externally applied 2×LO, PLL disabled 50 Ω VCO Operating Frequency With VCO amplitude = 63 (R6 [DB15 to DB10]) 3000 4500 MHz With VCO amplitude = 24 (R6 [DB15 to DB10]) 3000 4600 MHz
SYNTHESIZER SPECIFICATIONS All synthesizer specifications measured with recommended settings provided in Figure 33 through Figure 39
Channel Spacing fPFD = 26 MHz; modulus = 2047 25 kHz PLL Bandwidth Can be adjusted with off-chip loop filter component
values and RSET 130 kHz
SPURS fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured at BB outputs with fBB = 50 MHz
Reference Spurs fREF = 26 MHz, fPFD = 26 MHz −91.6 dBc fPFD/2 −107.8 dBc fPFD × 2 −89.1 dBc fPFD × 3 −94.2 dBc
ADRF6801 Data Sheet
Rev. A | Page 4 of 34
Parameter Test Conditions/Comments Min Typ Max Unit PHASE NOISE (USING 130 kHz LOOP FILTER) fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
1 kHz offset −99.5 dBc/Hz 10 kHz offset −107.8 dBc/Hz 100 kHz offset −106.6 dBc/Hz 500 kHz offset −126.7 dBc/Hz 1 MHz offset −131.7 dBc/Hz 5 MHz offset −143.5 dBc/Hz 10 MHz offset −150.5 dBc/Hz
Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.16 °rms PHASE NOISE (USING 2.5 kHz LOOP FILTER) fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
1 kHz offset −71.3 dBc/Hz 10 kHz offset −88.3 dBc/Hz 100 kHz offset −114.1 dBc/Hz 500 kHz offset −129.5 dBc/Hz 1 MHz offset −138.6 dBc/Hz 5 MHz offset −150.2 dBc/Hz 10 MHz offset −150.3 dBc/Hz PLL FIGURE OF MERIT (FOM) Measured with fREF = 26 MHz, fPFD = 26 MHz −215.4 dBc/Hz/Hz Measured with fREF = 104 MHz, fPFD = 26 MHz −220.9 dBc/Hz/Hz
Phase Detector Frequency 20 26 40 MHz REFERENCE CHARACTERISTICS REFIN, MUXOUT pins
REFIN Input Frequency Usable range 10 160 MHz REFIN Input Capacitance 4 pF MUXOUT Output Level VOL (lock detect output selected) 0.25 V VOH (lock detect output selected) 2.7 V REFOUT Duty Cycle 50 %
CHARGE PUMP Pump Current 500 µA Output Compliance Range 1 2.8 V
LOGIC INPUTS CLK, DATA, LE pins Input High Voltage, VINH 1.4 3.3 V Input Low Voltage, VINL 0 0.7 V Input Current, IINH/IINL 0.1 µA Input Capacitance, CIN 5 pF
POWER SUPPLIES VCC1, VCC2, VCCLO, VCCBB, VCCRF pins Voltage Range (5 V) 4.75 5 5.25 V Supply Current (5 V) Normal Rx mode, internal LO 262 mA Rx mode, internal LO with LO buffer enabled 288 mA Rx mode, using external LO input (internal VCO, PLL shut
down) 157 mA
Supply Current (5 V) Power-down mode 20 mA
Data Sheet ADRF6801
Rev. A | Page 5 of 34
TIMING CHARACTERISTICS VS = 5 V, unless otherwise noted.
Table 2. Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 20 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width
Timing Diagram
CLOCK
DATA
LE
LE
DB23 (MSB) DB22 DB2 DB1(CONTROL BIT C2)
DB0 (LSB)(CONTROL BIT C1)
t1
t2 t3
t7
t6
t4 t5
0957
6-00
2
Figure 2. Timing Diagram
ADRF6801 Data Sheet
Rev. A | Page 6 of 34
ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage, VCC1, VCC2, VCCLO,
VCCBB, and VCCRF (VS1) −0.5 V to +5.5 V
Digital I/O, CLK, DATA, and LE −0.3 V to +3.6 V RFIN 16 dBm θJA (Exposed Paddle Soldered Down) 30°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
ESD CAUTION
Data Sheet ADRF6801
Rev. A | Page 7 of 34
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
THIRD-ORDERSDM
VCOBAND
CURRENTCAL/SET
VCO3000MHz
TO4600MHz
PHASE DETECTORAND
CHARGE PUMP
QUADRATURE÷2
SERIAL PORT
×2
ENABLEPROGRAMABLE
DIVIDER÷4
MUX
PRESCALER÷2
VCOLDO
2.5VLDO
MUX
INTEGERFRACTION
6
6
BLEED
SCALE
MODULUS
BUFFERCTRL
DIVCTRL
÷2
DIV÷1OR÷2
VCC1 1
DECL3 2
CPOUT 3
GND 4
RSET 5
REFIN 6
GND 7
MUXOUT 8
DECL2 9
VCC2 10
23 GND
24 GND
25 GNDRF
26 RFIN
27 VCCRF
28 GND
29 VCCBB
30 GND
22 VCCBB
21 GND
GN
D 1
1
DA
TA 1
2
CLK
13
GN
D 1
5
VCC
LO 1
7
GN
D 1
6
QB
BP
18
QB
BN
19
GN
D 2
0
LE
14
33 I
BB
P
34 V
CC
LO
35 G
ND
36 L
OSE
L
37 L
ON
38 L
OP
39 V
TUN
E
40 D
ECL1
32
IBB
N
31 G
ND
0881
7-00
3
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VCC1 The 5 V Power Supply Pin for VCO and PLL (VCC1). 2 DECL3 Decoupling Node for the 3.3 V LDO. Connect a 0.1 µF capacitor between this pin and ground. 3 CPOUT Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter. 4, 7, 11, 15, 16, 20, 21, 23, 24, 28, 30, 31, 35
GND Connect these pins to a low impedance ground plane.
ADRF6801 Data Sheet
Rev. A | Page 8 of 34
Pin No. Mnemonic Description 5 RSET Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA, 750 µA, or 1
mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally tweaked according to the following equation where the resulting value is in units of ohms.
8.374.217
−
×=
NOMINAL
CPSET I
IR
6 REFIN Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz. 8 MUXOUT Multiplexer Output. This output can be programmed to provide the reference output signal or
the lock detect signal. The output is selected by programming the appropriate register. 9 DECL2 Decoupling Node for 2.5 V LDO. Connect a 0.1 µF capacitor between this pin and ground. 10 VCC2 The 5 V power supply pin for the 2.5 V LDO. 12 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. 13 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. 14 LE Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into
one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word.
17, 34 VCCLO The 5 V Power Supply for the LO Path Blocks. 18, 19 QBBP, QBBN Demodulator Q-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω. 22, 29 VCCBB The 5 V Power Supply for the Baseband Output Section of the Demodulator Blocks. 25 GNDRF Ground Return for RF Input Balun. 26 RFIN Single-Ended, Ground Referenced 50 Ω, RF Input. 27 VCCRF The 5 V Power Supply for the RF Input Section of the Demodulator Blocks. 32, 33 IBBN, IBBP Demodulator I-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω. 36 LOSEL LO Select. Connect this pin to ground for the simplest operation and to completely control the LO
path and input/output direction from the register SPI programming. For additional control without register reprogramming, this input pin can determine whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is set low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The externally applied LO drive must be at 2×LO frequency (and the LDIV bit of Register 5 (DB5) set low). LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set high and the LXL bit of Register 5 (DB4) is set low. The output frequency is 2×LO frequency (and the LDIV bit of Register 5 (DB5) must be set high). This pin should not be left floating.
37, 38 LON, LOP Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency divided version of the internal VCO is available on these pins. When the internal LO generation is disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds to the LO path divider setting). (Differential Input/Output Impedance of 50 Ω)
39 VTUNE VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range on this pin is 1.0 V to 2.8 V.
40 DECL1 Connect a 10 µF capacitor between this pin and ground as close to the device as possible because this pin serves as the VCO supply and loop filter reference.
EP Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Data Sheet ADRF6801
Rev. A | Page 9 of 34
TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, unless otherwise noted. LO = 750 MHz to 1150 MHz.
0
2
4
6
8
10
12
14
16
750 800 850 900 950 1000 1050 1100 1150
CO
NVE
RSI
ON
GA
IN (d
B)A
ND
INPU
T P1
dB (d
Bm
)
LO FREQUENCY (MHz)
GAIN
IP1dB
TA = +85°CTA = +25°CTA = –40°C
0957
6-00
4
Figure 4. Conversion Gain and Input P1dB vs. LO Frequency
15
17
19
21
23
25
27
29
31
33
35
750 800 850 900 950 1000 1050 1100 1150
INPU
T IP
3 (d
Bm
)
LO FREQUENCY (MHz)
TA = +85°CTA = +25°CTA = –40°C
0957
6-00
5
Figure 5. Input IP3 vs. LO Frequency
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
750 800 850 900 950 1000 1050 1100 1150
IQ G
AIN
MIS
MAT
CH
(dB
)
LO FREQUENCY (MHz)
TA = +85°CTA = +25°CTA = –40°C
0957
6-00
6
Figure 6. IQ Gain Mismatch vs. LO Frequency
50
55
60
65
70
75
80
750 800 850 900 950 1000 1050 1100 1150
INPU
T IP
2 (d
Bm
)
LO FREQUENCY (MHz)
TA = +85°CTA = +25°CTA = –40°C
I CHANNELQ CHANNEL
0957
6-00
7
Figure 7. Input IP2 vs. LO Frequency
10
11
12
13
14
15
16
17
18
19
20
750 800 850 900 950 1000 1050 1100 1150
NO
ISE
FIG
UR
E (d
B)
LO FREQUENCY (MHz)
TA = +85°CTA = +25°CTA = –40°C
0957
6-00
8
Figure 8. Noise Figure vs. LO Frequency
–5
–4
–3
–2
–1
0
1
2
3
4
5
750 800 850 900 950 1000 1050 1100 1150
IQ Q
UA
DR
ATU
RE
PHA
SE E
RR
OR
(Deg
rees
)
LO FREQUENCY (MHz)
TA = +85°CTA = +25°CTA = –40°C
0957
6-00
9
Figure 9. IQ Quadrature Phase Error vs. LO Frequency
ADRF6801 Data Sheet
Rev. A | Page 10 of 34
–90
–85
–80
–75
–70
–65
–60
–55
–50
750 800 850 900 950 1000 1050 1100 1150
LO-T
O-R
F FE
EDTH
RO
UG
H (d
Bm
)
LO FREQUENCY (MHz) 0957
6-01
0Figure 10. LO-to-RF Feedthrough vs. LO Frequency, LO Output Turned Off
–75
–70
–65
–60
–55
–50
–45
–40
–35
750 800 850 900 950 1000 1050 1100 1150
LO-T
O-B
B F
EED
THR
OU
GH
(dB
V rm
s)
LO FREQUENCY (MHz) 0957
6-01
1
Figure 11. LO-to-BB Feedthrough vs. LO Frequency, LO Output Turned Off
–70
–65
–60
–55
–50
–45
–40
–35
–30
750 800 850 900 950 1000 1050 1100 1150
RF-
TO-B
B F
EED
THR
OU
GH
(dB
c)
RF FREQUENCY (MHz) 0957
6-01
2
Figure 12. RF-to-BB Feedthrough vs. RF Frequency
–7
–6
–5
–4
–3
–2
–1
0
1
1 10 100
NO
RM
ALI
ZED
BA
SEB
AN
DFR
EQU
ENC
Y R
ESPO
NSE
(dB
)
BASEBAND FREQUENCY (MHz) 0957
6-01
3
Figure 13. Normalized Baseband Frequency Response vs. Baseband Frequency
0
10
20
30
40
50
60
70
80
5 10 15 20 25 30 35 40 45 50
INPU
T P1
dB (d
Bm
), IN
PUT
IP2
(dB
m),
AN
D IN
PUT
IP3
(dB
m)
BASEBAND FREQUENCY (MHz)
IP1dB
IIP3
IIP2
TA = +85°CTA = +25°CTA = –40°C
I CHANNELQ CHANNEL
0957
6-01
4
Figure 14. Input P1dB, Input IP2, and Input IP3 vs. Baseband Frequency
10
12
14
16
18
20
22
24
26
28
30
32
34
–35 –30 –25 –20 –15 –10 –5 0 5
NO
ISE
FIG
UR
E (d
B)
INPUT BLOCKER POWER (dBm) 0957
6-01
5
Figure 15. Noise Figure vs. Input Blocker Level, fLO = 900 MHz (RF Blocker 5 MHz Offset)
Data Sheet ADRF6801
Rev. A | Page 11 of 34
–40
–35
–30
–25
–20
–15
–10
–5
0
750 800 850 900 950 1000 1050 1100 1150
RF
INPU
T R
ETU
RN
LO
SS (d
B)
RF FREQUENCY (MHz) 0957
6-01
6
Figure 16. RF Input Return Loss vs. RF Frequency
–16
–14
12
–10
–8
–6
–4
–2
0
1500 1600 1700 1800 1900 2000 2100 2200 2300
LOP,
LO
N D
IFFE
REN
TIAL
OU
TPU
T R
ETU
RN
LO
SS (d
B)
LOP, LON OUTPUT FREQUENCY (MHz) 0957
6-01
7
Figure 17. LO Output Return Loss vs. LO Output Frequency, LO Output Enabled (1500 MHz to 2300 MHz), Measured through TC1-1-13 Balun
200
220
240
260
280
300
320
340
360
380
400
750 800 850 900 950 1000 1050 1100 1150
CU
RR
ENT
(mA
)
LO FREQUENCY (MHz)
TA = +85°CTA = +25°CTA = –40°C
0957
6-01
8
Figure 18. 5 V Supply Currents vs. LO Frequency, LO Output Enabled
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
–40 –15 10 35 60 85
VPTA
T VO
LTA
GE
(V)
TEMPERATURE (°C) 0957
6-01
9
Figure 19. VPTAT vs. Temperature
0.5
1.0
1.5
2.0
2.5
3.0
3.5
750 800 850 900 950 1000 1050 1100 1150
VTU
NE
VO
LTA
GE
(V)
LO FREQUENCY (MHz)
TA = +85°CTA = +25°CTA = –40°C
0957
6-02
0
Figure 20. VTUNE vs. LO Frequency
ADRF6801 Data Sheet
Rev. A | Page 12 of 34
SYNTHESIZER/PLL VS = 5 V. See the Register Structure section for recommended settings used. External loop filter bandwidths of ~130 kHz and 2.5 kHz used (see plots within this section for annotations), fREF = fPFD = 26 MHz, measured at BB output, fBB = 50 MHz, unless otherwise noted.
–160
–140
–120
–100
–80
–60
–40
1k 10k 100k 1M 10M
PHA
SE N
OIS
E (d
Bc/
Hz)
OFFSET FREQUENCY (Hz)
2.5kHz LOOP FILTERBANDWIDTH
130kHz LOOP FILTERBANDWIDTH
TA = +85°CTA = +25°CTA = –40°C
0957
6-02
1
Figure 21. Phase Noise vs. Offset Frequency, fLO = 900 MHz, Shown for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
–110
–105
–100
–95
–90
–85
–80
–75
–70
750 800 850 900 950 1000 1050 1100 1150
PLL
REF
EREN
CE
SPU
RS
(dB
c)
LO FREQUENCY (MHz)
TA = +85°CTA = +25°CTA = –40°C
1 × PFD FREQUENCY3 × PFD FREQUENCY0.5 × PFD FREQUENCY
0957
6-02
2
Figure 22. PLL Reference Spurs vs. LO Frequency, Using Loop Filter Bandwidth of 130 kHz
–110
–105
–100
–95
–90
–85
–80
–75
–70
750 800 850 900 950 1000 1050 1100 1150
PLL
REF
EREN
CE
SPU
RS
(dB
c)
LO FREQUENCY (MHz)
TA = +85°CTA = +25°CTA = –40°C
2 × PFD FREQUENCY4 × PFD FREQUENCY
0957
6-02
3
Figure 23. PLL Reference Spurs vs. LO Frequency, Using Loop Filter Bandwidth of 130 kHz
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
750 800 850 900 950 1000 1050 1100 1150
INTE
GRA
TED
PH
ASE
NO
ISE
(°rm
s)
LO FREQUENCY (MHz)
TA = +85°CTA = +25°CTA = –40°C
0957
6-02
4
Figure 24. Integrated Phase Noise vs. LO Frequency (Spurs Omitted), Using Loop Filter Bandwidth of 130 kHz
–170
–150
–130
–110
–90
–70
–50
750 800 850 900 950 1000 1050 1100 1150
PHA
SE N
OIS
E (d
Bc/
Hz)
LO FREQUENCY (MHz)
1kHz OFFSET
10kHzOFFSET
5MHzOFFSET
10kHzOFFSET
1kHzOFFSET
5MHzOFFSET
130kHz LOOP FILTER BANDWIDTH2.5kHz LOOP FILTER BANDWIDTH
TA = +85°CTA = +25°CTA = –40°C
0957
6-02
5
Figure 25. Phase Noise vs. LO Frequency (1 kHz, 10 kHz, and 5 MHz Offsets), Shown for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
–160
–150
–140
–130
–120
–110
–100
–90
750 800 850 900 950 1000 1050 1100 1150
PHA
SE N
OIS
E (d
Bc/
Hz)
LO FREQUENCY (MHz)
100kHz OFFSET
1MHz OFFSET100kHz OFFSET
130kHz LOOP FILTER BANDWIDTH2.5kHz LOOP FILTER BANDWIDTH
TA = +85°CTA = +25°CTA = –40°C
0957
6-02
6
1MHz OFFSET
Figure 26. Phase Noise vs. LO Frequency (100 kHz and 1 MHz Offsets), Shown for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
Data Sheet ADRF6801
Rev. A | Page 13 of 34
COMPLEMENTARY CUMULATIVE DISTRIBUTION FUNCTIONS (CCDF) VS = 5 V, fLO = 900 MHz, fBB = 4.5 MHz.
0
10
20
30
40
50
60
70
80
90
100
0 2 4 6 8 10 12 14 16 18
CU
MU
LATI
VE D
ISTR
IBU
TIO
N P
ERC
ENTA
GE
(%)
GAIN (dB) AND INPUT P1dB (dBm)
GAIN
IP1dB
TA = +85°CTA = +25°CTA = –40°C
0957
6-02
7
Figure 27. Gain and Input P1dB
0
10
20
30
40
50
60
70
80
90
100
15 17 19 21 23 25 27 29 31 33 35
CU
MU
LATI
VE D
ISTR
IBU
TIO
N P
ERC
ENTA
GE
(%)
INPUT IP3 (dBm)
TA = +85°CTA = +25°CTA = –40°C
I CHANNELQ CHANNEL
0957
6-02
8
Figure 28. Input IP3
0
10
20
30
40
50
60
70
80
90
100
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5
CU
MU
LATI
VE D
ISTR
IBU
TIO
N P
ERC
ENTA
GE
(%)
IQ GAIN MISMATCH (dB)
TA = +85°CTA = +25°CTA = –40°C
0957
6-02
9
Figure 29. IQ Gain Mismatch
0
10
20
30
40
50
60
70
80
90
100
60 62 64 66 68 70 72 74 76 78 80
CU
MU
LATI
VE D
ISTR
IBU
TIO
N P
ERC
ENTA
GE
(%)
INPUT IP2 (dBm)
TA = +85°CTA = +25°CTA = –40°C
I CHANNELQ CHANNEL
0957
6-03
0
Figure 30. Input IP2
0
10
20
30
40
50
60
70
80
90
100
4 6 8 10 12 14 16 18 20 22 24
CU
MU
LATI
VE D
ISTR
IBU
TIO
N P
ERC
ENTA
GE
(%)
NOISE FIGURE (dB)
TA = +85°CTA = +25°CTA = –40°C
0957
6-13
1
Figure 31. Noise Figure
0
10
20
30
40
50
60
70
80
90
100
–5 –4 –3 –2 –1 0 1 2 3 4 5
CU
MU
LATI
VE D
ISTR
IBU
TIO
N P
ERC
ENTA
GE
(%)
IQ QUADRATURE PHASE ERROR (Degrees)
TA = +85°CTA = +25°CTA = –40°C
0957
6-13
2
Figure 32. IQ Quadrature Phase Error
ADRF6801 Data Sheet
Rev. A | Page 14 of 34
CIRCUIT DESCRIPTION The ADRF6801 integrates a high performance IQ demodulator with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions, the demodulator LO divider functions, and optimization functions, as well as allowing for an externally applied LO.
The ADRF6801 uses a high performance mixer core that results in an exceptional input IP3 and input P1dB, with a very low output noise floor for excellent dynamic range.
LO QUADRATURE DRIVE A signal at 2× the desired mixer LO frequency is delivered to a divide-by-2 quadrature phase splitter followed by limiting amplifiers which then drive the I and Q mixers, respectively.
V-TO-I CONVERTER The RF input signal is applied to an on-chip balun which then provides both a ground referenced, 50 Ω single-ended input impedance and a differential voltage output to a V-to-I converter that converts the differential voltages to differential output currents. These currents are then applied to the emitters of the Gilbert cell mixers.
MIXERS The ADRF6801 has two double-balanced mixers: one for the in-phase channel (I channel) and one for the quadrature channel (Q channel). These mixers are based on the Gilbert cell design of four cross-connected transistors. The output currents from the two mixers are summed together in the resistive loads that then feed into the subsequent emitter follower buffers.
EMITTER FOLLOWER BUFFERS The output emitter followers drive the differential I and Q signals off chip. The output impedance is set by on-chip 12 Ω series resistors that yield a 24 Ω differential output impedance for each baseband port. The fixed output impedance forms a voltage divider with the load impedance that reduces the effective gain. For example, a 500 Ω differential load has ~0.5 dB lower effective gain than with a high (10 kΩ) differential load impedance.
The common-mode dc output levels of the emitter followers are set from VCCBB via the voltage drop across the mixer load resistors, the VBE of the output emitter follower, and the voltage drop across the 12 Ω series resistor.
BIAS CIRCUITRY There are several band gap reference circuits and three low dropout regulators (LDOs) in the ADRF6801 that generate the reference currents and voltages used by different sections. The first of the LDOs is the 2.5 V LDO, which is always active and provides the 2.5 V supply rail used by the internal digital logic blocks. The 2.5 V LDO output is connected to DECL2 (Pin 9) for the user to provide external decoupling.
The second LDO is the VCO LDO, which acts as the positive supply rail for the internal VCO. The VCO LDO output is connected to DECL2 (Pin 40) for the user to provide external decoupling. The VCO LDO can be powered down by setting Register 6, DB18 = 0, which allows the user to save power when not using the VCO.
The third LDO is the 3.3 V LDO, which acts as the 3.3 V positive supply rail for the reference input, phase frequency detector, and charge pump circuitry. The 3.3 V LDO output is connected to DECL3 (Pin 2) for the user to provide external decoupling. The 3.3 V LDO can be powered down by setting Register 6, DB19 = 0, which allows the user to save power when not using the VCO. The demodulator also has a bias circuit that supplies bias current for the mixer V-to-I stage, which then sets the bias for the mixer core. The demodulator bias cell can also be shut down by setting Register 5, DB7 = 0.
REGISTER STRUCTURE The ADRF6801 provides access to its many programmable features through a 3-wire SPI control interface that is used to program the seven internal registers. The minimum delay and hold times are shown in the timing diagram (see Figure 2). The SPI provides digital control of the internal PLL/VCO as well as several other features related to the demodulator core, on-chip referencing, and available system monitoring functions. The MUXOUT pin provides a convenient, single-pin monitor output signal that can be used to deliver a PLL lock-detect signal or an internal voltage proportional to the local junction temperature.
Note that internal calibration for the PLL must run when the ADRF6801 is initialized at a given frequency. This calibration is run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Register 0, Register 1, and Register 2 must always be programmed last. For ease of use, starting the initial programming with Register 6 and then programming the registers in descending order, ending with Register 0, is recommended. Once the PLL and other settings are programmed, the user can change the PLL frequency simply by programming Register 0, Register 1, or Register 2 as necessary.
Data Sheet ADRF6801
Rev. A | Page 15 of 34
DIVIDEMODE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0)
DM
0
1
ID6 ID5 ID4 ID3 ID2 ID1 ID0
0 0 1 0 1 0 1
0 0 1 0 1 1 0
0 0 1 0 1 1 1
0 0 1 1 0 0 0
... ... ... ... ... ... ...
... ... ... ... ... ... ...
0 1 1 1 0 0 0
... ... ... ... ... ... ...
... ... ... ... ... ... ...
1 1 1 0 1 1 1
1 1 1 1 0 0 0
1 1 1 1 0 0 1
1 1 1 1 0 1 0
1 1 1 1 0 1 1
...
...
119
120 (INTEGER MODE ONLY)
DIVIDE RATIO
21 (INTEGER MODE ONLY)
22 (INTEGER MODE ONLY)
23 (INTEGER MODE ONLY)
24
...
...
56 (DEFAULT)
INTEGER
INTEGER DIVIDE RATIO CONTROL BITS
DIVIDE MODE
FRACTIONAL (DEFAULT)
121 (INTEGER MODE ONLY)
122 (INTEGER MODE ONLY)
123 (INTEGER MODE ONLY)
0957
6-03
1
Figure 33. Integer Divide Control Register (R0)
Register 0—Integer Divide Control
With R0[2:0] set to 000, the on-chip integer divide control register is programmed as shown in Figure 33. The internal VCO frequency (fVCO) equation is
fVCO = fPFD × (INT + (FRAC/MOD)) × 2 (1)
where: fVCO is the output frequency of the internal VCO. INT is the preset integer divide ratio value (21 to 123 for integer mode, 24 to 119 for fractional mode). MOD is the preset fractional modulus (1 to 2047). FRAC is the preset fractional divider ratio value (0 to MOD − 1).
The integer divide ratio sets the INT value in Equation 1. The INT, FRAC, and MOD values make it possible to generate output frequencies that are spaced by fractions of the PFD frequency.
Note that the demodulator LO frequency is given by fLO = fVCO/4.
Divide Mode
Divide mode determines whether fractional mode or integer mode is used. In integer mode, the VCO output frequency, fVCO, is calculated by
fVCO = fPFD × (INT) × 2 (2)
ADRF6801 Data Sheet
Rev. A | Page 16 of 34
Register 1—Modulus Divide Control
With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 34. The MOD value is the preset fractional modulus ranging from 1 to 2047.
MODULUS DIVIDE RATIO
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)
MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 1 0
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
1 1 0 0 0 0 0 0 0 0 0
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
1 1 1 1 1 1 1 1 1 1 1
MODULUS VALUE
...
...
2047
CONTROL BITS
1
1536 (DEFAULT)
2
...
...
0957
6-03
2
Figure 34. Modulus Divide Control Register (R1)
Register 2—Fractional Divide Control
With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 35. The FRAC value is the preset fractional modulus ranging from 0 to MOD − 1.
FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 1
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
0 1 1 0 0 0 0 0 0 0 0
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
FRACTIONAL VALUE
0
1
...
...
768 (DEFAULT)
...
...
<MOD
FRACTIONAL DIVIDE RATIO
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CONTROL BITS
0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0)
0957
6-03
3
Figure 35. Fractional Divide Control Register (R2)
Register 3—Σ-Δ Modulator Dither Control
With R3[2:0] set to 011, the on-chip Σ-Δ modulator dither control register is programmed as shown in Figure 36. The dither restart value can be programmed from 0 to 217 to 1, though a value of 1 is typically recommended.
DITHERENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 DITH1 DITH0 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)
DITH1 DITH0
0 0
0 1
1 0
1 1
DEN
0
1
DITHERMAGNITUDE DITHER RESTART VALUE CONTROL BITS
DITHER MAGNITUDE
15 (DEFAULT)
7
3
1 (RECOMMENDED)
DITHER ENABLE
DISABLE
ENABLE (DEFAULT, RECOMMENDED)
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0x00001 (DEFAULT)
...
...
0x1FFFF
DITHER RESTARTVALUE
0957
6-03
4
Figure 36. Σ-Δ Modulator Dither Control Register (R3)
Data Sheet ADRF6801
Rev. A | Page 17 of 34
Register 4—Charge Pump, PFD, and Reference Path Control
With R4[2:0] set to 100, the on-chip charge pump, PFD, and reference path control register is programmed as shown in Figure 37.
The charge pump current is controlled by the base charge pump current (ICP, BASE) and the value of the charge pump current multiplier (ICP, MULT).
The base charge pump current can be set using an internal or external resistor (according to Bit DB18 of Register 4). When using an external resistor, the value of ICP, BASE can be varied according to
[ ] 8.37250
4.217Ω , −
×
= BASECPSET
IR
The actual charge pump current can be programmed to be a multiple (1, 2, 3, or 4) of the charge pump base current. The multiplying value (ICP, MULT) is equal to 1 plus the value of the DB11 and DB10 bits in Register 4.
The PFD phase offset multiplier (θPFD, OFS), which is set by Bit DB16 to Bit DB12 of Register 4, causes the PLL to lock with a nominally fixed phase offset between the PFD reference signal
and the divided-down VCO signal. This phase offset is used to linearize the PFD-CP transfer function and can improve fractional spurs. The magnitude of the phase offset is determined by
MULTCP
OFSPFD
I ,
,5.22[deg]ΔΦθ
=
Finally, the phase offset can be either positive or negative depending on the value of the DB17 bit in Register 4.
The reference frequency applied to the PFD can be manipulated using the internal reference path source. The external reference frequency applied can be internally scaled in frequency by 2×, 1×, 0.5×, or 0.25×. This allows a broader range of reference frequency selections while keeping the reference frequency applied to the PFD within an acceptable range.
The ADRF6801 also provides a MUXOUT pin that can be programmed to output a selection of several internal signals. The default mode provides a lock-detect output that allows users to verify when the PLL has locked to the target frequency. In addition, several other internal signals can be routed to the MUXOUT pin as described in Figure 37.
ADRF6801 Data Sheet
Rev. A | Page 18 of 34
CHARGEPUMPREF
PDFPHASEOFFSET
POLARITY
CPCNTLSRC
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)
CPC1 CPC0
0 00 11 01 1
CPS
01
CPP1 CPP0
0 00 11 01 1
CPB4 CPB3 CPB2 CPB1 CPB0
0 0 0 0 00 0 0 0 1
0 0 1 1 0
0 1 0 1 0... ... ... ... ...1 1 1 1 1
CPBD
01
CPM
01
RS1 RS0
0 00 11 01 1
RMS2 RMS1 RMS0
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
10 × 22.5°/ICP, MULT (DEFAULT)...31 × 22.5°/ICP, MULT
PFD PHASE OFFSET MULTIPLIER
0 × 22.5°/ICP, MULT1 × 22.5°/ICP, MULT
6 × 22.5°/ICP, MULT (RECOMMENDED)
BOTH ONPUMP DOWNPUMP UPTRISTATE (DEFAULT)
OUPUT MUXSOURCE
INPUT REFPATH
SOURCE
PFD PHASE OFFSETMULTIPLIER VALUE
CHARGEPUMP
CURRENTMULTIPLIER
CHARGEPUMP
CONTROL
PFD EDGESENSITIVITY
CONTROL BITSPFD ANTI-
BACKLASHDELAY
PE0
01
REFERENCE PATH EDGESENSITIVITY
FALLING EDGE (RECOMMENDED)RISING EDGE (DEFAULT)
PAB1 PAB0
0 0
0 11 01 1
PFD ANTIBACKLASHDELAY
0ns (DEFAULT, RECOMMENDED)0.5ns0.75ns0.9ns
CHARGE PUMPCONTROL
BUFFERED VERSION OF 0.5 × REFERENCE INPUT
CHARGE PUMP CONTROL SOURCE
CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL)CONTROL FROM PFD (DEFAULT)
OUTPUT MUX SOURCE
LOCK DETECT (DEFAULT)VPTATBUFFERED VERSION OF REFERENCE INPUT
PFD PHASE OFFSET POLARITY
NEGATIVEPOSITIVE (DEFAULT, RECOMMENDED)
CHARGE PUMP CURRENTREFERENCE SOURCE
INTERNAL (DEFAULT)EXTERNAL
0.25 × REFERENCE INPUT
CHARGE PUMPCURRENT MULTIPLIER
12 (DEFAULT, RECOMMENDED)34
INPUT REFERENCEPATH SOURCE
2 × REFERENCE INPUTREFERENCE INPUT (DEFAULT)0.5 × REFERENCE INPUT
BUFFERED VERSION OF 2 × REFERENCE INPUTTRISTATEBUFFERED VERSION OF 0.25 × FREFRESERVED (DO NOT USE)
PE1
01
DIVIDER PATH EDGESENSITIVITY
FALLING EDGE (RECOMMENDED)RISING EDGE (DEFAULT)
... ... ... ... ... ...
... ... ... ... ... ...
0957
6-03
5
Figure 37. Charge Pump, PFD, and Reference Path Control Register (R4)
Data Sheet ADRF6801
Rev. A | Page 19 of 34
Register 5—LO Path and Demodulator Control Register 5 controls whether the LOIP and LOIN pins act as an input or output, whether the divider before the polyphase divider is in divide-by-1 or divide-by-2, and whether the demodulator bias circuitry is enabled as detailed in Figure 38.
DEMODBIAS
ENABLE
LOFIRST
DIVIDER
LOIN/OUTCTRL
LOOUTPUTDRIVERENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
DMBE
DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 LDIV LXL LDRV C3(1) C2(0) C1(1)
LDRV
01
LXL
01
LDIV
01
÷ 1÷ 2 (DEFAULT, NECESSARY FOR VCO USE)
LO OUTPUT DRIVERENABLE
DRIVER OFF (DEFAULT)DRIVER ON
DMBE
01
DISABLEENABLE (DEFAULT)
DEMOD BIAS ENABLE
LO IN/OUT CONTROL
LO OUTPUT (DEFAULT)LO INPUT
DIVIDE RATIO
CONTROL BITS
0 0 0 0 00 0 00 0 0 0
0957
6-03
6
Figure 38. LO Path and Demodulator Control Register (R5)
ADRF6801 Data Sheet
Rev. A | Page 20 of 34
Register 6—VCO Control and Enables
With R6[2:0] set to 110, the VCO control and enables register is programmed as shown in Figure 39.
VCO band selection is normally selected based on BANDCAL calibration; however, the VCO band can be selected directly using Register 6. The VCO BS SRC determines whether the BANDCAL calibration determines the optimum VCO tuning band or if the external SPI interface is used to select the VCO tuning band based on the value of the VCO band select.
The VCO amplitude can be controlled through Register 6. The VCO amplitude setting can be controlled between 0 and 31 decimal, with a default value of 24.
The internal VCO can be disabled using Register 6. The internal VCO LDO can be disabled if an external clean 3.0 V supply is available.
The internal charge pump can be disabled through Register 6. Normally, the charge pump is enabled.
CHARGEPUMP
ENABLE
3.3VLDO
ENABLE
VCOENABLE
VCOSWITCH
VCOBSCSR
VBSRC
01
VCO EN
VCO LDOENABLE VCO AMPLITUDE VCO BAND SELECT
CHARGE PUMP ENABLE
VCO BAND CAL AND SW SOURCE CONTROL
BAND CAL (DEFAULT)
VCO SW
01
VCO SWITCH CONTROL FROM SPI
REGULAR (DEFAULT)BAND CAL
SPI
VCO ENABLE
DISABLEENABLE (DEFAULT)
DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CONTROL BITS
DB23
CPEN L3EN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)LVEN
01
LVEN VCO LDO ENABLE
DISABLEENABLE (DEFAULT)
01
L3EN 3.3V LDO ENABLE
DISABLEENABLE (DEFAULT)
01
CPEN
DISABLEENABLE (DEFAULT)
01
0 0 0
VC5 VC4 VC3 VC2 VC1
0 0 0 0 0... ... ... ... ...
... ... ... ... ...
... ... ... ... ...1 1 1 1 1
...63 (RECOMMENDED)
VCO AMPLITUDE
0...
...0 0 1 0 0 8 (DEFAULT)
1 0 1 1 1
VC0
0...
...
...1
0
1 47
VBS5 VBS4 VBS3 VBS2 VBS1
0 0 0 0 0... ... ... ... ...
... ... ... ... ...
VCO BAND SELECTFROM SPI
0...
...
1 0 0 0 0 32 (DEFAULT)
1 1 1 1 1
VBS0
0...
...0
1 63
0957
6-03
7
Figure 39. VCO Control and Enables (R6)
Data Sheet ADRF6801
Rev. A | Page 21 of 34
APPLICATIONS INFORMATION BASIC CONNECTIONS The basic circuit connections for a typical ADRF6801 application are shown in Figure 40.
SUPPLY CONNECTIONS The ADRF6801 has several supply connections and on-board regulated reference voltages that should be bypassed to ground using low inductance bypass capacitors located in close proximity to the supply and reference pins of the ADRF6801. Specifically Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 27, Pin 29, Pin 34, and Pin 40 should be bypassed to ground using individual bypass capacitors. Pin 40 is the decoupling pin for the on-board VCO LDO, and for best phase noise performance, several bypass capacitors ranging from 100 pF to 10 µF may help to improve phase noise performance. For additional details on bypassing the supply nodes, see the evaluation board schematic in Figure 42.
SYNTHESIZER CONNECTIONS The ADRF6801 includes an on-board VCO and PLL for LO synthesis. An external reference must be applied for the PLL to operate. A 1 V p-p nominal external reference must be applied to Pin 6 through an ac coupling capacitor. The reference is compared to an internally divided version of the VCO output frequency to create a charge pump error current to control and lock the VCO. The charge pump output current is filtered and converted to a control voltage through the external loop filter that is then applied to the VTUNE pin (Pin 39). ADIsimPLL™ can be a helpful tool when designing the external charge pump loop filter. The typical Kv of the VCO, the charge pump output current magnitude, and PFD frequency should all be considered when designing the loop filter. The charge pump current magnitude can be set internally or with an external RSET resistor connected to Pin 5 and ground, along with the internal digital settings applied to the PLL (see the Register 4—Charge Pump, PFD, and Reference Path Control section for more details).
40 39 38 37 36 35 34 33 32 31
11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
6
7
8
9
10 21
22
23
24
25
26
27
28
29
30
IBBN
LOSE
L
IBBP
GND
V CC
LO
LON
LOP
DEC
L1
VTU
NE
GND
RFIN
GND
GND
VCCBB
GND
GND
GNDRF
VCCRF
GND
VCCBB
QB
BN
GN
D
CLK
DAT A
QB
BP
VCC
L O
LEGN
D
GN
D
GND
MUXOUT
GND
RSET
DECL3
GND
CPOUT
VCC2
REFIN
VCC1
DECL2
ADRF6801
+5V
+5V
+5V
RF INPUT
+5V
+5V
EXTERNALREFERENCE
MONITOROUTPUT
R2
OPEN
+5V
SPI CONTROL IF Q-OUTPUTBALUN IF Q-OUTPUT
IF I-OUTPUTBALUN IF I-OUTPUT
CHARGE PUMPLOOP FILTER
+5V
0957
6-04
1
Figure 40. Basic Connections
ADRF6801 Data Sheet
Rev. A | Page 22 of 34
I/Q OUTPUT CONNECTIONS The ADRF6801 has I and Q baseband outputs. Each output stage consists of emitter follower output transistors with a low differential impedance of 24 Ω and can source up to 12 mA p-p differentially. A Mini-Circuits TCM9-1+ balun is used to trans-form a single-ended 50 Ω load impedance into a nominal 450 Ω differential impedance.
RF INPUT CONNECTIONS The ADRF6801 is to be driven single-ended and can be either dc coupled or ac coupled. There is an on-chip ground referenced balun that converts the applied single-ended signal to a differential signal that is then input to the RF V-to-I converter.
CHARGE PUMP/VTUNE CONNECTIONS The ADRF6801 uses a loop filter to create the VTUNE voltage for the internal VCO. The loop filter in its simplest form is an integrating capacitor. It converts the current mode error signal coming out of the CPOUT pin into a voltage to control the VCO via the VTUNE voltage. The stock filter on the evaluation board has a bandwidth of 130 kHz. The loop filter contains seven components, four capacitors, and three resistors. Changing the values of these components changes the bandwidth of the loop filter. Note that to obtain the approximately 2.5 kHz loop band-width, the user can change the values of the following components on the evaluation board to as follows: C14 = 0.1 µF, R10 = 68 Ω, C15 = 4.7 µF, R9 = 270 Ω, C13 = 47 nF, R60 = 0 Ω, C4 = open.
LO SELECT INTERFACE The ADRF6801 has the option of either monitoring a scaled version of the internally generated LO (LOSEL pin driven high at 3.3 V) or providing an external LO source (LOSEL pin driven low to ground, the LDRV bit in Register 5 set low, and the LXL bit in Register 5 set high). See the Pin Configuration and Function Descriptions section for full operation details.
EXTERNAL LO INTERFACE The ADRF6801 provides the option to use an external signal source for the LO into the IQ demodulating mixer core. It is important to note that the applied LO signal is divided down by either 2 or 4 depending on the LO path divider bit, LDIV, in Register 5, prior to the actual IQ demodulating mixer core. The divider is determined by the register settings in the LO path and mixer control register (see the Register 5—LO Path and Demodulator Control section). The LO input pins (Pin 37 and Pin 38) present a broadband differential 50 Ω input impedance. The LOP and LON input pins must be ac-coupled. This is achieved on the evaluation board via a Mini-Circuits TC1-1-13+ balun with a 1:1 impedance ratio. When not in use, the LOP and LON pins can be left unconnected.
SETTING THE FREQUENCY OF THE PLL The frequency of the VCO/PLL, once locked, is governed by the values programmed into the PLL registers, as follows:
fPLL = fPFD × 2 × (INT + FRAC/MOD)
where: fPLL is the frequency at the VCO when the loop is locked. fPFD is the frequency at the input of the phase frequency detector. INT is the integer divide ratio programmed into Register 0. MOD is the modulus divide ratio programmed into Register 1. FRAC is the fractional value programmed into Register 2.
The practical lower limit of the reference input frequency is determined by the combination of the desired fPLL and the maximum programmable integer divide ratio of 119 and reference input frequency multiplier of 2. For a maximum fPLL of 4600 MHz,
fREF > ~fPLL/(119 × 2 × 2), or 9.7 MHz.
A lock detect signal is available as one of the selectable outputs through the MUXOUT pin, with logic high signifying that the loop is locked.
When the internal VCO is used, the actual LO frequency is
fLO = fPLL/4
REGISTER PROGRAMMING Because Register 6 controls the powering of the VCO and charge pump, it must be programmed once before programming the PLL frequency (Register 0, Register 1, and Register 2).
The registers should be programmed starting with the highest register first and then sequentially down to Register 0 last. When Register 0, Register 1, or Register 2 is programmed, an internal VCO calibration is initiated that must execute when the other registers are set. Therefore, the order must be Register 6, Register 5, Register 4, Register 3, Register 2, Register 1, and then Register 0. Whenever Register 0, Register 1, or Register 2 is written to, it initializes the VCO calibration (even if the value in these registers does not change). After the device has been powered up and the registers configured for the desired mode of operation, only Register 0, Register 1, or Register 2 must be programmed to change the LO frequency.
If none of the register values is changing from their defaults, there is no need to program them.
Data Sheet ADRF6801
Rev. A | Page 23 of 34
EVM MEASUREMENTS EVM is a measure used to quantify the performance of a digital radio transmitter or receiver. A signal received by a receiver has all constellation points at their ideal locations; however, various imperfections in the implementation (such as magnitude imbalance, noise floor, and phase imbalance) cause the actual constellation points to deviate from their ideal locations.
In general, a demodulator exhibits three distinct EVM limitations vs. received input signal power. As signal power increases, the distortion components increase. At large enough signal levels, where the distortion components due to the harmonic non-linearities in the device are falling in-band, EVM degrades as signal levels increase. At medium signal levels, where the demodulator behaves in a linear manner and the signal is well above any notable noise contributions, the EVM has a tendency to reach an optimal level determined dominantly by either quadrature accuracy and I/Q gain match of the demodulator or the precision of the test equipment. As signal levels decrease, such that the noise is the major contribution, the EVM performance vs. the signal level exhibits a decibel-for-decibel degradation with decreasing signal level. At lower signal levels, where noise proves to be the dominant limitation, the decibel EVM proves to be directly proportional to the SNR.
The basic test setup to test EVM for the ADRF6801 consisted of an Agilent E4438C, which was used as a signal source. The 900 MHz modulated signal was driven single ended into the RFIN SMA connector of the ADRF6801 evaluation board. The IQ baseband outputs were taken differentially into two AD8130 difference amplifiers to convert the differential signals into single-ended signals. A Hewlett Packard 89410A VSA was used to sample and calculate the EVM of the signal. The ADRF6801 IQ base-band output pins were presented with a 450 Ω differential load impedance.
The ADRF6801 shows excellent EVM performance for 16 QAM. Figure 41 shows the EVM of the ADRF6801 being better than −40 dB over a RF input range of about +35 dB for the 16 QAM modulated signal at a 10 MHz symbol rate. The pulse shaping filter’s roll-off (alpha) was set to 0.35.
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
–65 –55 –45 –35 –25 –15 –5 5 15EV
M (d
B)
INPUT POWER (dBm) 0957
6-04
2
Figure 41. EVM vs. Input Power, EVM Measurements at fRF = 900 MHz;
fIF = 0 MHz (that is, Direct Down Conversion); 16 QAM; Symbol Rate = 10 MHz
ADRF6801 Data Sheet
Rev. A | Page 24 of 34
EVALUATION BOARD LAYOUT AND THERMAL GROUNDING An evaluation board is available for testing the ADRF6801. The evaluation board schematic is shown in Figure 42. Table 5 provides
the component values and suggestions for modifying the component values for the various modes of operation.
40 39 38 37 36 35 34 33 32 31
11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
6
7
8
9
10 21
22
23
24
25
26
27
28
29
30
IBB
N
LOSE
L
IBB
P
GN
D
VCC
LO
LON
LOP
DEC
L1
VTU
NE
GN
D
RFIN
GND
GND
VCCBB
GND
GND
GNDRF
VCCRF
GND
VCCBB
QB
BN
GN
D
CLK
DAT
A
QB
BP
VCC
LO
LEGN
D
GN
D
GN
D
MUXOUT
GND
RSET
DECL3
GND
CPOUT
VCC2
REFIN
VCC1
DECL2
ADRF6801
3P3V_SENSE
VCC4
VCO_LDO
0.1µF 100pF
CP
LO VCC_LO
0.1µF
VCC_BB
100pF
VCC_RF
1nF1nF
RFIN
100pF
VCC_BB
C1422pF C15
2.7nF
R103kΩ
R9
QOUT_SE
0.1µF100pF
VCC_LO
OUTPUT_EN
REFIN
REFOUT
2P5V0Ω
0Ω
0Ω
0Ω
0Ω 0Ω
VCC2
NET NAME
LEGEND
TEST POINT
SMA INPUT/OUTPUT
49.9Ω1nF
R47
R48R44
R43
R42C290.1µF
P3
T1
R2
R8
C12C11
C10100pF
C90.1µF
R7
C27100pFC26
C24
R26
C25
R60Ω
C8100pF
C70.1µF
C6 C5
R37
R38
10kΩ
C136.8pF C4
22pF
VTUNE
R59OPEN
R1R12R11
C1100pF
C210µF
VCO_LDO
C31
R14
R16
R18
C16100pF
C170.1µF
C310µF
2P5V_LDO
R17VCC
C18100pF
C190.1µF
1 2 3 4 5
6 7 8 9
OPENR58
OPENR50
OPENR19
OPEN
CLK
C32
R350Ω
OPENR51
OPENC33
R30
DATA
OPENR52
OPENC34
R57
LE
R36
VTUNE
GND
GND1
GND2C21 C20
R24
C22 C23
R25
VCC_RF VCC_BB
VCC_SENSEVCC
R29 R32
C2810µF
OPEN
OPEN
OPEN
0Ω
0Ω
0Ω 0Ω
0Ω
R21
R22
QBBP
QBBN
R23
OPEN
OPEN
IOUT_SER41
R40
R39C30
0.1µF
0.1µF
0.1µF
T2
0Ω
R4
24
51
3
IBBP
IBBN
R3
OPEN
OPEN
R46OPEN
R45
R56
R55
10kΩ
10kΩ
VCCS1
13
4 5 2
OPENR49
3P3V1
VCC4
VCC_LO1
VCC
DIG_GND
P1
VCC_BB1
VCC_RF
VCC_LO
VCC
R28
0Ω
R60
10kΩ
R33
0ΩLO_EXTERN
R150Ω
S2
P2
R54
T3
24
51
3
0Ω
0Ω
0Ω
0Ω
VCC_LO
R310Ω
VCC4
R130Ω0Ω
R50Ω
0Ω
0Ω
0Ω
0Ω
R20
0Ω
R34
OPEN
10kΩOPEN
0Ω
R530Ω
0Ω0Ω
0Ω
R270Ω
0Ω
0957
6-04
4
J1
LO_EXTERN
OUTPUT_EN
OSC_3P3V
VCC_SENSE
VCO_LDO
2P5V_LDO
3P3V_SENSE
VCC1
3
5
7
2
4
6
8
109
Figure 42. Evaluation Board Schematic
Data Sheet ADRF6801
Rev. A | Page 25 of 34
The package for the ADRF6801 features an exposed paddle on the underside that should be well soldered to an exposed opening in the solder mask on the evaluation board. Figure 43 illustrates the dimensions used in the layout of the ADRF6801 footprint on the ADRF6801 evaluation board (1 mil. = 0.0254 mm).
Note the use of nine via holes on the exposed paddle. These ground vias should be connected to all other ground layers on the evaluation board to maximize heat dissipation from the device package. Under these conditions, the thermal impedance of the ADRF6801 was measured to be approximately 30°C/W in still air.
0.168
0.232
0.177
0.0350.050
0.012
0.025
0.020
0957
6-04
3
Figure 43. Evaluation Board Layout Dimensions for the ADRF6801 Package
0957
6-04
6
Figure 44. ADRF6801 Evaluation Board Top Layer
0957
6-04
7
Figure 45. ADRF6801 Evaluation Board Bottom Layer
Table 5. Evaluation Board Configuration Options Component Function Default Condition VCC, VCC2, VCC4, VCO_LDO, VCC_LO, VCC_LO1, VCC_RF, VCC_BB1, 3P3V1, 2P5V, CLK, DATA, LE, CP, DIG_GND, GND, GND1, GND2
Power supply, ground and other test points. Connect a 5 V supply to VCC.
VCC, VCC2, VCC4, VCC_LO, VCC_RF, VCC_BB1, VCC_LO1, VCO_LDO, 3P3V1, 2P5V = Components Corporation TP-104-01-02, CP, LE, CLK, DATA = Components Corporation TP-104-01-06, GND, GND1, GND2, DIG_GND = Components Corporation TP-104-01-00
R1, R6, R7, R8, R13, R15, R17, R18, R24, R25, R26, R27, R29, R31, R32, R36, R49
Power supply decoupling. Shorts or power supply decoupling resistors.
R1, R6, R7, R8 = 0 Ω (0402), R13, R15, R17 = 0 Ω (0402), R18, R24, R25, R26, R27 = 0 Ω (0402), R29, R31, R32 = 0 Ω (0402), R36 = 0 Ω (0402),
ADRF6801 Data Sheet
Rev. A | Page 26 of 34
Component Function Default Condition C1, C2, C3, C7, C8, C9, C10, C11, C12, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28
The capacitors provide the required decoupling of the supply-related pins.
C1, C8, C10, C12 = 100 pF (0402), C16, C18, C21, C22 = 100 pF (0402), C24, C26 = 100 pF (0402), C7, C9, C11 = 0.1 µF (0402), C17, C19, C20, C23 = 0.1 µF (0402), C25, C27 = 0.1 µF (0402), C3, C2 = 10 µF (0603), C28 = 10 µF (3216)
T1, C5, C6 External LO path. The T1 transformer provides single-ended-to-differential conversion. C5 and C6 provide the necessary ac coupling.
C5, C6 = 1 nF (0603), T1 = TC1-1-13+ Mini-Circuits
R16, R14, R58, C31 REFIN input path. R14 provides a broadband 50 Ω termination followed by C31, which provides the ac coupling into REFIN. R16 provides an external connectivity to the MUXOUT feature described in Register 4. R58 provides option for connectivity to the P1-6 line of a 9-pin D-sub connector for dc measurements.
R14 = 49.9 Ω (0402), R16 = 0 Ω (0402), R58 = open (0402), C31 = 1 nF (0603)
R2, R9, R10, R11, R12, R37, R38, R59, R60, C4, C14, C15, C13
Loop filter component options. A variety of loop filter topologies is supported using component placements C4, C13, C14, C15, R9, R10, and R60. R38 and R59 provide connectivity options to numerous test points for engineering evaluation purposes. R2 provides resistor programmability of the charge pump current (see Register 4 description). R37 connects the charge pump output to the loop filter. R12 references the loop filter to the VCO_LDO. Default values on board provide a loop filter bandwidth of roughly 130 kHz using a 26 MHz PFD frequency.
R12, R37, R38 = 0 Ω (0402), R59 = open (0402), R9, R60 = 10 kΩ (0402), R10 = 3 kΩ (0402), R2, R11 = open (0402), C13 = 6.8 pF (0402), C4, C14 = 22 pF (0402), C15 = 2.7 nF (1206)
R3, R4, R5, R21, R22, R23, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, C29, C30, T2, T3, P2, P3
IF I/Q output paths. The T2 and T3 baluns provide a 9:1 impedance transformation; therefore, with a 50 Ω load on the single-ended IOUT/QOUT side, the center tap side of the balun presents a differential 450 Ω to the ADRF6806. The center taps of the baluns are ac grounded through C29 and C30. The baluns create a differential-to-single-ended conversion for ease of testing and use, but an option to have straight differential outputs is achieved via populating R3, R39, R23, and R42 with 0 Ω resistors and removing R4, R5, R21, and R22. P2 and P3 are differential measurement test points (not to be used as jumpers).
R4, R5, R21, R22, = 0 Ω (0402), R40, R43, R45, R46 = 0 Ω (0402), R47, R48 = 0 Ω (0402), R3, R23, R39, R41, R42, R44 = open (0402), C29, C30, = 0.1 µF (0402), T2, T3 = TCM9-1+ Mini-Circuits, P2, P3 = Samtec SSW-102-01-G-S
R28 RF input interface. R28 provides the single-ended RF input path to the on-chip RF input balun.
R28 = 0 Ω (0402)
R30, R35, R50, R51, R52, R57, C32, C33, C34, P1
Serial port interface. A 9-pin D-sub connector (P1) is provided for connecting to a host PC or control hardware. Optional RC filters can be installed on the CLK, DATA, and LE lines to filter the PC signals through R50 to R52 and C32 to C34. CLK, DATA, and LE signals can be observed via test points for debug purposes. R58 provides a connection to the MUXOUT for sensing lock detect through the P1 connector.
R30, R35, R57 = 0 Ω (0402), R50, R51, R52 = open (0402), C32, C33, C34 = open (0402), P1 = Tyco Electronics 5747840-3
R33, R55, R56, S1 LO select interface. The LOSEL pin, in combination with the LDRV and LXL bits in Register 5, controls whether the LOP and LON pins operate as inputs or outputs. A detailed description of how the LOSEL pin, LDRV bit, and the LXL bit work together to control the LOP and LON pins is found in Table 4 under the LOSEL pin description. Using the S1 switch, the user can pull LOSEL to a logic high (VCC/2) or a logic low (ground). Resistors R55 and R56 form a resistor divider to provide a logic high of VCC/2. LO select can also be controlled through Pin 9 of J1. The 0 Ω jumper, R33, must be installed to control LOSEL via J1.
R33 = 0 Ω (0402), R55, R56 = 10 kΩ (0402), S1 = Samtec TSW-103-08-G-S
Data Sheet ADRF6801
Rev. A | Page 27 of 34
Component Function Default Condition J1 Engineering test points and external control. J1 is a
10-pin connector connected to various important points on the evaluation board that the user can measure or force voltages upon.
J1 = Molex Connector Corp. 10-89-7102
R19, R20, R34, R53, R54, S2 Provides ground connection for Pin 16. R20, R53 = 0 Ω (0402), R34, R54 = open (0402), R19 = open, S2 = open
ADRF6801 Data Sheet
Rev. A | Page 28 of 34
ADRF6801 SOFTWARE The ADRF6801 evaluation board can be controlled from PCs using a USB adapter board, which is also available from Analog Devices, Inc. The USB adapter evaluation documentation and ordering information can be found on the EVAL-ADF4XXXZ-USB product page. The basic user interfaces are shown in Figure 46 and Figure 47.
The software allows the user to configure the ADRF6801 for various modes of operation. The internal synthesizer is controlled by clicking on any of the numeric values listed in RF Section.
Attempting to program Ref Input Frequency, PFD Frequency, VCO Frequency (2×LO), LO Frequency, or other values in RF Section launches the Synth Form window shown in Figure 47. Using Synth Form, the user can specify values for Local Oscillator Frequency (MHz) and External Reference Frequency (MHz). The user can also enable the LO output buffer and divider options from this menu. After setting the desired values, it is important to click Upload all registers for the new setting to take effect.
0957
6-04
8
Figure 46. Evaluation Board Software Main Window
Data Sheet ADRF6801
Rev. A | Page 29 of 34
0957
6-04
9
Figure 47. Evaluation Board Software Synth Form Window
ADRF6801 Data Sheet
Rev. A | Page 30 of 34
CHARACTERIZATION SETUPS Figure 48 to Figure 50 show the general characterization bench setups used extensively for the ADRF6801. The setup shown in Figure 48 was used to do the bulk of the testing. An automated Agilent VEE program was used to control the equipment over the IEEE bus. This setup was used to measure gain, input P1dB, output P1dB, input IP2, input IP3, IQ gain mismatch, IQ quadrature accuracy, and supply current. The evaluation board was used to perform the characterization with a Mini-Circuits TCM9-1+ balun on each of the I and Q outputs. When using the TCM9-1+ balun below 5 MHz (the specified 1 dB low frequency corner of the balun), distortion performance degrades; however, this is not the ADRF6801 degrading, merely the low frequency corner of the balun introducing distortion effects. Through this balun, the 9-to-1 impedance transformation effectively presented a 450 Ω differential load at each of the I and Q channels. The losses of the output baluns were de-embedded from all measurements.
To do phase noise and reference spur measurements, the setup shown in Figure 50 was used. Phase noise was measured at the baseband output (I or Q) at a baseband carrier frequency of 50 MHz. The baseband carrier of 50 MHz was chosen to allow phase noise measurements to be taken at frequencies of up to 20 MHz offset from the carrier. The noise figure was measured using the setup shown in Figure 49 at a baseband frequency of 10 MHz.
Data Sheet ADRF6801
Rev. A | Page 31 of 34
R&S SMT03 SIGNAL GENERATOR
R&S SMT03 SIGNAL GENERATOR
AGILENT E3631APOWER SUPPLY
MINI-CIRCUITSZHL-42W AMPLIFIER
(SUPPLIED WITH +15V dcFOR OPERATION)
AGILENT 11636APOWER DIVIDER
(USED AS COMBINER)REF
RF2
RF1
RF SWITCH MATRIX
ADRF6801EVALUATION BOARD
RF
6dB 3dB
3dB
3dB
3dB
3dB
6dB
I CH
AGILENT 34980AMULTIFUNCTION
SWITCH(WITH 34950 AND 2×
34921 MODULES)10-PIN
CONNECTION(+5V VPOS,
DC MEASURE)
9-PIN D-SUB CONNECTION(VCO AND PLL PROGRAMMING)
RF
IEEE
IEEE
R&S SMA100SIGNAL GENERATOR
AGILENT MXASPECTRUM ANALYZER
HP 8508AVECTOR
VOLTMETER
Q CH
AGILENT DMM(FOR ISUPPLY MEAS.)
REF
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEECH A
CH B
6dB
0957
6-05
0
IEEE
Figure 48. General Characterization Setup
ADRF6801 Data Sheet
Rev. A | Page 32 of 34
AGILENT E3631APOWER SUPPLY
REF
RF SWITCH MATRIX
ADRF6801EVALUATION BOARD
RF
6dB 3dB 6dB
I CH
10-PINCONNECTION(+5V VPOS1,
DC MEASURE)
9-PIN D-SUB CONNECTION(VCO AND PLL PROGRAMMING)
IEEE
Q CH
AGILENT DMM(FOR ISUPPLY MEAS.)
REF
E IEEE
IEEE
IEEE
IEEE
IEEE
6dB
RF1
AGILENT N8974ANOISE FIGURE ANALYZER
AGILENT 346BNOISE SOURCE
AGILENT 8665BLOW NOISE SYN
SIGNAL GENERATOR
10MHzLOW-PASS FILTER
RF
3dB
0957
6-05
1
IEEE
AGILENT 34980AMULTIFUNCTION
SWITCH(WITH 34950 AND 2×
34921 MODULES)
Figure 49. Noise Figure Characterization Setup
Data Sheet ADRF6801
Rev. A | Page 33 of 34
AGILENT E3631APOWER SUPPLY
REF
RF SWITCH MATRIX
ADRF6801EVALUATION BOARD
RF
6dB 3dB 6dB
I CH
10-PINCONNECTION(+5V VPOS1,
DC MEASURE)
9-PIN D-SUB CONNECTION(VCO AND PLL PROGRAMMING)
I E
IEEE
Q CH
AGILENT DMM(FOR ISUPPLY MEAS.)
REF
E IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
6dB
RF1
RF
3dB
AGILENT MXASPECTRUM ANALYZER
AGILENT E5052 SIGNAL SOURCEANALYZER
R&S SMA100SIGNAL GENERATOR
R&S SMA100SIGNAL GENERATOR
100MHzLOW-PASS FILTER
0957
6-05
2
IEEE
AGILENT 34980AMULTIFUNCTION
SWITCH(WITH 34950 AND 2×
34921 MODULES)
Figure 50. Phase Noise Characterization Setup
ADRF6801 Data Sheet
Rev. A | Page 34 of 34
OUTLINE DIMENSIONS
140
1011
3130
2120
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 06-0
1-20
12-D
0.50BSC
PIN 1INDICATOR
4.50 REF0.20 MIN0.50
0.400.30
TOP VIEW
12° MAX 0.80 MAX0.65 TYP
SEATINGPLANE
COPLANARITY0.08
1.000.850.80
0.300.230.18
0.05 MAX0.02 NOM
0.20 REF
4.254.10 SQ3.95
0.60 MAX
0.60 MAX
PIN 1INDICATOR
6.106.00 SQ5.90
5.855.75 SQ5.65
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.
EXPOSEDPAD
(BOTTOM VIEW)
Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad (CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity
ADRF6801ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1 750 ADRF6801-EVALZ Evaluation Board 1 Z = RoHS Compliant Part.
©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09576-0-6/18(A)