8 bit alu by xilinx.docx

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A PROJECT SYNOPSIS ON

DESIGN AND IMPLEMENTATIONOF A8-BIT ALU ON XILINX FPGA

USING VHDL

SUBMITTED BYDipanwita D

Diptan! Ma"!#$%Ja&a'(% Ba%#an

Ra")!#a% MannaSan! Sa#antaSa&ani D!tta

G!i$$ B&M%* A#%i) Ba'a)+A''t* P%,'',%.

Dpt* , ECE/ SMIT

SAROJ MOHAN INSTITUTE OF TECHNOLOGY+DEGREE DIVISION.

GUPTIPARA/ HOOGHLY

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OBJECTIVE

The main objective of our project is to design a 8 bit Arithmetic Logic Unit which isa digital circuit that performs arithmetic and logical operations using VHDL. The ALUis a fundamental building bloc of the central processing unit !"#U$ of a computer%

and even the simplest microprocessors contain one for purposes such asmaintaining timers. The processors found inside modern "#Us and graphicsprocessing units !Us$ accommodate ver' powerful and ver' comple( ALUs) asingle component ma' contain a number of ALUs. *athematician +ohn von,eumann proposed the ALU concept in -/0% when he wrote a report on thefoundations for a new computer called the 1DVA". 2esearch into ALUs remains animportant part of computer science% falling under Arithmetic and logic structures inthe A"* "omputing "lassification 3'stem. Here% ALU is designed using VHDL!VH34" hardware description language$ is a hardware description language used inelectronic design automation to describe digital and mi(ed signal s'stems such as

field5programmable gate arra's and integrated circuits.

INTRODUCTION

This paper deals with the design methodolog' of a 6#&A Arithmetic #rocessor usingVHDL to enhance the description% simulation and hardware reali7ation. The designand implementation of 6#&A based Arithmetic Logic Unit is of core significance indigital technologies as it is being an integral part of all microprocessors. As the namesuggests% this is a s'stem which is capable of performing not onl' arithmetic

operations but also computes logic functions and provides the output through gatingcircuitr'. All the modules described in the design are coded using VHDL which is aver' useful tool with its degree of concurrenc' to cope with the parallelism of digitalhardware. The top level module connects all the stages into a higher level. nceidentif'ing the individual approaches for input% output and other modules% the VHDLdescriptions are run through a VHDL simulator% followed b' the timing diagrams forthe verification% woring and performance of the above design along with thehardware implementation that shows the appropriateness of the design.

VHDL QUICK LOOKA digital s'stem in VHDL consists of a design entit' that can contain other entitiesthat are then considered components of the top5level entit'. 1ach entit' is modeledb' an entit' declaration and an architecture bod'. 3o a VHDL module has two partsnamel'% 1ntit' and Architecture as 6ig. -.

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6ig. -. VHDL *odule

Fundamental Concepts

The unif'ing factor is that we want to achieve ma(imum reliabilit' in the designprocess for minimum cost and design time. There are two aspects to modelinghardware that an' hardware description language facilitates) true abstract behaviorand hardware structure. A multitude of language or user defined data t'pes canbe used. This will mae models easier to write% clearer to read and avoidunnecessar' conversion functions that can clutter the code. The e' advantage ofVHDL% when used for s'stems design% is that it allows the behavior of the re9uireds'stem to be described !modeled$ and verified !simulated$ before s'nthesis toolstranslate the design into real hardware !gates and wires$. Another benefit is thatVHDL allows the description of a concurrent s'stem. VHDL is a dataflow language%unlie procedural computing languages such as :A34"% "% and assembl' code%which all run se9uentiall'% one instruction at a time. VHDL project is multipurposeand portable. :eing created for one element base% a computing device project canbe ported on another element base% for e(ample VL34 with various technologies.

Programming in VHDL

1ntit' Declaration;

4t defines the names% input output signals and modes of a hardware module.An entit' declaration should starts with entit' and ends with end e'words. #orts1 1 1 1are interfaced through which an entit' can communicate with its environment.1ach port must have a name% direction and a t'pe. An entit' ma' have no portdeclaration also. The direction will be input% output or inout.

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< 3'nta(;

entity entity_name isPort declaration;end entity_name;

< E2a#p34

Architecture Declaration

4t describes the internal description of design or it tells what is there inside design.1ach entit' has at least one architecture and an entit' can have man' architecture.Architecture can be described using structural% dataflow% behavioral or mi(ed st'le.Architecture can be used to describe a design at different levels of abstraction liegate level% register transfer level !2TL$ or behavior level.

< 3'nta(;

architecture architecture_name of entity_name

architecture_declarative_part;begin

Statements;end architecture_name;

Here we should specif' the entit' name for which we are writing the architecturebod'. The architecture statements should be inside the begin and end e'word.Architecture declarative part ma' contain variables% constants% or componentdeclaration.

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< E2a#p34

Spartan-3E FPGA Startr K!t "#ar$

6igure shows the actual 3partan5=1 6#&A 3tarter >it :oard which includes?"=3-@@1 device of 3partan5=1 famil'.

< *ain components;< -@@%@@@5gate ?ilin( 3partan5=1 ?"=3-@@1 6#&A< A /@5pin e(pansion connection port to gain access to the 3partan5=1 6#&A< 6our 5pin e(pansion connector ports to e(tend and enhance the 3partan5=13ample #ac< B Light 1mitting Diodes !L1Ds$< #ower 2egulators

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6ig.=;5 3partan5=1 6#&A 3tarter >it :oard

Field Programmable Gate rra! "FPG#

6#&As combine the programmabilit' of processors with the performance of customhardware. As the' become more common in critical embedded s'stems% newtechni9ues are necessar' to manage securit' in 6#&A designs. This article

discusses 6#&A securit' problems and current research on reconfigurable devicesand securit'% and presents securit' primitives and a component architecture forbuilding highl' secure s'stems on 6#&As. :ecause 6#&As can provide a usefulbalance between performance% rapid time to maret% and fle(ibilit'% the' havebecome the primar' source of computation in man' critical embedded s'stems.-,CThe aerospace industr'% for e(ample% relies on 6#&As to control ever'thing from the+oint 3trie 6ighter to the *ars 2over. 6ace recognition s'stems% wireless networs%intrusion detection s'stems% and supercomputers% all of which are emplo'ed in largesecurit' applications% also use 6#&As. 4n fact% in C@@0 alone% an estimated 8@%@@@different commercial 6#&A design projects began. :ecause major 4" manufacturersoutsource most of their operations%/ 4# theft from a foundr' is a serious concern.

6#&As provide a viable solution to this problem because the sensitive 4# is notloaded onto the device until after it has been manufactured and delivered% maing it

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harder for adversaries to target a specific application or user. 6urthermore% modern6#&As use bit stream encr'ption and other methods to protect 4# once it is loadedonto the 6#&A or e(ternal memor'. However% techni9ues be'ond bit streamencr'ption are necessar' to ensure 6#&A design securit'. To save time and mone'%6#&A s'stems are t'picall' cobbled together from a collection of e(isting

computational cores% often obtained from third parties.

6#&As are programmable semiconductor devices that are based around a matri( of"onfigurable Logic :locs !"L:s$ connected through programmable interconnects.As opposed to Application 3pecific 4ntegrated "ircuits !A34"s$% where the device iscustom built for the particular design% 6#&As can be programmed to the desiredapplication or functionalit' re9uirements. Although ne5 Time #rogrammable !T#$6#&As are available% the dominant t'pe are 32A* based which can bereprogrammed as the design evolves. 6#&As allow designers to change theirdesigns ver' late in the design c'cle even after the end product has beenmanufactured and deplo'ed in the field. 4n addition% ?ilin( 6#&As allow for field

upgrades to be completed remotel'% eliminating the costs associated with re5designing or manuall' updating electronic s'stems.

Fig.4. FPGA Block Structure

Common FPGA Features

6#&As have evolved far be'ond the basic capabilities present in their predecessors%

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and incorporate hard !A34" t'pe$ blocs of commonl' used functionalit' such as2A*% cloc management% and D3#. The following are the basic components in an6#&A;.


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< Hardware verview;

The fundamental building bloc of ALU is shown in 6ig. . Here bold dots !dipswitches$ indicate the inputs to an ALU which are selected b' the user. The inputcan either be - or @ indicating 0V and @ V respectivel'. A L"D is used to displa' -

bit output% whereas G indicates L1Ds which are used to show the status of carr' out%overflow% borrow and 7ero. The VHDL code which implies the hardware part of ALUis downloaded on 6#&A processor using +TA& cable interfacing #" and thehardware element.

6ig 0. Hardware representation of an 85bit ALU.

A final point is that when a VHDL model is translated into the gates and wires thatare mapped onto a programmable logic device such as a "#LD or 6#&A% and then itis the actual hardware being configured% rather than the VHDL code beinge(ecuted as if on some form of a processor chip.

< perational overview

The operational overview deals with two inds of operations which an ALU canperform. 6irst part deals with arithmetic computations and is referred to asArithmetic Unit. 4t is capable of addition% subtraction% multiplication% division%increment and decrement. The second part deals with the &ated results in the shapeof A,D% 2% ?2% inverter% rotate% left shift and right shift% which is referred to asLogic Unit. The functions are controlled and e(ecuted b' selecting operation orcontrol bits. A select input of 0 bit si7e that will accommodate up to =C operations issufficient to achieve the objectives. The operations selected b' the "ontrol Unit areshown in the 6ig. . Arithmetic part is 9uite comple( as compared to logic unit andinvolves an additional carr' input. *ultiplication and Division also increases thecomple(it' of ALU. 4n the Logic :loc% gates such as A,D% 2% ?2 and ,T

operations are shown. Logic :loc of ALU does not need as man' gates as re9uiredin Arithmetic Unit and if done separatel'% the L&4" unit can be implemented using

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"omple( #rogrammable Logic Devices !"#LD$ or other #rogrammable Logic Device!#LD$ technologies instead of using 6#&A.

6ig. ; &eneral operation ALU sub5blocs and control

units using multiple(ers

4n this method% an ALU is chopped into several segments each incorporating itsspecific operations. A model of this techni9ue containing Arithmetic% Logic%*ultiple(er and 3hift and 2otate Units are shown in 6ig ..

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6ig.B. :loc Diagram of ALU

6ig.8;diagram of 85bit ALU.

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< Truth Table DesignTruth table design is an effective method compiling all those functions that areneeded b' the user on a single platform. Table - indicates the combination of five bitcontrol input 3 I/ down to @J with their operation and functions that are used in ALU.Arithmetic% Logic and 3hifter units are separated in the table.

Table - ; "ombination of five bit control input 3 I/ down to @J with their operation andfunctions that are used in ALU.

E(amples )or arit*metic operations in L&

< :inar' Adder53ubtractor;

The most basic arithmetic operation is the addition of two binar' digits. This simpleaddition consists of four possible elementar' operations. @ K @ @% @ K - -% - K @ -% - K - -@. The first three operations produce sum of one digit% but when the bothaugends and addend bits are e9ual -% the binar' sum consists of two digits. Thehigher significant bit of the result is called carr' .Ehen the augends and addendnumber contains more significant digits% the carr' obtained from the addition of thetwo bits is called half adder. ne that performs the addition of three bits !twosignificant bits and a previous carr'$ is called half adder. The name of circuit is fromthe fact that two half adders can be emplo'ed to implement a full adder.A binar'adder5subtractor is a combinational circuit that performs the arithmetic operations ofaddition and subtraction with binar' numbers. "onnecting n full adders in cascadeproduces a binar' adder for two n5bit numbers.

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:inar' Adder;

A binar' adder is a digital circuit that produces the arithmetic sum of two binar'

numbers. 4t can be constructed with full adder connected in cascade% the outputcarr' from each full adder connected to the input carr' of the ne(t full adder in thechain. 6ig. / shows the interconnection of four full adder !6A$ circuits to provide a /bit binar' ripple carr' adder. The augends bits of A and addend bits of : aredesignated b' subscript

6ig.. :inar' Adder

numbers from right to left% with subscript @ denoting the least significant bit. Thecarries are connected in the chain through the full adders. The input carr' to theadder is "@ and it ripples through the full adder to the output carr' "/.The 3 outputgenerate the re9uired sum bits. An n5bit adder re9uires n full adders with each outputconnected to the input carr' of the ne(t higher order full adder.

:inar' 3ubtractor;

The subtraction of unsigned binar' numbers can be done most convenientl' b'means of complement. 3ubtraction A: can be done b' taing the C s complement1of : and adding it to A. The C s complement can be obtained b' taing the - s1 1complement and adding one to the least significant pair of bits. The - s complement1can be implemented with the inverters and a one can be added to the sum throughthe input carr'. The circuit for subtracting% A:% consists of an adder with inverterplaced between each data input : and the corresponding input of the full adder. Theinput carr' "@ must be e9ual to -when performing subtraction. The operation thusperformed becomes A% plus the - s complement of :% plus -.This is e9ual to A plus1C s complement of :. 6or unsigned numbers this gives A: if A M : or the C s1 1complement of !:A$ if A N :. for signed numbers% the result is A :% provided thatthere is no overflow.

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E(amples )or Logical operations in L&

4n a /5bit Arithmetic Logic Unit% logical operations are performed on individual bits.

1?52 &ate;

4n a / bit ALU% the inputs given are A@% A-% AC% A= and :@% :-% :C% :=. perationsare performed on individual bits. Thus% as shown in a fig.% inputs% A@ and :@ willgive output 6@.

Fig.10 Ex-OR Gate Table: Truth table for Ex-OR Gate

Implementation

The VHDL coding of this paper design is compiled and simulated using6#&A using ?ilin( 3partan ?"=3-@@1 it shown in 6ig.-- . The data is updated tothe it using two separate select inputs A and : each carr'ing 8 bits. The function of6#&A is embedded on the it along with #2*% L"D% L1Ds and D4# switches. A+oint Test Action &roup !+TA&$ interface connects the 6#&A chip with #2* andleads to #" through a serial interface. The structure of such a #2* assembl'?"-@3 is shown in 6ig-C.. 3ince 6#&A is user programmable% therefore +TA& is ofcore significance. #2* has several postulates in the shape of data storage anddebugging% permanent storage of data% consistenc' of operation% low cost% highspeed and compactness. #2* used in this design of ALU is O?"-@3P% which ise9uipped with the inbuilt circuitr' to support and store comple( functions. 4t supports

both mode of *aster and 3lave serial 6ield #rogrammable &ate Arra'.

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6ig.--;"ircuit design of 6#&A it.

4n real time application% after the process of compilation and simulation of the VHDLdesign% the hardware reali7ation is constructed and tested as shown in 6ig. -C. Herethe 85bit inputs are given b' means of two sets of D4# switches and the -5bit outputcan be displa'ed on a L"D panel and the result can be verified with the simulated

output. The status of the flag register is indicated b' a series of 85bit L1Ds. Theprovision of a select switch used in this hardware enables the user to perform there9uired operation on the 6#&A processor.

6ig.-C ; 2eal time hardware implementation

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CONCLUSION

VHDL i#p3#ntati,n , 8-5it a%it(#ti6 3,0i6 !nit +ALU. i' p%'nt$*T( $'i0n wa' i#p3#nt$ !'in0 VHDL Xi3in2 S&nt('i' t,,3 an$

ta%0t$ ,% Spa%tan $7i6* ALU wa' $'i0n$ t, p%,%# a%it(#ti6,p%ati,n' '!6( a' a$$iti,n an$ '!5t%a6ti,n !'in0 8-5it a't a$$%/3,0i6a3 ,p%ati,n' '!6( a' AND/ OR/ XOR an$ NOT ,p%ati,n'/ 9' an$:9' 6,#p3#nt ,p%ati,n' an$ 6,#pa% an$ #an& #,% ,p%ati,n'*

Hi0( 373 $'i0n #t(,$,3,0& a33,w' #ana0in0 t( $'i0n 6,#p32it&in a 5tt% wa& an$ %$!6' t( $'i0n 6&63* A (i0(-373 #,$3#a)' t( $'6%ipti,n an$ 7a3!ati,n , t( 6,#p32 '&'t#' a'i%*RTL $'6%ipti,n 'p6i;' a33 t( %0i't%' in a $'i0n/ an$ t(6,#5inati,na3 3,0i6 5twn t(#* T( %0i't%' a% $'6%i5$ it(%2p3i6it3& t(%,!0( 6,#p,nnt in'tantiati,n ,% i#p3i6it3& t(%,!0(

in%n6* T( 6,#5inati,na3 3,0i6 i' $'6%i5$ 5& 3,0i6a3

< = +ana, .#/p0!t Fw% 3in' , 6,$ i#p%,7' p%,$!6ti7it&an$ %$!6' %%,%*

< = In.ra $!,n r I#p3#ntati,n , in$pn$nt$'i0n' a' 633 3i5%a%& > %!' in 7a%i,!' #,$3'*

< = I/pr#5 5r!6.at!#n H3p' t, %!n p%,6'' a't%

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8 bit alu by xilinx.docx

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